1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/sysreg.h> 13 #include <asm/types.h> 14 15 /* 16 * Because I'm terribly lazy and that repainting the whole of the KVM 17 * code with the proper names is a pain, use a helper to map the names 18 * inherited from AArch32 with the new fancy nomenclature. One day... 19 */ 20 #define __HCR(x) HCR_EL2_##x 21 22 #define HCR_TID5 __HCR(TID5) 23 #define HCR_DCT __HCR(DCT) 24 #define HCR_ATA_SHIFT __HCR(ATA_SHIFT) 25 #define HCR_ATA __HCR(ATA) 26 #define HCR_TTLBOS __HCR(TTLBOS) 27 #define HCR_TTLBIS __HCR(TTLBIS) 28 #define HCR_ENSCXT __HCR(EnSCXT) 29 #define HCR_TOCU __HCR(TOCU) 30 #define HCR_AMVOFFEN __HCR(AMVOFFEN) 31 #define HCR_TICAB __HCR(TICAB) 32 #define HCR_TID4 __HCR(TID4) 33 #define HCR_FIEN __HCR(FIEN) 34 #define HCR_FWB __HCR(FWB) 35 #define HCR_NV2 __HCR(NV2) 36 #define HCR_AT __HCR(AT) 37 #define HCR_NV1 __HCR(NV1) 38 #define HCR_NV __HCR(NV) 39 #define HCR_API __HCR(API) 40 #define HCR_APK __HCR(APK) 41 #define HCR_TEA __HCR(TEA) 42 #define HCR_TERR __HCR(TERR) 43 #define HCR_TLOR __HCR(TLOR) 44 #define HCR_E2H __HCR(E2H) 45 #define HCR_ID __HCR(ID) 46 #define HCR_CD __HCR(CD) 47 #define HCR_RW __HCR(RW) 48 #define HCR_TRVM __HCR(TRVM) 49 #define HCR_HCD __HCR(HCD) 50 #define HCR_TDZ __HCR(TDZ) 51 #define HCR_TGE __HCR(TGE) 52 #define HCR_TVM __HCR(TVM) 53 #define HCR_TTLB __HCR(TTLB) 54 #define HCR_TPU __HCR(TPU) 55 #define HCR_TPC __HCR(TPCP) 56 #define HCR_TSW __HCR(TSW) 57 #define HCR_TACR __HCR(TACR) 58 #define HCR_TIDCP __HCR(TIDCP) 59 #define HCR_TSC __HCR(TSC) 60 #define HCR_TID3 __HCR(TID3) 61 #define HCR_TID2 __HCR(TID2) 62 #define HCR_TID1 __HCR(TID1) 63 #define HCR_TID0 __HCR(TID0) 64 #define HCR_TWE __HCR(TWE) 65 #define HCR_TWI __HCR(TWI) 66 #define HCR_DC __HCR(DC) 67 #define HCR_BSU __HCR(BSU) 68 #define HCR_BSU_IS __HCR(BSU_IS) 69 #define HCR_FB __HCR(FB) 70 #define HCR_VSE __HCR(VSE) 71 #define HCR_VI __HCR(VI) 72 #define HCR_VF __HCR(VF) 73 #define HCR_AMO __HCR(AMO) 74 #define HCR_IMO __HCR(IMO) 75 #define HCR_FMO __HCR(FMO) 76 #define HCR_PTW __HCR(PTW) 77 #define HCR_SWIO __HCR(SWIO) 78 #define HCR_VM __HCR(VM) 79 80 /* 81 * The bits we set in HCR: 82 * TLOR: Trap LORegion register accesses 83 * RW: 64bit by default, can be overridden for 32bit VMs 84 * TACR: Trap ACTLR 85 * TSC: Trap SMC 86 * TSW: Trap cache operations by set/way 87 * TWE: Trap WFE 88 * TWI: Trap WFI 89 * TIDCP: Trap L2CTLR/L2ECTLR 90 * BSU_IS: Upgrade barriers to the inner shareable domain 91 * FB: Force broadcast of all maintenance operations 92 * AMO: Override CPSR.A and enable signaling with VA 93 * IMO: Override CPSR.I and enable signaling with VI 94 * FMO: Override CPSR.F and enable signaling with VF 95 * SWIO: Turn set/way invalidates into set/way clean+invalidate 96 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 97 * TID3: Trap EL1 reads of group 3 ID registers 98 * TID1: Trap REVIDR_EL1, AIDR_EL1, and SMIDR_EL1 99 */ 100 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 101 HCR_BSU_IS | HCR_FB | HCR_TACR | \ 102 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 103 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID1) 104 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK) 105 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) 106 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H | HCR_AMO | HCR_IMO | HCR_FMO) 107 108 #define MPAMHCR_HOST_FLAGS 0 109 110 /* TCR_EL2 Registers bits */ 111 #define TCR_EL2_DS (1UL << 32) 112 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) 113 #define TCR_EL2_HPD (1 << 24) 114 #define TCR_EL2_HA (1 << 21) 115 #define TCR_EL2_TBI (1 << 20) 116 #define TCR_EL2_PS_SHIFT 16 117 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 118 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 119 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 120 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 121 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 122 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 123 #define TCR_EL2_T0SZ_MASK 0x3f 124 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 125 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK) 126 127 /* 128 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu. 129 * 130 * Note that when using 4K pages, we concatenate two first level page tables 131 * together. With 16K pages, we concatenate 16 first level page tables. 132 * 133 */ 134 135 /* 136 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 137 * Interestingly, it depends on the page size. 138 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 139 * 140 * ----------------------------------------- 141 * | Entry level | 4K | 16K/64K | 142 * ------------------------------------------ 143 * | Level: 0 | 2 | - | 144 * ------------------------------------------ 145 * | Level: 1 | 1 | 2 | 146 * ------------------------------------------ 147 * | Level: 2 | 0 | 1 | 148 * ------------------------------------------ 149 * | Level: 3 | - | 0 | 150 * ------------------------------------------ 151 * 152 * The table roughly translates to : 153 * 154 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 155 * 156 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 157 * TGRAN_SL0_BASE(4K) = 2 158 * TGRAN_SL0_BASE(16K) = 3 159 * TGRAN_SL0_BASE(64K) = 3 160 * provided we take care of ruling out the unsupported cases and 161 * Entry_Level = 4 - Number_of_levels. 162 * 163 */ 164 #ifdef CONFIG_ARM64_64K_PAGES 165 166 #define VTCR_EL2_TGRAN 64K 167 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 168 169 #elif defined(CONFIG_ARM64_16K_PAGES) 170 171 #define VTCR_EL2_TGRAN 16K 172 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 173 174 #else /* 4K */ 175 176 #define VTCR_EL2_TGRAN 4K 177 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 178 179 #endif 180 181 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 182 FIELD_PREP(VTCR_EL2_SL0, (VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels)))) 183 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 184 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 185 #define VTCR_EL2_LVLS(vtcr) \ 186 VTCR_EL2_SL0_TO_LVLS(FIELD_GET(VTCR_EL2_SL0, (vtcr))) 187 188 #define VTCR_EL2_FLAGS (SYS_FIELD_PREP_ENUM(VTCR_EL2, SH0, INNER) | \ 189 SYS_FIELD_PREP_ENUM(VTCR_EL2, ORGN0, WBWA) | \ 190 SYS_FIELD_PREP_ENUM(VTCR_EL2, IRGN0, WBWA) | \ 191 SYS_FIELD_PREP_ENUM(VTCR_EL2, TG0, VTCR_EL2_TGRAN) | \ 192 VTCR_EL2_RES1) 193 194 #define VTCR_EL2_IPA(vtcr) (64 - FIELD_GET(VTCR_EL2_T0SZ, (vtcr))) 195 196 /* 197 * ARM VMSAv8-64 defines an algorithm for finding the translation table 198 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 199 * 200 * The algorithm defines the expectations on the translation table 201 * addresses for each level, based on PAGE_SIZE, entry level 202 * and the translation table size (T0SZ). The variable "x" in the 203 * algorithm determines the alignment of a table base address at a given 204 * level and thus determines the alignment of VTTBR:BADDR for stage2 205 * page table entry level. 206 * Since the number of bits resolved at the entry level could vary 207 * depending on the T0SZ, the value of "x" is defined based on a 208 * Magic constant for a given PAGE_SIZE and Entry Level. The 209 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 210 * x = PAGE_SHIFT). 211 * 212 * The value of "x" for entry level is calculated as : 213 * x = Magic_N - T0SZ 214 * 215 * where Magic_N is an integer depending on the page size and the entry 216 * level of the page table as below: 217 * 218 * -------------------------------------------- 219 * | Entry level | 4K 16K 64K | 220 * -------------------------------------------- 221 * | Level: 0 (4 levels) | 28 | - | - | 222 * -------------------------------------------- 223 * | Level: 1 (3 levels) | 37 | 31 | 25 | 224 * -------------------------------------------- 225 * | Level: 2 (2 levels) | 46 | 42 | 38 | 226 * -------------------------------------------- 227 * | Level: 3 (1 level) | - | 53 | 51 | 228 * -------------------------------------------- 229 * 230 * We have a magic formula for the Magic_N below: 231 * 232 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 233 * 234 * where Number_of_levels = (4 - Level). We are only interested in the 235 * value for Entry_Level for the stage2 page table. 236 * 237 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 238 * 239 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 240 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 241 * 242 * Here is one way to explain the Magic Formula: 243 * 244 * x = log2(Size_of_Entry_Level_Table) 245 * 246 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 247 * PAGE_SHIFT bits in the PTE, we have : 248 * 249 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 250 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 251 * where n = number of levels, and since each pointer is 8bytes, we have: 252 * 253 * x = Bits_Entry_Level + 3 254 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 255 * 256 * The only constraint here is that, we have to find the number of page table 257 * levels for a given IPA size (which we do, see stage2_pt_levels()) 258 */ 259 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 260 261 #define VTTBR_CNP_BIT (UL(1)) 262 #define VTTBR_VMID_SHIFT (UL(48)) 263 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 264 265 /* Hyp System Trap Register */ 266 #define HSTR_EL2_T(x) (1 << x) 267 268 /* Hyp Coprocessor Trap Register Shifts */ 269 #define CPTR_EL2_TFP_SHIFT 10 270 271 /* Hyp Coprocessor Trap Register */ 272 #define CPTR_EL2_TCPAC (1U << 31) 273 #define CPTR_EL2_TAM (1 << 30) 274 #define CPTR_EL2_TTA (1 << 20) 275 #define CPTR_EL2_TSM (1 << 12) 276 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 277 #define CPTR_EL2_TZ (1 << 8) 278 #define CPTR_NVHE_EL2_RES1 (BIT(13) | BIT(9) | GENMASK(7, 0)) 279 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ 280 GENMASK(29, 21) | \ 281 GENMASK(19, 14) | \ 282 BIT(11)) 283 284 #define CPTR_VHE_EL2_RES0 (GENMASK(63, 32) | \ 285 GENMASK(27, 26) | \ 286 GENMASK(23, 22) | \ 287 GENMASK(19, 18) | \ 288 GENMASK(15, 0)) 289 290 /* 291 * Polarity masks for HCRX_EL2, limited to the bits that we know about 292 * at this point in time. It doesn't mean that we actually *handle* 293 * them, but that at least those that are not advertised to a guest 294 * will be RES0 for that guest. 295 */ 296 #define __HCRX_EL2_MASK (BIT_ULL(6)) 297 #define __HCRX_EL2_nMASK (GENMASK_ULL(24, 14) | \ 298 GENMASK_ULL(11, 7) | \ 299 GENMASK_ULL(5, 0)) 300 #define __HCRX_EL2_RES0 ~(__HCRX_EL2_nMASK | __HCRX_EL2_MASK) 301 #define __HCRX_EL2_RES1 ~(__HCRX_EL2_nMASK | \ 302 __HCRX_EL2_MASK | \ 303 __HCRX_EL2_RES0) 304 305 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 306 #define HPFAR_MASK (~UL(0xf)) 307 /* 308 * We have 309 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 310 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 311 * 312 * Always assume 52 bit PA since at this point, we don't know how many PA bits 313 * the page table has been set up for. This should be safe since unused address 314 * bits in PAR are res0. 315 */ 316 #define PAR_TO_HPFAR(par) \ 317 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8) 318 319 #define FAR_TO_FIPA_OFFSET(far) ((far) & GENMASK_ULL(11, 0)) 320 321 #define ECN(x) { ESR_ELx_EC_##x, #x } 322 323 #define kvm_arm_exception_class \ 324 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 325 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 326 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 327 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 328 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 329 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 330 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 331 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 332 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET) 333 334 #define kvm_mode_names \ 335 { PSR_MODE_EL0t, "EL0t" }, \ 336 { PSR_MODE_EL1t, "EL1t" }, \ 337 { PSR_MODE_EL1h, "EL1h" }, \ 338 { PSR_MODE_EL2t, "EL2t" }, \ 339 { PSR_MODE_EL2h, "EL2h" }, \ 340 { PSR_MODE_EL3t, "EL3t" }, \ 341 { PSR_MODE_EL3h, "EL3h" }, \ 342 { PSR_AA32_MODE_USR, "32-bit USR" }, \ 343 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \ 344 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \ 345 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \ 346 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \ 347 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \ 348 { PSR_AA32_MODE_UND, "32-bit UND" }, \ 349 { PSR_AA32_MODE_SYS, "32-bit SYS" } 350 351 #endif /* __ARM64_KVM_ARM_H__ */ 352