1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_X86_H
3 #define ARCH_X86_KVM_X86_H
4
5 #include <linux/kvm_host.h>
6 #include <asm/fpu/xstate.h>
7 #include <asm/mce.h>
8 #include <asm/pvclock.h>
9 #include "msrs.h"
10 #include "mmu.h"
11 #include "regs.h"
12 #include "kvm_emulate.h"
13 #include "cpuid.h"
14
15 #define KVM_MAX_MCE_BANKS 32
16
17 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops);
18 void kvm_x86_vendor_exit(void);
19
20 void kvm_spurious_fault(void);
21
22 #define SIZE_OF_MEMSLOTS_HASHTABLE \
23 (sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES)
24
25 /* Sanity check the size of the memslot hash tables. */
26 static_assert(SIZE_OF_MEMSLOTS_HASHTABLE ==
27 (1024 * (1 + IS_ENABLED(CONFIG_X86_64)) * (1 + IS_ENABLED(CONFIG_KVM_SMM))));
28
29 /*
30 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation.
31 * Spilling over to an order-2 allocation isn't fundamentally problematic, but
32 * isn't expected to happen in the foreseeable future (O(years)). Assert that
33 * the size is an order-0 allocation when ignoring the memslot hash tables, to
34 * help detect and debug unexpected size increases.
35 */
36 #define KVM_SANITY_CHECK_VM_STRUCT_SIZE(x) \
37 do { \
38 BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) && \
39 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \
40 BUILD_BUG_ON(get_order(sizeof(struct x)) > 1 && \
41 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \
42 } while (0)
43
44 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
45 ({ \
46 bool failed = (consistency_check); \
47 if (failed) \
48 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
49 failed; \
50 })
51
52 #define KVM_DEFAULT_PLE_GAP 128
53 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
54 #define KVM_DEFAULT_PLE_WINDOW_GROW 2
55 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
56 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
57 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
58 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000
59
__grow_ple_window(unsigned int val,unsigned int base,unsigned int modifier,unsigned int max)60 static inline unsigned int __grow_ple_window(unsigned int val,
61 unsigned int base, unsigned int modifier, unsigned int max)
62 {
63 u64 ret = val;
64
65 if (modifier < 1)
66 return base;
67
68 if (modifier < base)
69 ret *= modifier;
70 else
71 ret += modifier;
72
73 return min(ret, (u64)max);
74 }
75
__shrink_ple_window(unsigned int val,unsigned int base,unsigned int modifier,unsigned int min)76 static inline unsigned int __shrink_ple_window(unsigned int val,
77 unsigned int base, unsigned int modifier, unsigned int min)
78 {
79 if (modifier < 1)
80 return base;
81
82 if (modifier < base)
83 val /= modifier;
84 else
85 val -= modifier;
86
87 return max(val, min);
88 }
89
90 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
91 int kvm_check_nested_events(struct kvm_vcpu *vcpu);
92
93 /* Forcibly leave the nested mode in cases like a vCPU reset */
kvm_leave_nested(struct kvm_vcpu * vcpu)94 static inline void kvm_leave_nested(struct kvm_vcpu *vcpu)
95 {
96 kvm_nested_call(leave_nested)(vcpu);
97 }
98
99 /*
100 * If IBRS is advertised to the vCPU, KVM must flush the indirect branch
101 * predictors when transitioning from L2 to L1, as L1 expects hardware (KVM in
102 * this case) to provide separate predictor modes. Bare metal isolates the host
103 * from the guest, but doesn't isolate different guests from one another (in
104 * this case L1 and L2). The exception is if bare metal supports same mode IBRS,
105 * which offers protection within the same mode, and hence protects L1 from L2.
106 */
kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu * vcpu)107 static inline void kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu *vcpu)
108 {
109 if (cpu_feature_enabled(X86_FEATURE_AMD_IBRS_SAME_MODE))
110 return;
111
112 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) ||
113 guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBRS))
114 indirect_branch_prediction_barrier();
115 }
116
117 /*
118 * Disallow modifying CPUID and feature MSRs, which affect the core virtual CPU
119 * model exposed to the guest and virtualized by KVM, if the vCPU has already
120 * run or is in guest mode (L2). In both cases, KVM has already consumed the
121 * current virtual CPU model, and doesn't support "unwinding" to react to the
122 * new model.
123 *
124 * Note, the only way is_guest_mode() can be true with 'last_vmentry_cpu == -1'
125 * is if userspace sets CPUID and feature MSRs (to enable VMX/SVM), then sets
126 * nested state, and then attempts to set CPUID and/or feature MSRs *again*.
127 */
kvm_can_set_cpuid_and_feature_msrs(struct kvm_vcpu * vcpu)128 static inline bool kvm_can_set_cpuid_and_feature_msrs(struct kvm_vcpu *vcpu)
129 {
130 return vcpu->arch.last_vmentry_cpu == -1 && !is_guest_mode(vcpu);
131 }
132
133 /*
134 * WARN if a nested VM-Enter is pending completion, and userspace hasn't gained
135 * control since the nested VM-Enter was initiated (in which case, userspace
136 * may have modified vCPU state to induce an architecturally invalid VM-Exit).
137 */
kvm_warn_on_nested_run_pending(struct kvm_vcpu * vcpu)138 static inline void kvm_warn_on_nested_run_pending(struct kvm_vcpu *vcpu)
139 {
140 WARN_ON_ONCE(vcpu->arch.nested_run_pending == KVM_NESTED_RUN_PENDING);
141 }
142
kvm_set_mp_state(struct kvm_vcpu * vcpu,int mp_state)143 static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state)
144 {
145 vcpu->arch.mp_state = mp_state;
146 if (mp_state == KVM_MP_STATE_RUNNABLE)
147 vcpu->arch.pv.pv_unhalted = false;
148 }
149
kvm_is_exception_pending(struct kvm_vcpu * vcpu)150 static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu)
151 {
152 return vcpu->arch.exception.pending ||
153 vcpu->arch.exception_vmexit.pending ||
154 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
155 }
156
kvm_clear_exception_queue(struct kvm_vcpu * vcpu)157 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
158 {
159 vcpu->arch.exception.pending = false;
160 vcpu->arch.exception.injected = false;
161 vcpu->arch.exception_vmexit.pending = false;
162 }
163
kvm_queue_interrupt(struct kvm_vcpu * vcpu,u8 vector,bool soft)164 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
165 bool soft)
166 {
167 vcpu->arch.interrupt.injected = true;
168 vcpu->arch.interrupt.soft = soft;
169 vcpu->arch.interrupt.nr = vector;
170 }
171
kvm_clear_interrupt_queue(struct kvm_vcpu * vcpu)172 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
173 {
174 vcpu->arch.interrupt.injected = false;
175 }
176
kvm_event_needs_reinjection(struct kvm_vcpu * vcpu)177 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
178 {
179 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
180 vcpu->arch.nmi_injected;
181 }
182
kvm_exception_is_soft(unsigned int nr)183 static inline bool kvm_exception_is_soft(unsigned int nr)
184 {
185 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
186 }
187
x86_exception_has_error_code(unsigned int vector)188 static inline bool x86_exception_has_error_code(unsigned int vector)
189 {
190 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
191 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
192 BIT(PF_VECTOR) | BIT(AC_VECTOR);
193
194 return (1U << vector) & exception_has_error_code;
195 }
196
vcpu_virt_addr_bits(struct kvm_vcpu * vcpu)197 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
198 {
199 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
200 }
201
max_host_virt_addr_bits(void)202 static inline u8 max_host_virt_addr_bits(void)
203 {
204 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48;
205 }
206
207 /*
208 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and
209 * IDT/GDT bases have static canonicality checks, the size of which depends
210 * only on the CPU's support for 5-level paging, rather than on the state of
211 * CR4.LA57. This applies to both WRMSR and to other instructions that set
212 * their values, e.g. SGDT.
213 *
214 * KVM passes through most of these MSRS and also doesn't intercept the
215 * instructions that set the hidden segment bases.
216 *
217 * Because of this, to be consistent with hardware, even if the guest doesn't
218 * have LA57 enabled in its CPUID, perform canonicality checks based on *host*
219 * support for 5 level paging.
220 *
221 * Finally, instructions which are related to MMU invalidation of a given
222 * linear address, also have a similar static canonical check on address.
223 * This allows for example to invalidate 5-level addresses of a guest from a
224 * host which uses 4-level paging.
225 */
is_noncanonical_address(u64 la,struct kvm_vcpu * vcpu,unsigned int flags)226 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu,
227 unsigned int flags)
228 {
229 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD))
230 return !__is_canonical_address(la, max_host_virt_addr_bits());
231 else
232 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
233 }
234
is_noncanonical_msr_address(u64 la,struct kvm_vcpu * vcpu)235 static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu)
236 {
237 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR);
238 }
239
is_noncanonical_base_address(u64 la,struct kvm_vcpu * vcpu)240 static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu)
241 {
242 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD);
243 }
244
is_noncanonical_invlpg_address(u64 la,struct kvm_vcpu * vcpu)245 static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu)
246 {
247 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG);
248 }
249
vcpu_cache_mmio_info(struct kvm_vcpu * vcpu,gva_t gva,gfn_t gfn,unsigned access)250 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
251 gva_t gva, gfn_t gfn, unsigned access)
252 {
253 u64 gen = kvm_vcpu_memslots(vcpu)->generation;
254
255 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
256 return;
257
258 /*
259 * If this is a shadow nested page table, the "GVA" is
260 * actually a nGPA.
261 */
262 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
263 vcpu->arch.mmio_access = access;
264 vcpu->arch.mmio_gfn = gfn;
265 vcpu->arch.mmio_gen = gen;
266 }
267
vcpu_match_mmio_gen(struct kvm_vcpu * vcpu)268 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
269 {
270 return vcpu->arch.mmio_gen == kvm_vcpu_memslots(vcpu)->generation;
271 }
272
273 /*
274 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
275 * clear all mmio cache info.
276 */
277 #define MMIO_GVA_ANY (~(gva_t)0)
278
vcpu_clear_mmio_info(struct kvm_vcpu * vcpu,gva_t gva)279 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
280 {
281 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
282 return;
283
284 vcpu->arch.mmio_gva = 0;
285 }
286
vcpu_match_mmio_gva(struct kvm_vcpu * vcpu,unsigned long gva)287 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
288 {
289 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
290 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
291 return true;
292
293 return false;
294 }
295
vcpu_match_mmio_gpa(struct kvm_vcpu * vcpu,gpa_t gpa)296 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
297 {
298 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
299 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
300 return true;
301
302 return false;
303 }
304
kvm_check_has_quirk(struct kvm * kvm,u64 quirk)305 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
306 {
307 return !(READ_ONCE(kvm->arch.disabled_quirks) & quirk);
308 }
309
kvm_request_l1tf_flush_l1d(void)310 static __always_inline void kvm_request_l1tf_flush_l1d(void)
311 {
312 #if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
313 /*
314 * Use a raw write to set the per-CPU flag, as KVM will ensure a flush
315 * even if preemption is currently enabled.. If the current vCPU task
316 * is migrated to a different CPU (or userspace runs the vCPU on a
317 * different task) before the next VM-Entry, then kvm_arch_vcpu_load()
318 * will request a flush on the new CPU.
319 */
320 raw_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1);
321 #endif
322 }
323
324 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
325
326 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
327
328 u64 get_kvmclock_ns(struct kvm *kvm);
329 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm);
330 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp);
331 int kvm_guest_time_update(struct kvm_vcpu *v);
332
333 void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value);
334 u64 kvm_scale_tsc(u64 tsc, u64 ratio);
335 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
336 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
337 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
338 u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc);
339 void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset);
340
adjust_tsc_offset_guest(struct kvm_vcpu * vcpu,s64 adjustment)341 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
342 s64 adjustment)
343 {
344 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.l1_tsc_offset + adjustment);
345 }
346
adjust_tsc_offset_host(struct kvm_vcpu * vcpu,s64 adjustment)347 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
348 {
349 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
350 WARN_ON(adjustment < 0);
351 adjustment = kvm_scale_tsc((u64) adjustment,
352 vcpu->arch.l1_tsc_scaling_ratio);
353 adjust_tsc_offset_guest(vcpu, adjustment);
354 }
355
356 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
357 gva_t addr, void *val, unsigned int bytes,
358 struct x86_exception *exception);
359
360 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
361 gva_t addr, void *val, unsigned int bytes,
362 struct x86_exception *exception);
363
364 int handle_ud(struct kvm_vcpu *vcpu);
365
366 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
367 struct kvm_queued_exception *ex);
368 void kvm_handle_exception_payload_quirk(struct kvm_vcpu *vcpu);
369
370 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
371 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
372 void *insn, int insn_len);
373 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
374 int emulation_type, void *insn, int insn_len);
375 /*
376 * EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
377 * userspace I/O) to indicate that the emulation context
378 * should be reused as is, i.e. skip initialization of
379 * emulation context, instruction fetch and decode.
380 *
381 * EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
382 * Indicates that only select instructions (tagged with
383 * EmulateOnUD) should be emulated (to minimize the emulator
384 * attack surface). See also EMULTYPE_TRAP_UD_FORCED.
385 *
386 * EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
387 * decode the instruction length. For use *only* by
388 * kvm_x86_ops.skip_emulated_instruction() implementations if
389 * EMULTYPE_COMPLETE_USER_EXIT is not set.
390 *
391 * EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
392 * retry native execution under certain conditions,
393 * Can only be set in conjunction with EMULTYPE_PF.
394 *
395 * EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
396 * triggered by KVM's magic "force emulation" prefix,
397 * which is opt in via module param (off by default).
398 * Bypasses EmulateOnUD restriction despite emulating
399 * due to an intercepted #UD (see EMULTYPE_TRAP_UD).
400 * Used to test the full emulator from userspace.
401 *
402 * EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
403 * backdoor emulation, which is opt in via module param.
404 * VMware backdoor emulation handles select instructions
405 * and reinjects the #GP for all other cases.
406 *
407 * EMULTYPE_PF - Set when an intercepted #PF triggers the emulation, in which case
408 * the CR2/GPA value pass on the stack is valid.
409 *
410 * EMULTYPE_COMPLETE_USER_EXIT - Set when the emulator should update interruptibility
411 * state and inject single-step #DBs after skipping
412 * an instruction (after completing userspace I/O).
413 *
414 * EMULTYPE_WRITE_PF_TO_SP - Set when emulating an intercepted page fault that
415 * is attempting to write a gfn that contains one or
416 * more of the PTEs used to translate the write itself,
417 * and the owning page table is being shadowed by KVM.
418 * If emulation of the faulting instruction fails and
419 * this flag is set, KVM will exit to userspace instead
420 * of retrying emulation as KVM cannot make forward
421 * progress.
422 *
423 * If emulation fails for a write to guest page tables,
424 * KVM unprotects (zaps) the shadow page for the target
425 * gfn and resumes the guest to retry the non-emulatable
426 * instruction (on hardware). Unprotecting the gfn
427 * doesn't allow forward progress for a self-changing
428 * access because doing so also zaps the translation for
429 * the gfn, i.e. retrying the instruction will hit a
430 * !PRESENT fault, which results in a new shadow page
431 * and sends KVM back to square one.
432 *
433 * EMULTYPE_SKIP_SOFT_INT - Set in combination with EMULTYPE_SKIP to only skip
434 * an instruction if it could generate a given software
435 * interrupt, which must be encoded via
436 * EMULTYPE_SET_SOFT_INT_VECTOR().
437 */
438 #define EMULTYPE_NO_DECODE (1 << 0)
439 #define EMULTYPE_TRAP_UD (1 << 1)
440 #define EMULTYPE_SKIP (1 << 2)
441 #define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
442 #define EMULTYPE_TRAP_UD_FORCED (1 << 4)
443 #define EMULTYPE_VMWARE_GP (1 << 5)
444 #define EMULTYPE_PF (1 << 6)
445 #define EMULTYPE_COMPLETE_USER_EXIT (1 << 7)
446 #define EMULTYPE_WRITE_PF_TO_SP (1 << 8)
447 #define EMULTYPE_SKIP_SOFT_INT (1 << 9)
448
449 #define EMULTYPE_SET_SOFT_INT_VECTOR(v) ((u32)((v) & 0xff) << 16)
450 #define EMULTYPE_GET_SOFT_INT_VECTOR(e) (((e) >> 16) & 0xff)
451
kvm_can_emulate_event_vectoring(int emul_type)452 static inline bool kvm_can_emulate_event_vectoring(int emul_type)
453 {
454 return !(emul_type & EMULTYPE_PF);
455 }
456
457 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
458 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
459 void *insn, int insn_len);
460 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu,
461 u64 *data, u8 ndata);
462 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu);
463
464 void kvm_prepare_event_vectoring_exit(struct kvm_vcpu *vcpu, gpa_t gpa);
465 void kvm_prepare_unexpected_reason_exit(struct kvm_vcpu *vcpu, u64 exit_reason);
466
467 fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu);
468 fastpath_t handle_fastpath_invd(struct kvm_vcpu *vcpu);
469
470 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
471 int kvm_emulate_invd(struct kvm_vcpu *vcpu);
472 int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
473 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
474 int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
475
476 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
477 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
478 int kvm_emulate_halt(struct kvm_vcpu *vcpu);
479 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu);
480 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
481 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
482
483 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
484
485 enum kvm_task_switch_reason {
486 TASK_SWITCH_CALL = 0,
487 TASK_SWITCH_IRET = 1,
488 TASK_SWITCH_JMP = 2,
489 TASK_SWITCH_GATE = 3,
490 };
491 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
492 int reason, bool has_error_code, u32 error_code);
493
494 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
495 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
496 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
497
498 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
499 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
500
501 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
502 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
503 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
504 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned int nr,
505 bool has_error_code, u32 error_code);
506 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault,
507 bool from_hardware);
508 void __kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
509 struct x86_exception *fault,
510 bool from_hardware);
511
kvm_inject_emulated_page_fault(struct kvm_vcpu * vcpu,struct x86_exception * fault)512 static inline void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
513 struct x86_exception *fault)
514 {
515 __kvm_inject_emulated_page_fault(vcpu, fault, false);
516 }
517
518 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
519
kvm_inject_gp(struct kvm_vcpu * vcpu,u32 error_code)520 static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
521 {
522 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
523 }
524
525 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
526 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu);
527
528 void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
529 u32 size);
530 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages);
531
532 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
533 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
534
535 enum kvm_apicv_inhibit {
536
537 /********************************************************************/
538 /* INHIBITs that are relevant to both Intel's APICv and AMD's AVIC. */
539 /********************************************************************/
540
541 /*
542 * APIC acceleration is disabled by a module parameter
543 * and/or not supported in hardware.
544 */
545 APICV_INHIBIT_REASON_DISABLED,
546
547 /*
548 * APIC acceleration is inhibited because AutoEOI feature is
549 * being used by a HyperV guest.
550 */
551 APICV_INHIBIT_REASON_HYPERV,
552
553 /*
554 * APIC acceleration is inhibited because the userspace didn't yet
555 * enable the kernel/split irqchip.
556 */
557 APICV_INHIBIT_REASON_ABSENT,
558
559 /* APIC acceleration is inhibited because KVM_GUESTDBG_BLOCKIRQ
560 * (out of band, debug measure of blocking all interrupts on this vCPU)
561 * was enabled, to avoid AVIC/APICv bypassing it.
562 */
563 APICV_INHIBIT_REASON_BLOCKIRQ,
564
565 /*
566 * APICv is disabled because not all vCPUs have a 1:1 mapping between
567 * APIC ID and vCPU, _and_ KVM is not applying its x2APIC hotplug hack.
568 */
569 APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED,
570
571 /*
572 * For simplicity, the APIC acceleration is inhibited
573 * first time either APIC ID or APIC base are changed by the guest
574 * from their reset values.
575 */
576 APICV_INHIBIT_REASON_APIC_ID_MODIFIED,
577 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED,
578
579 /******************************************************/
580 /* INHIBITs that are relevant only to the AMD's AVIC. */
581 /******************************************************/
582
583 /*
584 * AVIC is inhibited on a vCPU because it runs a nested guest.
585 *
586 * This is needed because unlike APICv, the peers of this vCPU
587 * cannot use the doorbell mechanism to signal interrupts via AVIC when
588 * a vCPU runs nested.
589 */
590 APICV_INHIBIT_REASON_NESTED,
591
592 /*
593 * On SVM, the wait for the IRQ window is implemented with pending vIRQ,
594 * which cannot be injected when the AVIC is enabled, thus AVIC
595 * is inhibited while KVM waits for IRQ window.
596 */
597 APICV_INHIBIT_REASON_IRQWIN,
598
599 /*
600 * PIT (i8254) 're-inject' mode, relies on EOI intercept,
601 * which AVIC doesn't support for edge triggered interrupts.
602 */
603 APICV_INHIBIT_REASON_PIT_REINJ,
604
605 /*
606 * AVIC is disabled because SEV doesn't support it.
607 */
608 APICV_INHIBIT_REASON_SEV,
609
610 /*
611 * AVIC is disabled because not all vCPUs with a valid LDR have a 1:1
612 * mapping between logical ID and vCPU.
613 */
614 APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED,
615
616 /*
617 * AVIC is disabled because the vCPU's APIC ID is beyond the max
618 * supported by AVIC/x2AVIC, i.e. the vCPU is unaddressable.
619 */
620 APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG,
621
622 NR_APICV_INHIBIT_REASONS,
623 };
624
625 #define __APICV_INHIBIT_REASON(reason) \
626 { BIT(APICV_INHIBIT_REASON_##reason), #reason }
627
628 #define APICV_INHIBIT_REASONS \
629 __APICV_INHIBIT_REASON(DISABLED), \
630 __APICV_INHIBIT_REASON(HYPERV), \
631 __APICV_INHIBIT_REASON(ABSENT), \
632 __APICV_INHIBIT_REASON(BLOCKIRQ), \
633 __APICV_INHIBIT_REASON(PHYSICAL_ID_ALIASED), \
634 __APICV_INHIBIT_REASON(APIC_ID_MODIFIED), \
635 __APICV_INHIBIT_REASON(APIC_BASE_MODIFIED), \
636 __APICV_INHIBIT_REASON(NESTED), \
637 __APICV_INHIBIT_REASON(IRQWIN), \
638 __APICV_INHIBIT_REASON(PIT_REINJ), \
639 __APICV_INHIBIT_REASON(SEV), \
640 __APICV_INHIBIT_REASON(LOGICAL_ID_ALIASED), \
641 __APICV_INHIBIT_REASON(PHYSICAL_ID_TOO_BIG)
642
643 bool kvm_apicv_activated(struct kvm *kvm);
644 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu);
645 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
646 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
647 enum kvm_apicv_inhibit reason, bool set);
648 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
649 enum kvm_apicv_inhibit reason, bool set);
650
kvm_set_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)651 static inline void kvm_set_apicv_inhibit(struct kvm *kvm,
652 enum kvm_apicv_inhibit reason)
653 {
654 kvm_set_or_clear_apicv_inhibit(kvm, reason, true);
655 }
656
kvm_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason)657 static inline void kvm_clear_apicv_inhibit(struct kvm *kvm,
658 enum kvm_apicv_inhibit reason)
659 {
660 kvm_set_or_clear_apicv_inhibit(kvm, reason, false);
661 }
662
663 void kvm_inc_or_dec_irq_window_inhibit(struct kvm *kvm, bool inc);
664
kvm_inc_apicv_irq_window_req(struct kvm * kvm)665 static inline void kvm_inc_apicv_irq_window_req(struct kvm *kvm)
666 {
667 kvm_inc_or_dec_irq_window_inhibit(kvm, true);
668 }
669
kvm_dec_apicv_irq_window_req(struct kvm * kvm)670 static inline void kvm_dec_apicv_irq_window_req(struct kvm *kvm)
671 {
672 kvm_inc_or_dec_irq_window_inhibit(kvm, false);
673 }
674
675 void kvm_make_scan_ioapic_request(struct kvm *kvm);
676 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
677 unsigned long *vcpu_bitmap);
678
679 void kvm_setup_xss_caps(void);
680
681 /*
682 * Get a filtered version of KVM's supported XCR0 that strips out dynamic
683 * features for which the current process doesn't (yet) have permission to use.
684 * This is intended to be used only when enumerating support to userspace,
685 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be
686 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if
687 * userspace attempts to enable unpermitted features.
688 */
kvm_get_filtered_xcr0(void)689 static inline u64 kvm_get_filtered_xcr0(void)
690 {
691 u64 permitted_xcr0 = kvm_caps.supported_xcr0;
692
693 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
694
695 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) {
696 permitted_xcr0 &= xstate_get_guest_group_perm();
697
698 /*
699 * Treat XTILE_CFG as unsupported if the current process isn't
700 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in
701 * XCR0 without setting XTILE_DATA is architecturally illegal.
702 */
703 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA))
704 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG;
705 }
706 return permitted_xcr0;
707 }
708
kvm_mpx_supported(void)709 static inline bool kvm_mpx_supported(void)
710 {
711 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
712 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
713 }
714
715 extern unsigned int min_timer_period_us;
716
717 extern bool enable_vmware_backdoor;
718
719 extern int pi_inject_timer;
720
nsec_to_cycles(struct kvm_vcpu * vcpu,u64 nsec)721 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
722 {
723 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
724 vcpu->arch.virtual_tsc_shift);
725 }
726
727 /* Same "calling convention" as do_div:
728 * - divide (n << 32) by base
729 * - put result in n
730 * - return remainder
731 */
732 #define do_shl32_div32(n, base) \
733 ({ \
734 u32 __quot, __rem; \
735 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
736 : "rm" (base), "0" (0), "1" ((u32) n)); \
737 n = __quot; \
738 __rem; \
739 })
740
kvm_disable_exits(struct kvm * kvm,u64 mask)741 static inline void kvm_disable_exits(struct kvm *kvm, u64 mask)
742 {
743 kvm->arch.disabled_exits |= mask;
744 }
745
kvm_mwait_in_guest(struct kvm * kvm)746 static inline bool kvm_mwait_in_guest(struct kvm *kvm)
747 {
748 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_MWAIT;
749 }
750
kvm_hlt_in_guest(struct kvm * kvm)751 static inline bool kvm_hlt_in_guest(struct kvm *kvm)
752 {
753 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_HLT;
754 }
755
kvm_pause_in_guest(struct kvm * kvm)756 static inline bool kvm_pause_in_guest(struct kvm *kvm)
757 {
758 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_PAUSE;
759 }
760
kvm_cstate_in_guest(struct kvm * kvm)761 static inline bool kvm_cstate_in_guest(struct kvm *kvm)
762 {
763 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_CSTATE;
764 }
765
kvm_aperfmperf_in_guest(struct kvm * kvm)766 static inline bool kvm_aperfmperf_in_guest(struct kvm *kvm)
767 {
768 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_APERFMPERF;
769 }
770
kvm_notify_vmexit_enabled(struct kvm * kvm)771 static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
772 {
773 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
774 }
775
kvm_before_interrupt(struct kvm_vcpu * vcpu,enum kvm_intr_type intr)776 static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
777 enum kvm_intr_type intr)
778 {
779 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
780 }
781
kvm_after_interrupt(struct kvm_vcpu * vcpu)782 static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
783 {
784 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
785 }
786
kvm_handling_nmi_from_guest(struct kvm_vcpu * vcpu)787 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
788 {
789 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
790 }
791
kvm_pat_valid(u64 data)792 static inline bool kvm_pat_valid(u64 data)
793 {
794 if (data & 0xF8F8F8F8F8F8F8F8ull)
795 return false;
796 /* 0, 1, 4, 5, 6, 7 are valid values. */
797 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
798 }
799
__kvm_pv_async_pf_enabled(u64 data)800 static inline bool __kvm_pv_async_pf_enabled(u64 data)
801 {
802 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
803
804 return (data & mask) == mask;
805 }
806
kvm_pv_async_pf_enabled(struct kvm_vcpu * vcpu)807 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
808 {
809 return __kvm_pv_async_pf_enabled(vcpu->arch.apf.msr_en_val);
810 }
811
kvm_async_pf_hash_reset(struct kvm_vcpu * vcpu)812 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
813 {
814 int i;
815 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
816 vcpu->arch.apf.gfns[i] = ~0;
817 }
818
819 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
820
821 /*
822 * Trigger machine check on the host. We assume all the MSRs are already set up
823 * by the CPU and that we still run on the same CPU as the MCE occurred on.
824 * We pass a fake environment to the machine check handler because we want
825 * the guest to be always treated like user space, no matter what context
826 * it used internally.
827 */
kvm_machine_check(void)828 static inline void kvm_machine_check(void)
829 {
830 #if defined(CONFIG_X86_MCE)
831 struct pt_regs regs = {
832 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
833 .flags = X86_EFLAGS_IF,
834 };
835
836 do_machine_check(®s);
837 #endif
838 }
839
840 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
841 struct x86_exception *e);
842 void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid);
843 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
844
845 int kvm_sev_es_mmio(struct kvm_vcpu *vcpu, bool is_write, gpa_t gpa,
846 unsigned int bytes, void *data);
847 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
848 unsigned int port, void *data, unsigned int count,
849 int in);
850
__kvm_prepare_emulated_mmio_exit(struct kvm_vcpu * vcpu,gpa_t gpa,unsigned int len,const void * data,bool is_write)851 static inline void __kvm_prepare_emulated_mmio_exit(struct kvm_vcpu *vcpu,
852 gpa_t gpa, unsigned int len,
853 const void *data,
854 bool is_write)
855 {
856 struct kvm_run *run = vcpu->run;
857
858 KVM_BUG_ON(len > 8, vcpu->kvm);
859
860 run->mmio.len = len;
861 run->mmio.is_write = is_write;
862 run->exit_reason = KVM_EXIT_MMIO;
863 run->mmio.phys_addr = gpa;
864 if (is_write)
865 memcpy(run->mmio.data, data, len);
866 }
867
kvm_prepare_emulated_mmio_exit(struct kvm_vcpu * vcpu,struct kvm_mmio_fragment * frag)868 static inline void kvm_prepare_emulated_mmio_exit(struct kvm_vcpu *vcpu,
869 struct kvm_mmio_fragment *frag)
870 {
871 WARN_ON_ONCE(!vcpu->mmio_needed || !vcpu->mmio_nr_fragments);
872
873 __kvm_prepare_emulated_mmio_exit(vcpu, frag->gpa, min(8u, frag->len),
874 frag->data, vcpu->mmio_is_write);
875 }
876
kvm_is_valid_map_gpa_range_ret(u64 hypercall_ret)877 static inline bool kvm_is_valid_map_gpa_range_ret(u64 hypercall_ret)
878 {
879 return !hypercall_ret || hypercall_ret == EINVAL ||
880 hypercall_ret == EAGAIN;
881 }
882
user_exit_on_hypercall(struct kvm * kvm,unsigned long hc_nr)883 static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr)
884 {
885 return kvm->arch.hypercall_exit_enabled & BIT(hc_nr);
886 }
887
888 int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl,
889 int (*complete_hypercall)(struct kvm_vcpu *));
890
891 #define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall) \
892 ({ \
893 int __ret; \
894 __ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall); \
895 \
896 if (__ret > 0) \
897 __ret = complete_hypercall(_vcpu); \
898 __ret; \
899 })
900
901 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
902
903 #endif
904