| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.h | 70 LiveRangeStage Stage = RS_New; member
92 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
97 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
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| H A D | ModuloSchedule.cpp | 1638 int Stage = getStage(MI); in filterInstructions() local
1663 MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage) { in moveStageBetweenBlocks()
1818 unsigned Stage = Schedule.getNumStages() - 1 + I - J; in peelPrologAndEpilogs() local
1951 int Stage = getStage(MI); in rewriteUsesOf() local
2831 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { in parseSymbolString()
2855 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
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| H A D | MLRegallocPriorityAdvisor.cpp | |
| H A D | MLRegAllocPriorityAdvisor.cpp | 330 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriorityImpl() local
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| H A D | RegAllocGreedy.cpp | 425 auto Stage = ExtraInfo->getOrInitStage(Reg); in enqueue() local
442 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriority() local
2584 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); in selectOrSplitImpl() local
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| H A D | MachinePipeliner.cpp | 1346 for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); in computeScheduledInsts() local
1711 const auto Stage = Stages[MI]; in computeMaxSetPressure() local
4249 int Stage = Schedule.stageScheduled(SU); in isValidSchedule() local
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| H A D | MachineSink.cpp | 884 for (unsigned Stage = CycleSinkStage::COPY; Stage != CycleSinkStage::END; in run() local
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| /freebsd/contrib/llvm-project/llvm/lib/DWARFLinker/Parallel/ |
| H A D | DWARFLinkerCompileUnit.h | 56 enum class Stage : uint8_t { enum
101 void setStage(Stage Stage) { this->Stage = Stage; } in setStage() argument
717 std::atomic<Stage> Stage; variable
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 94 DenseMap<MachineInstr *, int> Stage; variable
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | DXContainerPSVInfo.cpp | 149 void PSVRuntimeInfo::finalize(Triple::EnvironmentType Stage) { in finalize()
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| /freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | DXContainerYAML.cpp | 237 uint16_t Stage) in PSVInfo()
338 Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage); in mapping() local
592 Triple::EnvironmentType Stage = dxbc::getShaderStage(Info.ShaderStage); in mapInfoForVersion() local
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DFAPacketizerEmitter.cpp | 278 for (NfaStateTy Stage : InsnClass) { in emitForItineraries() local
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| H A D | SubtargetEmitter.cpp | 352 const Record *Stage = StageList[I]; in formItineraryStageString() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local
471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DXILLegalizePass.cpp | 575 for (int Stage = 0; Stage < NumStages; ++Stage) { in runLegalizationPipeline() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 613 enum InstrStage Stage; variable
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 964 auto Stage = createSchedStage(S.getCurrentStage()); in runSchedStages() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | DXContainer.h | 348 void swapBytes(Triple::EnvironmentType Stage) { in swapBytes()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaHLSL.cpp | 853 const Attr *A, llvm::Triple::EnvironmentType Stage, in DiagnoseAttrStageMismatch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 6669 for (int Stage = 0, StageEnd = SMS.getMaxStageCount(); Stage <= StageEnd; in tooMuchRegisterPressure() local
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| H A D | ARMISelDAGToDAG.cpp | 2811 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { in SelectMVE_VLD() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20918 for (unsigned Stage = 0; Stage != 6; ++Stage) { in computeGREVOrGORC() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5471 for (unsigned Stage = 0; Stage != Repetitions; ++Stage) { in createPackShuffleMask() local
|