| /freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
| H A D | DXContainerYAML.cpp | 53 uint16_t Stage) in PSVInfo()
154 Triple::EnvironmentType Stage = dxbc::getShaderStage(PSV.Info.ShaderStage); in mapping() local
279 Triple::EnvironmentType Stage = dxbc::getShaderStage(Info.ShaderStage); in mapInfoForVersion() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.h | 68 LiveRangeStage Stage = RS_New; member
90 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
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| H A D | ModuloSchedule.cpp | 1619 int Stage = getStage(MI); in filterInstructions() local
1644 MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage) { in moveStageBetweenBlocks()
1799 unsigned Stage = Schedule.getNumStages() - 1 + I - J; in peelPrologAndEpilogs() local
1932 int Stage = getStage(MI); in rewriteUsesOf() local
2796 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { in parseSymbolString()
2820 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
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| H A D | MLRegallocPriorityAdvisor.cpp | |
| H A D | MLRegAllocPriorityAdvisor.cpp | 299 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriorityImpl() local
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| H A D | RegAllocGreedy.cpp | 290 auto Stage = ExtraInfo->getOrInitStage(Reg); in enqueue() local
307 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriority() local
2437 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); in selectOrSplitImpl() local
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| H A D | MachinePipeliner.cpp | 1092 for (int Stage = 0, LastStage = Schedule.getMaxStageCount(); in computeScheduledInsts() local
1496 const auto Stage = Stages[MI]; in computeMaxSetPressure() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 94 DenseMap<MachineInstr *, int> Stage; variable
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | DXContainerPSVInfo.cpp | 150 void PSVRuntimeInfo::finalize(Triple::EnvironmentType Stage) { in finalize()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | DFAPacketizerEmitter.cpp | 277 for (NfaStateTy Stage : InsnClass) { in emitForItineraries() local
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| H A D | SubtargetEmitter.cpp | 364 const Record *Stage = StageList[i]; in FormItineraryStageString() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local
471 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaHLSL.cpp | 287 const Attr *A, llvm::Triple::EnvironmentType Stage, in DiagnoseAttrStageMismatch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 734 auto Stage = createSchedStage(S.getCurrentStage()); in runSchedStages() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 612 enum InstrStage Stage; variable
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| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | DXContainer.h | 247 void swapBytes(Triple::EnvironmentType Stage) { in swapBytes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2820 for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) { in SelectMVE_VLD() local
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| H A D | ARMBaseInstrInfo.cpp | 6886 for (int Stage = 0, StageEnd = SMS.getMaxStageCount(); Stage <= StageEnd; in tooMuchRegisterPressure() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 17793 for (unsigned Stage = 0; Stage != 6; ++Stage) { computeGREVOrGORC() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5176 for (unsigned Stage = 0; Stage != Repetitions; ++Stage) { in createPackShuffleMask() local
|