1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PCIE_DBI = 40, 24 TARGET_PTP = 41, 25 TARGET_QS = 42, 26 TARGET_QSYS = 46, 27 TARGET_REW = 47, 28 TARGET_SYS = 52, 29 TARGET_VCAP = 61, 30 NUM_TARGETS = 66 31 }; 32 33 #define __REG(...) __VA_ARGS__ 34 35 /* AFI:PORT_TBL:PORT_FRM_OUT */ 36 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 37 38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 40 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 41 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 42 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 43 44 /* AFI:PORT_TBL:PORT_CFG */ 45 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 46 47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 49 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 50 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 51 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 52 53 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 54 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 55 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 56 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 57 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 58 59 /* ANA:ANA:ADVLEARN */ 60 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 61 62 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 63 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 64 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 65 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 66 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 67 68 /* ANA:ANA:VLANMASK */ 69 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 70 71 /* ANA:ANA:ANAINTR */ 72 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 73 74 #define ANA_ANAINTR_INTR BIT(1) 75 #define ANA_ANAINTR_INTR_SET(x)\ 76 FIELD_PREP(ANA_ANAINTR_INTR, x) 77 #define ANA_ANAINTR_INTR_GET(x)\ 78 FIELD_GET(ANA_ANAINTR_INTR, x) 79 80 #define ANA_ANAINTR_INTR_ENA BIT(0) 81 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 82 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 83 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 84 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 85 86 /* ANA:ANA:AUTOAGE */ 87 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 88 89 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 90 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 91 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 92 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 93 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 94 95 /* ANA:ANA:MIRRORPORTS */ 96 #define ANA_MIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4) 97 98 #define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0) 99 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\ 100 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x) 101 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\ 102 FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x) 103 104 /* ANA:ANA:EMIRRORPORTS */ 105 #define ANA_EMIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4) 106 107 #define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0) 108 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\ 109 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 110 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\ 111 FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 112 113 /* ANA:ANA:FLOODING */ 114 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 115 116 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 117 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 118 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 119 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 120 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 121 122 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 123 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 124 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 125 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 126 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 127 128 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 129 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 130 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 131 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 132 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 133 134 /* ANA:ANA:FLOODING_IPMC */ 135 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 136 137 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 138 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 139 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 140 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 141 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 142 143 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 144 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 145 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 146 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 147 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 148 149 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 150 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 151 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 152 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 153 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 154 155 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 156 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 157 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 158 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 159 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 160 161 /* ANA:PGID:PGID */ 162 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 163 164 #define ANA_PGID_PGID GENMASK(8, 0) 165 #define ANA_PGID_PGID_SET(x)\ 166 FIELD_PREP(ANA_PGID_PGID, x) 167 #define ANA_PGID_PGID_GET(x)\ 168 FIELD_GET(ANA_PGID_PGID, x) 169 170 /* ANA:PGID:PGID_CFG */ 171 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 172 173 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 174 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 175 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 176 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 177 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 178 179 /* ANA:ANA_TABLES:MACHDATA */ 180 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 181 182 /* ANA:ANA_TABLES:MACLDATA */ 183 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 184 185 /* ANA:ANA_TABLES:MACACCESS */ 186 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 187 188 #define ANA_MACACCESS_CHANGE2SW BIT(17) 189 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 190 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 191 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 192 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 193 194 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 195 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 196 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 197 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 198 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 199 200 #define ANA_MACACCESS_VALID BIT(12) 201 #define ANA_MACACCESS_VALID_SET(x)\ 202 FIELD_PREP(ANA_MACACCESS_VALID, x) 203 #define ANA_MACACCESS_VALID_GET(x)\ 204 FIELD_GET(ANA_MACACCESS_VALID, x) 205 206 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 207 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 208 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 209 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 210 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 211 212 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 213 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 214 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 215 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 216 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 217 218 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 219 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 220 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 221 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 222 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 223 224 /* ANA:ANA_TABLES:MACTINDX */ 225 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 226 227 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 228 #define ANA_MACTINDX_BUCKET_SET(x)\ 229 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 230 #define ANA_MACTINDX_BUCKET_GET(x)\ 231 FIELD_GET(ANA_MACTINDX_BUCKET, x) 232 233 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 234 #define ANA_MACTINDX_M_INDEX_SET(x)\ 235 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 236 #define ANA_MACTINDX_M_INDEX_GET(x)\ 237 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 238 239 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 240 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 241 242 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 243 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 244 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 245 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 246 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 247 248 /* ANA:ANA_TABLES:VLANACCESS */ 249 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 250 251 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 252 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 253 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 254 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 255 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 256 257 /* ANA:ANA_TABLES:VLANTIDX */ 258 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 259 260 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 261 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 262 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 263 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 264 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 265 266 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 267 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 268 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 269 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 270 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 271 272 /* ANA:PORT:VLAN_CFG */ 273 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 274 275 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 276 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 277 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 278 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 279 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 280 281 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 282 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 283 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 284 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 285 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 286 287 #define ANA_VLAN_CFG_VLAN_PCP GENMASK(15, 13) 288 #define ANA_VLAN_CFG_VLAN_PCP_SET(x)\ 289 FIELD_PREP(ANA_VLAN_CFG_VLAN_PCP, x) 290 #define ANA_VLAN_CFG_VLAN_PCP_GET(x)\ 291 FIELD_GET(ANA_VLAN_CFG_VLAN_PCP, x) 292 293 #define ANA_VLAN_CFG_VLAN_DEI BIT(12) 294 #define ANA_VLAN_CFG_VLAN_DEI_SET(x)\ 295 FIELD_PREP(ANA_VLAN_CFG_VLAN_DEI, x) 296 #define ANA_VLAN_CFG_VLAN_DEI_GET(x)\ 297 FIELD_GET(ANA_VLAN_CFG_VLAN_DEI, x) 298 299 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 300 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 301 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 302 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 303 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 304 305 /* ANA:PORT:DROP_CFG */ 306 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 307 308 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 309 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 310 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 311 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 312 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 313 314 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 315 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 316 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 317 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 318 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 319 320 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 321 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 322 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 323 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 324 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 325 326 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 327 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 328 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 329 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 330 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 331 332 /* ANA:PORT:QOS_CFG */ 333 #define ANA_QOS_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 8, 0, 1, 4) 334 335 #define ANA_QOS_CFG_DP_DEFAULT_VAL BIT(8) 336 #define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\ 337 FIELD_PREP(ANA_QOS_CFG_DP_DEFAULT_VAL, x) 338 #define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\ 339 FIELD_GET(ANA_QOS_CFG_DP_DEFAULT_VAL, x) 340 341 #define ANA_QOS_CFG_QOS_DEFAULT_VAL GENMASK(7, 5) 342 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\ 343 FIELD_PREP(ANA_QOS_CFG_QOS_DEFAULT_VAL, x) 344 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\ 345 FIELD_GET(ANA_QOS_CFG_QOS_DEFAULT_VAL, x) 346 347 #define ANA_QOS_CFG_QOS_DSCP_ENA BIT(4) 348 #define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\ 349 FIELD_PREP(ANA_QOS_CFG_QOS_DSCP_ENA, x) 350 #define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\ 351 FIELD_GET(ANA_QOS_CFG_QOS_DSCP_ENA, x) 352 353 #define ANA_QOS_CFG_QOS_PCP_ENA BIT(3) 354 #define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\ 355 FIELD_PREP(ANA_QOS_CFG_QOS_PCP_ENA, x) 356 #define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\ 357 FIELD_GET(ANA_QOS_CFG_QOS_PCP_ENA, x) 358 359 #define ANA_QOS_CFG_DSCP_REWR_CFG GENMASK(1, 0) 360 #define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\ 361 FIELD_PREP(ANA_QOS_CFG_DSCP_REWR_CFG, x) 362 #define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\ 363 FIELD_GET(ANA_QOS_CFG_DSCP_REWR_CFG, x) 364 365 /* ANA:PORT:VCAP_CFG */ 366 #define ANA_VCAP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4) 367 368 #define ANA_VCAP_CFG_S1_ENA BIT(14) 369 #define ANA_VCAP_CFG_S1_ENA_SET(x)\ 370 FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x) 371 #define ANA_VCAP_CFG_S1_ENA_GET(x)\ 372 FIELD_GET(ANA_VCAP_CFG_S1_ENA, x) 373 374 /* ANA:PORT:VCAP_S1_KEY_CFG */ 375 #define ANA_VCAP_S1_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 16, r, 3, 4) 376 377 #define ANA_VCAP_S1_CFG_KEY_RT_CFG GENMASK(11, 9) 378 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\ 379 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 380 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\ 381 FIELD_GET(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 382 383 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG GENMASK(8, 6) 384 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\ 385 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 386 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\ 387 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 388 389 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG GENMASK(5, 3) 390 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\ 391 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 392 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\ 393 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 394 395 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG GENMASK(2, 0) 396 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\ 397 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 398 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\ 399 FIELD_GET(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 400 401 /* ANA:PORT:VCAP_S2_CFG */ 402 #define ANA_VCAP_S2_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4) 403 404 #define ANA_VCAP_S2_CFG_ISDX_ENA GENMASK(20, 19) 405 #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\ 406 FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x) 407 #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\ 408 FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x) 409 410 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA GENMASK(18, 17) 411 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\ 412 FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 413 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\ 414 FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 415 416 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA GENMASK(16, 15) 417 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\ 418 FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 419 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\ 420 FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 421 422 #define ANA_VCAP_S2_CFG_ENA BIT(14) 423 #define ANA_VCAP_S2_CFG_ENA_SET(x)\ 424 FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x) 425 #define ANA_VCAP_S2_CFG_ENA_GET(x)\ 426 FIELD_GET(ANA_VCAP_S2_CFG_ENA, x) 427 428 #define ANA_VCAP_S2_CFG_SNAP_DIS GENMASK(13, 12) 429 #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\ 430 FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x) 431 #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\ 432 FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x) 433 434 #define ANA_VCAP_S2_CFG_ARP_DIS GENMASK(11, 10) 435 #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\ 436 FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x) 437 #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\ 438 FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x) 439 440 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS GENMASK(9, 8) 441 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\ 442 FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 443 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\ 444 FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 445 446 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS GENMASK(7, 6) 447 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\ 448 FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 449 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\ 450 FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 451 452 #define ANA_VCAP_S2_CFG_IP6_CFG GENMASK(5, 2) 453 #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\ 454 FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x) 455 #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\ 456 FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x) 457 458 #define ANA_VCAP_S2_CFG_OAM_DIS GENMASK(1, 0) 459 #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\ 460 FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x) 461 #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\ 462 FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x) 463 464 /* ANA:PORT:QOS_PCP_DEI_MAP_CFG */ 465 #define ANA_PCP_DEI_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 32, r, 16, 4) 466 467 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL BIT(3) 468 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\ 469 FIELD_PREP(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x) 470 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\ 471 FIELD_GET(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x) 472 473 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL GENMASK(2, 0) 474 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\ 475 FIELD_PREP(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x) 476 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\ 477 FIELD_GET(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x) 478 479 /* ANA:PORT:CPU_FWD_CFG */ 480 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 481 482 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 483 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 484 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 485 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 486 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 487 488 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 489 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 490 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 491 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 492 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 493 494 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 495 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 496 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 497 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 498 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 499 500 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 501 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 502 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 503 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 504 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 505 506 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 507 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 508 509 /* ANA:PORT:PORT_CFG */ 510 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 511 512 #define ANA_PORT_CFG_SRC_MIRROR_ENA BIT(13) 513 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\ 514 FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 515 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\ 516 FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 517 518 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 519 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 520 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 521 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 522 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 523 524 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 525 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 526 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 527 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 528 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 529 530 #define ANA_PORT_CFG_RECV_ENA BIT(4) 531 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 532 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 533 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 534 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 535 536 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 537 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 538 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 539 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 540 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 541 542 /* ANA:COMMON:DSCP_REWR_CFG */ 543 #define ANA_DSCP_REWR_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 332, r, 16, 4) 544 545 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL GENMASK(5, 0) 546 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\ 547 FIELD_PREP(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x) 548 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\ 549 FIELD_GET(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x) 550 551 /* ANA:PORT:POL_CFG */ 552 #define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4) 553 554 #define ANA_POL_CFG_PORT_POL_ENA BIT(17) 555 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\ 556 FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x) 557 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\ 558 FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x) 559 560 #define ANA_POL_CFG_POL_ORDER GENMASK(8, 0) 561 #define ANA_POL_CFG_POL_ORDER_SET(x)\ 562 FIELD_PREP(ANA_POL_CFG_POL_ORDER, x) 563 #define ANA_POL_CFG_POL_ORDER_GET(x)\ 564 FIELD_GET(ANA_POL_CFG_POL_ORDER, x) 565 566 /* ANA:PFC:PFC_CFG */ 567 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 568 569 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 570 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 571 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 572 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 573 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 574 575 /* ANA:COMMON:AGGR_CFG */ 576 #define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4) 577 578 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6) 579 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ 580 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x) 581 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ 582 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x) 583 584 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5) 585 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ 586 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x) 587 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ 588 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x) 589 590 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4) 591 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ 592 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x) 593 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ 594 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x) 595 596 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3) 597 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ 598 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 599 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ 600 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 601 602 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2) 603 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ 604 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 605 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ 606 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 607 608 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1) 609 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ 610 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 611 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ 612 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 613 614 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0) 615 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ 616 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 617 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ 618 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 619 620 /* ANA:COMMON:DSCP_CFG */ 621 #define ANA_DSCP_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 76, r, 64, 4) 622 623 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) 624 #define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\ 625 FIELD_PREP(ANA_DSCP_CFG_DP_DSCP_VAL, x) 626 #define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\ 627 FIELD_GET(ANA_DSCP_CFG_DP_DSCP_VAL, x) 628 629 #define ANA_DSCP_CFG_QOS_DSCP_VAL GENMASK(10, 8) 630 #define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\ 631 FIELD_PREP(ANA_DSCP_CFG_QOS_DSCP_VAL, x) 632 #define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\ 633 FIELD_GET(ANA_DSCP_CFG_QOS_DSCP_VAL, x) 634 635 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) 636 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 637 FIELD_PREP(ANA_DSCP_CFG_DSCP_TRUST_ENA, x) 638 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 639 FIELD_GET(ANA_DSCP_CFG_DSCP_TRUST_ENA, x) 640 641 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) 642 #define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 643 FIELD_PREP(ANA_DSCP_CFG_DSCP_REWR_ENA, x) 644 #define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 645 FIELD_GET(ANA_DSCP_CFG_DSCP_REWR_ENA, x) 646 647 /* ANA:POL:POL_PIR_CFG */ 648 #define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4) 649 650 #define ANA_POL_PIR_CFG_PIR_RATE GENMASK(20, 6) 651 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\ 652 FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x) 653 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\ 654 FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x) 655 656 #define ANA_POL_PIR_CFG_PIR_BURST GENMASK(5, 0) 657 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\ 658 FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x) 659 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\ 660 FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x) 661 662 /* ANA:POL:POL_MODE_CFG */ 663 #define ANA_POL_MODE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4) 664 665 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA BIT(11) 666 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\ 667 FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 668 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\ 669 FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 670 671 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA BIT(10) 672 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\ 673 FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 674 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\ 675 FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 676 677 #define ANA_POL_MODE_IPG_SIZE GENMASK(9, 5) 678 #define ANA_POL_MODE_IPG_SIZE_SET(x)\ 679 FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x) 680 #define ANA_POL_MODE_IPG_SIZE_GET(x)\ 681 FIELD_GET(ANA_POL_MODE_IPG_SIZE, x) 682 683 #define ANA_POL_MODE_FRM_MODE GENMASK(4, 3) 684 #define ANA_POL_MODE_FRM_MODE_SET(x)\ 685 FIELD_PREP(ANA_POL_MODE_FRM_MODE, x) 686 #define ANA_POL_MODE_FRM_MODE_GET(x)\ 687 FIELD_GET(ANA_POL_MODE_FRM_MODE, x) 688 689 #define ANA_POL_MODE_OVERSHOOT_ENA BIT(0) 690 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\ 691 FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x) 692 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\ 693 FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x) 694 695 /* ANA:POL:POL_PIR_STATE */ 696 #define ANA_POL_PIR_STATE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4) 697 698 #define ANA_POL_PIR_STATE_PIR_LVL GENMASK(21, 0) 699 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\ 700 FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x) 701 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\ 702 FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x) 703 704 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 705 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 706 707 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 708 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 709 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 710 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 711 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 712 713 /* DEV:PORT_MODE:CLOCK_CFG */ 714 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 715 716 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 717 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 718 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 719 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 720 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 721 722 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 723 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 724 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 725 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 726 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 727 728 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 729 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 730 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 731 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 732 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 733 734 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 735 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 736 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 737 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 738 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 739 740 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 741 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 742 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 743 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 744 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 745 746 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 747 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 748 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 749 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 750 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 751 752 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 753 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 754 755 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 756 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 757 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 758 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 759 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 760 761 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 762 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 763 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 764 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 765 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 766 767 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 768 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 769 770 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 771 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 772 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 773 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 774 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 775 776 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 777 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 778 779 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 780 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 781 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 782 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 783 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 784 785 /* DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */ 786 #define DEV_MAC_TAGS_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4) 787 788 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1) 789 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\ 790 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 791 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\ 792 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 793 794 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 795 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 796 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 797 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 798 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 799 800 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 801 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 802 803 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 804 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 805 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 806 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 807 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 808 809 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 810 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 811 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 812 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 813 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 814 815 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 816 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 817 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 818 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 819 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 820 821 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 822 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 823 824 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 825 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 826 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 827 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 828 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 829 830 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 831 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 832 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 833 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 834 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 835 836 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 837 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 838 839 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 840 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 841 842 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 843 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 844 845 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 846 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 847 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 848 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 849 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 850 851 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 852 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 853 854 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 855 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 856 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 857 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 858 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 859 860 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 861 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 862 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 863 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 864 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 865 866 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 867 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 868 869 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 870 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 871 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 872 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 873 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 874 875 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 876 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 877 878 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 879 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 880 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 881 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 882 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 883 884 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 885 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 886 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 887 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 888 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 889 890 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 891 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 892 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 893 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 894 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 895 896 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 897 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 898 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 899 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 900 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 901 902 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 903 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 904 905 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 906 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 907 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 908 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 909 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 910 911 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 912 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 913 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 914 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 915 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 916 917 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 918 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 919 920 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 921 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 922 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 923 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 924 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 925 926 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 927 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 928 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 929 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 930 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 931 932 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 933 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 934 935 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 936 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 937 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 938 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 939 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 940 941 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 942 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 943 944 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 945 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 946 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 947 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 948 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 949 950 /* FDMA:FDMA:FDMA_CH_RELOAD */ 951 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 952 953 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 954 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 955 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 956 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 957 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 958 959 /* FDMA:FDMA:FDMA_CH_DISABLE */ 960 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 961 962 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 963 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 964 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 965 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 966 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 967 968 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 969 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 970 971 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 972 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 973 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 974 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 975 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 976 977 /* FDMA:FDMA:FDMA_DCB_LLP */ 978 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 979 980 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 981 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 982 983 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 984 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 985 986 /* FDMA:FDMA:FDMA_CH_CFG */ 987 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 988 989 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 990 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 991 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 992 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 993 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 994 995 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 996 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 997 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 998 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 999 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 1000 1001 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 1002 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 1003 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 1004 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 1005 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 1006 1007 #define FDMA_CH_CFG_CH_MEM BIT(0) 1008 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 1009 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 1010 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 1011 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 1012 1013 /* FDMA:FDMA:FDMA_CTRL */ 1014 #define FDMA_CTRL __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) 1015 1016 #define FDMA_CTRL_NRESET BIT(0) 1017 #define FDMA_CTRL_NRESET_SET(x)\ 1018 FIELD_PREP(FDMA_CTRL_NRESET, x) 1019 #define FDMA_CTRL_NRESET_GET(x)\ 1020 FIELD_GET(FDMA_CTRL_NRESET, x) 1021 1022 /* FDMA:FDMA:FDMA_PORT_CTRL */ 1023 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 1024 1025 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 1026 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 1027 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 1028 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 1029 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 1030 1031 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 1032 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 1033 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 1034 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 1035 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 1036 1037 /* FDMA:FDMA:FDMA_INTR_DB */ 1038 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 1039 1040 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 1041 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 1042 1043 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 1044 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 1045 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 1046 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 1047 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 1048 1049 /* FDMA:FDMA:FDMA_INTR_ERR */ 1050 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 1051 1052 /* FDMA:FDMA:FDMA_INTR_ENA */ 1053 #define FDMA_INTR_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 404, 0, 1, 4) 1054 1055 #define FDMA_INTR_ENA_INTR_PORT_ENA GENMASK(9, 8) 1056 #define FDMA_INTR_ENA_INTR_PORT_ENA_SET(x)\ 1057 FIELD_PREP(FDMA_INTR_ENA_INTR_PORT_ENA, x) 1058 #define FDMA_INTR_ENA_INTR_PORT_ENA_GET(x)\ 1059 FIELD_GET(FDMA_INTR_ENA_INTR_PORT_ENA, x) 1060 1061 #define FDMA_INTR_ENA_INTR_CH_ENA GENMASK(7, 0) 1062 #define FDMA_INTR_ENA_INTR_CH_ENA_SET(x)\ 1063 FIELD_PREP(FDMA_INTR_ENA_INTR_CH_ENA, x) 1064 #define FDMA_INTR_ENA_INTR_CH_ENA_GET(x)\ 1065 FIELD_GET(FDMA_INTR_ENA_INTR_CH_ENA, x) 1066 1067 /* FDMA:FDMA:FDMA_ERRORS */ 1068 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 1069 1070 /* PTP:PTP_CFG:PTP_PIN_INTR */ 1071 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 1072 1073 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 1074 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 1075 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 1076 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 1077 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 1078 1079 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 1080 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 1081 1082 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 1083 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 1084 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 1085 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 1086 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 1087 1088 /* PTP:PTP_CFG:PTP_DOM_CFG */ 1089 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 1090 1091 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 1092 #define PTP_DOM_CFG_ENA_SET(x)\ 1093 FIELD_PREP(PTP_DOM_CFG_ENA, x) 1094 #define PTP_DOM_CFG_ENA_GET(x)\ 1095 FIELD_GET(PTP_DOM_CFG_ENA, x) 1096 1097 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 1098 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 1099 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 1100 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 1101 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 1102 1103 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 1104 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 1105 1106 /* PTP:PTP_PINS:PTP_PIN_CFG */ 1107 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 1108 1109 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 1110 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 1111 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 1112 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 1113 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 1114 1115 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 1116 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 1117 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 1118 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 1119 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 1120 1121 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 1122 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 1123 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 1124 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 1125 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 1126 1127 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 1128 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 1129 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 1130 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 1131 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 1132 1133 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 1134 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 1135 1136 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 1137 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 1138 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1139 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 1140 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1141 1142 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 1143 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 1144 1145 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 1146 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 1147 1148 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 1149 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 1150 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 1151 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 1152 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 1153 1154 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 1155 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 1156 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 1157 1158 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 1159 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 1160 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 1161 1162 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 1163 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 1164 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 1165 1166 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 1167 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 1168 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 1169 1170 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 1171 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 1172 1173 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 1174 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 1175 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 1176 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 1177 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 1178 1179 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 1180 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 1181 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 1182 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 1183 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 1184 1185 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 1186 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 1187 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1188 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 1189 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1190 1191 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 1192 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 1193 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1194 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 1195 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1196 1197 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 1198 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 1199 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 1200 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 1201 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 1202 1203 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 1204 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 1205 1206 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 1207 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 1208 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1209 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 1210 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1211 1212 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 1213 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 1214 1215 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 1216 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 1217 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 1218 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 1219 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 1220 1221 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 1222 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 1223 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1224 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 1225 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1226 1227 /* DEVCPU_QS:XTR:XTR_RD */ 1228 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 1229 1230 /* DEVCPU_QS:XTR:XTR_FLUSH */ 1231 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 1232 1233 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 1234 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 1235 1236 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 1237 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 1238 1239 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 1240 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 1241 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 1242 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 1243 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 1244 1245 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 1246 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 1247 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1248 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 1249 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1250 1251 /* DEVCPU_QS:INJ:INJ_WR */ 1252 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 1253 1254 /* DEVCPU_QS:INJ:INJ_CTRL */ 1255 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 1256 1257 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 1258 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 1259 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 1260 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 1261 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 1262 1263 #define QS_INJ_CTRL_EOF BIT(19) 1264 #define QS_INJ_CTRL_EOF_SET(x)\ 1265 FIELD_PREP(QS_INJ_CTRL_EOF, x) 1266 #define QS_INJ_CTRL_EOF_GET(x)\ 1267 FIELD_GET(QS_INJ_CTRL_EOF, x) 1268 1269 #define QS_INJ_CTRL_SOF BIT(18) 1270 #define QS_INJ_CTRL_SOF_SET(x)\ 1271 FIELD_PREP(QS_INJ_CTRL_SOF, x) 1272 #define QS_INJ_CTRL_SOF_GET(x)\ 1273 FIELD_GET(QS_INJ_CTRL_SOF, x) 1274 1275 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 1276 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 1277 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 1278 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 1279 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 1280 1281 /* DEVCPU_QS:INJ:INJ_STATUS */ 1282 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 1283 1284 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 1285 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 1286 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 1287 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 1288 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 1289 1290 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 1291 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 1292 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 1293 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 1294 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 1295 1296 /* QSYS:SYSTEM:PORT_MODE */ 1297 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 1298 1299 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 1300 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 1301 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1302 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 1303 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1304 1305 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 1306 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 1307 1308 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 1309 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 1310 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 1311 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 1312 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 1313 1314 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 1315 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 1316 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1317 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 1318 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1319 1320 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 1321 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 1322 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1323 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 1324 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1325 1326 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 1327 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 1328 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1329 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 1330 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1331 1332 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 1333 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 1334 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 1335 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 1336 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 1337 1338 /* QSYS:SYSTEM:SW_STATUS */ 1339 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 1340 1341 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 1342 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 1343 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 1344 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 1345 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 1346 1347 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 1348 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 1349 1350 /* QSYS:RES_CTRL:RES_CFG */ 1351 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 1352 1353 /* QSYS:HSCH:CIR_CFG */ 1354 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4) 1355 1356 #define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6) 1357 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ 1358 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x) 1359 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ 1360 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x) 1361 1362 #define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0) 1363 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ 1364 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x) 1365 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ 1366 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x) 1367 1368 /* QSYS:HSCH:SE_CFG */ 1369 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4) 1370 1371 #define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6) 1372 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ 1373 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x) 1374 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ 1375 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x) 1376 1377 #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 1378 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ 1379 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x) 1380 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ 1381 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x) 1382 1383 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 1384 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ 1385 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x) 1386 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ 1387 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x) 1388 1389 #define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2) 1390 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ 1391 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x) 1392 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ 1393 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x) 1394 1395 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4) 1396 1397 #define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0) 1398 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ 1399 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1400 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ 1401 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1402 1403 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ 1404 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4) 1405 1406 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23) 1407 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ 1408 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1409 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ 1410 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1411 1412 #define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18) 1413 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ 1414 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1415 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ 1416 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1417 1418 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17) 1419 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ 1420 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1421 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ 1422 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1423 1424 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5) 1425 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ 1426 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1427 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ 1428 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1429 1430 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ 1431 #define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4) 1432 1433 #define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0) 1434 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ 1435 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1436 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ 1437 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1438 1439 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 1440 #define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4) 1441 1442 #define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0) 1443 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ 1444 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1445 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ 1446 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1447 1448 /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ 1449 #define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4) 1450 1451 #define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19) 1452 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ 1453 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1454 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ 1455 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1456 1457 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16) 1458 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ 1459 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1460 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ 1461 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1462 1463 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ 1464 #define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4) 1465 1466 #define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0) 1467 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ 1468 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x) 1469 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ 1470 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x) 1471 1472 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ 1473 #define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4) 1474 1475 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ 1476 #define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4) 1477 1478 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0) 1479 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ 1480 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1481 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ 1482 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1483 1484 /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ 1485 #define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4) 1486 1487 /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ 1488 #define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4) 1489 1490 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23) 1491 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ 1492 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1493 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ 1494 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1495 1496 /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ 1497 #define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4) 1498 1499 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0) 1500 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ 1501 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1502 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ 1503 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1504 1505 /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ 1506 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4) 1507 1508 #define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0) 1509 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ 1510 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x) 1511 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ 1512 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x) 1513 1514 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ 1515 #define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4) 1516 1517 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10) 1518 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ 1519 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1520 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ 1521 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1522 1523 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2) 1524 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ 1525 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1526 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ 1527 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1528 1529 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0) 1530 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ 1531 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1532 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ 1533 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1534 1535 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ 1536 #define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4) 1537 1538 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12) 1539 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ 1540 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1541 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ 1542 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1543 1544 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0) 1545 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ 1546 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1547 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ 1548 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1549 1550 /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ 1551 #define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4) 1552 1553 /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ 1554 #define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4) 1555 1556 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0) 1557 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ 1558 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1559 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ 1560 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1561 1562 /* REW:PORT:PORT_VLAN_CFG */ 1563 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 1564 1565 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 1566 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 1567 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 1568 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 1569 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 1570 1571 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 1572 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 1573 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 1574 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 1575 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 1576 1577 /* REW:PORT:TAG_CFG */ 1578 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 1579 1580 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 1581 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 1582 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 1583 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 1584 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 1585 1586 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 1587 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 1588 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 1589 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 1590 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 1591 1592 #define REW_TAG_CFG_TAG_PCP_CFG GENMASK(3, 2) 1593 #define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\ 1594 FIELD_PREP(REW_TAG_CFG_TAG_PCP_CFG, x) 1595 #define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\ 1596 FIELD_GET(REW_TAG_CFG_TAG_PCP_CFG, x) 1597 1598 #define REW_TAG_CFG_TAG_DEI_CFG GENMASK(1, 0) 1599 #define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\ 1600 FIELD_PREP(REW_TAG_CFG_TAG_DEI_CFG, x) 1601 #define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\ 1602 FIELD_GET(REW_TAG_CFG_TAG_DEI_CFG, x) 1603 1604 /* REW:PORT:PORT_CFG */ 1605 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1606 1607 #define REW_PORT_CFG_ES0_EN BIT(4) 1608 #define REW_PORT_CFG_ES0_EN_SET(x)\ 1609 FIELD_PREP(REW_PORT_CFG_ES0_EN, x) 1610 #define REW_PORT_CFG_ES0_EN_GET(x)\ 1611 FIELD_GET(REW_PORT_CFG_ES0_EN, x) 1612 1613 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1614 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1615 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1616 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1617 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1618 1619 /* REW:PORT:DSCP_CFG */ 1620 #define REW_DSCP_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 12, 0, 1, 4) 1621 1622 #define REW_DSCP_CFG_DSCP_REWR_CFG GENMASK(1, 0) 1623 #define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\ 1624 FIELD_PREP(REW_DSCP_CFG_DSCP_REWR_CFG, x) 1625 #define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\ 1626 FIELD_GET(REW_DSCP_CFG_DSCP_REWR_CFG, x) 1627 1628 /* REW:PORT:PCP_DEI_QOS_MAP_CFG */ 1629 #define REW_PCP_DEI_CFG(g, r) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 16, r, 16, 4) 1630 1631 #define REW_PCP_DEI_CFG_DEI_QOS_VAL BIT(3) 1632 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\ 1633 FIELD_PREP(REW_PCP_DEI_CFG_DEI_QOS_VAL, x) 1634 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\ 1635 FIELD_GET(REW_PCP_DEI_CFG_DEI_QOS_VAL, x) 1636 1637 #define REW_PCP_DEI_CFG_PCP_QOS_VAL GENMASK(2, 0) 1638 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\ 1639 FIELD_PREP(REW_PCP_DEI_CFG_PCP_QOS_VAL, x) 1640 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\ 1641 FIELD_GET(REW_PCP_DEI_CFG_PCP_QOS_VAL, x) 1642 1643 /* REW:COMMON:STAT_CFG */ 1644 #define REW_STAT_CFG __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528, 520, 0, 1, 4) 1645 1646 #define REW_STAT_CFG_STAT_MODE GENMASK(1, 0) 1647 #define REW_STAT_CFG_STAT_MODE_SET(x)\ 1648 FIELD_PREP(REW_STAT_CFG_STAT_MODE, x) 1649 #define REW_STAT_CFG_STAT_MODE_GET(x)\ 1650 FIELD_GET(REW_STAT_CFG_STAT_MODE, x) 1651 1652 /* SYS:SYSTEM:RESET_CFG */ 1653 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1654 1655 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1656 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1657 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1658 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1659 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1660 1661 /* SYS:SYSTEM:PORT_MODE */ 1662 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1663 1664 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1665 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1666 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1667 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1668 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1669 1670 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1671 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1672 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1673 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1674 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1675 1676 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1677 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1678 1679 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1680 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1681 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1682 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1683 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1684 1685 /* SYS:SYSTEM:FRM_AGING */ 1686 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1687 1688 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1689 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1690 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1691 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1692 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1693 1694 /* SYS:SYSTEM:STAT_CFG */ 1695 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1696 1697 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1698 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1699 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1700 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1701 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1702 1703 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1704 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1705 1706 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1707 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1708 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1709 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1710 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1711 1712 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1713 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1714 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1715 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1716 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1717 1718 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1719 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1720 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1721 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1722 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1723 1724 /* SYS:PAUSE_CFG:ATOP */ 1725 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1726 1727 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1728 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1729 1730 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1731 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1732 1733 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1734 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1735 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1736 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1737 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1738 1739 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1740 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1741 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1742 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1743 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1744 1745 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1746 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1747 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1748 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1749 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1750 1751 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1752 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1753 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1754 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1755 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1756 1757 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1758 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1759 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1760 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1761 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1762 1763 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1764 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1765 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1766 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1767 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1768 1769 /* SYS:STAT:CNT */ 1770 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1771 1772 /* SYS:RAM_CTRL:RAM_INIT */ 1773 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1774 1775 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1776 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1777 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1778 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1779 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1780 1781 /* VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 1782 #define VCAP_UPDATE_CTRL(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4) 1783 1784 #define VCAP_UPDATE_CTRL_UPDATE_CMD GENMASK(24, 22) 1785 #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\ 1786 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1787 #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\ 1788 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1789 1790 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 1791 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 1792 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1793 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 1794 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1795 1796 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 1797 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\ 1798 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1799 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\ 1800 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1801 1802 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 1803 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\ 1804 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1805 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\ 1806 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1807 1808 #define VCAP_UPDATE_CTRL_UPDATE_ADDR GENMASK(18, 3) 1809 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\ 1810 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1811 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\ 1812 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1813 1814 #define VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2) 1815 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\ 1816 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1817 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\ 1818 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1819 1820 #define VCAP_UPDATE_CTRL_CLEAR_CACHE BIT(1) 1821 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\ 1822 FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1823 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\ 1824 FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1825 1826 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 1827 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\ 1828 FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1829 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\ 1830 FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1831 1832 /* VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */ 1833 #define VCAP_MV_CFG(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4) 1834 1835 #define VCAP_MV_CFG_MV_NUM_POS GENMASK(31, 16) 1836 #define VCAP_MV_CFG_MV_NUM_POS_SET(x)\ 1837 FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x) 1838 #define VCAP_MV_CFG_MV_NUM_POS_GET(x)\ 1839 FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x) 1840 1841 #define VCAP_MV_CFG_MV_SIZE GENMASK(15, 0) 1842 #define VCAP_MV_CFG_MV_SIZE_SET(x)\ 1843 FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x) 1844 #define VCAP_MV_CFG_MV_SIZE_GET(x)\ 1845 FIELD_GET(VCAP_MV_CFG_MV_SIZE, x) 1846 1847 /* VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 1848 #define VCAP_ENTRY_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4) 1849 1850 /* VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 1851 #define VCAP_MASK_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4) 1852 1853 /* VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 1854 #define VCAP_ACTION_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4) 1855 1856 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 1857 #define VCAP_CNT_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4) 1858 1859 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 1860 #define VCAP_CNT_FW_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4) 1861 1862 /* VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */ 1863 #define VCAP_TG_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4) 1864 1865 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */ 1866 #define VCAP_CORE_IDX(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4) 1867 1868 #define VCAP_CORE_IDX_CORE_IDX GENMASK(3, 0) 1869 #define VCAP_CORE_IDX_CORE_IDX_SET(x)\ 1870 FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x) 1871 #define VCAP_CORE_IDX_CORE_IDX_GET(x)\ 1872 FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x) 1873 1874 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */ 1875 #define VCAP_CORE_MAP(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4) 1876 1877 #define VCAP_CORE_MAP_CORE_MAP GENMASK(2, 0) 1878 #define VCAP_CORE_MAP_CORE_MAP_SET(x)\ 1879 FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x) 1880 #define VCAP_CORE_MAP_CORE_MAP_GET(x)\ 1881 FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x) 1882 1883 /* VCAP:VCAP_CONST:VCAP_VER */ 1884 #define VCAP_VER(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4) 1885 1886 /* VCAP:VCAP_CONST:ENTRY_WIDTH */ 1887 #define VCAP_ENTRY_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4) 1888 1889 /* VCAP:VCAP_CONST:ENTRY_CNT */ 1890 #define VCAP_ENTRY_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4) 1891 1892 /* VCAP:VCAP_CONST:ENTRY_SWCNT */ 1893 #define VCAP_ENTRY_SWCNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4) 1894 1895 /* VCAP:VCAP_CONST:ENTRY_TG_WIDTH */ 1896 #define VCAP_ENTRY_TG_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4) 1897 1898 /* VCAP:VCAP_CONST:ACTION_DEF_CNT */ 1899 #define VCAP_ACTION_DEF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4) 1900 1901 /* VCAP:VCAP_CONST:ACTION_WIDTH */ 1902 #define VCAP_ACTION_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4) 1903 1904 /* VCAP:VCAP_CONST:CNT_WIDTH */ 1905 #define VCAP_CNT_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4) 1906 1907 /* VCAP:VCAP_CONST:CORE_CNT */ 1908 #define VCAP_CORE_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4) 1909 1910 /* VCAP:VCAP_CONST:IF_CNT */ 1911 #define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4) 1912 1913 #endif /* _LAN966X_REGS_H_ */ 1914