1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/vncr_mapping.h>
31
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
33
34 #define KVM_HALT_POLL_NS_DEFAULT 500000
35
36 #include <kvm/arm_vgic.h>
37 #include <kvm/arm_arch_timer.h>
38 #include <kvm/arm_pmu.h>
39
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
41
42 #define KVM_VCPU_MAX_FEATURES 7
43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
44
45 #define KVM_REQ_SLEEP \
46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
48 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
49 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
50 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
51 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
52 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
53 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
54 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8)
55
56 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
57 KVM_DIRTY_LOG_INITIALLY_SET)
58
59 #define KVM_HAVE_MMU_RWLOCK
60
61 /*
62 * Mode of operation configurable with kvm-arm.mode early param.
63 * See Documentation/admin-guide/kernel-parameters.txt for more information.
64 */
65 enum kvm_mode {
66 KVM_MODE_DEFAULT,
67 KVM_MODE_PROTECTED,
68 KVM_MODE_NV,
69 KVM_MODE_NONE,
70 };
71 #ifdef CONFIG_KVM
72 enum kvm_mode kvm_get_mode(void);
73 #else
kvm_get_mode(void)74 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
75 #endif
76
77 extern unsigned int __ro_after_init kvm_sve_max_vl;
78 extern unsigned int __ro_after_init kvm_host_sve_max_vl;
79 int __init kvm_arm_init_sve(void);
80
81 u32 __attribute_const__ kvm_target_cpu(void);
82 void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
83 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
84
85 struct kvm_hyp_memcache {
86 phys_addr_t head;
87 unsigned long nr_pages;
88 struct pkvm_mapping *mapping; /* only used from EL1 */
89 };
90
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))91 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
92 phys_addr_t *p,
93 phys_addr_t (*to_pa)(void *virt))
94 {
95 *p = mc->head;
96 mc->head = to_pa(p);
97 mc->nr_pages++;
98 }
99
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))100 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
101 void *(*to_va)(phys_addr_t phys))
102 {
103 phys_addr_t *p = to_va(mc->head & PAGE_MASK);
104
105 if (!mc->nr_pages)
106 return NULL;
107
108 mc->head = *p;
109 mc->nr_pages--;
110
111 return p;
112 }
113
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)114 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
115 unsigned long min_pages,
116 void *(*alloc_fn)(void *arg),
117 phys_addr_t (*to_pa)(void *virt),
118 void *arg)
119 {
120 while (mc->nr_pages < min_pages) {
121 phys_addr_t *p = alloc_fn(arg);
122
123 if (!p)
124 return -ENOMEM;
125 push_hyp_memcache(mc, p, to_pa);
126 }
127
128 return 0;
129 }
130
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)131 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
132 void (*free_fn)(void *virt, void *arg),
133 void *(*to_va)(phys_addr_t phys),
134 void *arg)
135 {
136 while (mc->nr_pages)
137 free_fn(pop_hyp_memcache(mc, to_va), arg);
138 }
139
140 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
141 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
142
143 struct kvm_vmid {
144 atomic64_t id;
145 };
146
147 struct kvm_s2_mmu {
148 struct kvm_vmid vmid;
149
150 /*
151 * stage2 entry level table
152 *
153 * Two kvm_s2_mmu structures in the same VM can point to the same
154 * pgd here. This happens when running a guest using a
155 * translation regime that isn't affected by its own stage-2
156 * translation, such as a non-VHE hypervisor running at vEL2, or
157 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
158 * canonical stage-2 page tables.
159 */
160 phys_addr_t pgd_phys;
161 struct kvm_pgtable *pgt;
162
163 /*
164 * VTCR value used on the host. For a non-NV guest (or a NV
165 * guest that runs in a context where its own S2 doesn't
166 * apply), its T0SZ value reflects that of the IPA size.
167 *
168 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to
169 * the guest.
170 */
171 u64 vtcr;
172
173 /* The last vcpu id that ran on each physical CPU */
174 int __percpu *last_vcpu_ran;
175
176 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
177 /*
178 * Memory cache used to split
179 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
180 * is used to allocate stage2 page tables while splitting huge
181 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
182 * influences both the capacity of the split page cache, and
183 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
184 * too high.
185 *
186 * Protected by kvm->slots_lock.
187 */
188 struct kvm_mmu_memory_cache split_page_cache;
189 uint64_t split_page_chunk_size;
190
191 struct kvm_arch *arch;
192
193 /*
194 * For a shadow stage-2 MMU, the virtual vttbr used by the
195 * host to parse the guest S2.
196 * This either contains:
197 * - the virtual VTTBR programmed by the guest hypervisor with
198 * CnP cleared
199 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid
200 *
201 * We also cache the full VTCR which gets used for TLB invalidation,
202 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted
203 * to be cached in a TLB" to the letter.
204 */
205 u64 tlb_vttbr;
206 u64 tlb_vtcr;
207
208 /*
209 * true when this represents a nested context where virtual
210 * HCR_EL2.VM == 1
211 */
212 bool nested_stage2_enabled;
213
214 /*
215 * true when this MMU needs to be unmapped before being used for a new
216 * purpose.
217 */
218 bool pending_unmap;
219
220 /*
221 * 0: Nobody is currently using this, check vttbr for validity
222 * >0: Somebody is actively using this.
223 */
224 atomic_t refcnt;
225 };
226
227 struct kvm_arch_memory_slot {
228 };
229
230 /**
231 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
232 *
233 * @std_bmap: Bitmap of standard secure service calls
234 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
235 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
236 */
237 struct kvm_smccc_features {
238 unsigned long std_bmap;
239 unsigned long std_hyp_bmap;
240 unsigned long vendor_hyp_bmap;
241 };
242
243 typedef unsigned int pkvm_handle_t;
244
245 struct kvm_protected_vm {
246 pkvm_handle_t handle;
247 struct kvm_hyp_memcache teardown_mc;
248 bool enabled;
249 };
250
251 struct kvm_mpidr_data {
252 u64 mpidr_mask;
253 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
254 };
255
kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)256 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
257 {
258 unsigned long index = 0, mask = data->mpidr_mask;
259 unsigned long aff = mpidr & MPIDR_HWID_BITMASK;
260
261 bitmap_gather(&index, &aff, &mask, fls(mask));
262
263 return index;
264 }
265
266 struct kvm_sysreg_masks;
267
268 enum fgt_group_id {
269 __NO_FGT_GROUP__,
270 HFGxTR_GROUP,
271 HDFGRTR_GROUP,
272 HDFGWTR_GROUP = HDFGRTR_GROUP,
273 HFGITR_GROUP,
274 HAFGRTR_GROUP,
275
276 /* Must be last */
277 __NR_FGT_GROUP_IDS__
278 };
279
280 struct kvm_arch {
281 struct kvm_s2_mmu mmu;
282
283 /*
284 * Fine-Grained UNDEF, mimicking the FGT layout defined by the
285 * architecture. We track them globally, as we present the
286 * same feature-set to all vcpus.
287 *
288 * Index 0 is currently spare.
289 */
290 u64 fgu[__NR_FGT_GROUP_IDS__];
291
292 /*
293 * Stage 2 paging state for VMs with nested S2 using a virtual
294 * VMID.
295 */
296 struct kvm_s2_mmu *nested_mmus;
297 size_t nested_mmus_size;
298 int nested_mmus_next;
299
300 /* Interrupt controller */
301 struct vgic_dist vgic;
302
303 /* Timers */
304 struct arch_timer_vm_data timer_data;
305
306 /* Mandated version of PSCI */
307 u32 psci_version;
308
309 /* Protects VM-scoped configuration data */
310 struct mutex config_lock;
311
312 /*
313 * If we encounter a data abort without valid instruction syndrome
314 * information, report this to user space. User space can (and
315 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
316 * supported.
317 */
318 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
319 /* Memory Tagging Extension enabled for the guest */
320 #define KVM_ARCH_FLAG_MTE_ENABLED 1
321 /* At least one vCPU has ran in the VM */
322 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
323 /* The vCPU feature set for the VM is configured */
324 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3
325 /* PSCI SYSTEM_SUSPEND enabled for the guest */
326 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4
327 /* VM counter offset */
328 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
329 /* Timer PPIs made immutable */
330 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
331 /* Initial ID reg values loaded */
332 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7
333 /* Fine-Grained UNDEF initialised */
334 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8
335 /* SVE exposed to guest */
336 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9
337 unsigned long flags;
338
339 /* VM-wide vCPU feature set */
340 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
341
342 /* MPIDR to vcpu index mapping, optional */
343 struct kvm_mpidr_data *mpidr_data;
344
345 /*
346 * VM-wide PMU filter, implemented as a bitmap and big enough for
347 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
348 */
349 unsigned long *pmu_filter;
350 struct arm_pmu *arm_pmu;
351
352 cpumask_var_t supported_cpus;
353
354 /* PMCR_EL0.N value for the guest */
355 u8 pmcr_n;
356
357 /* Iterator for idreg debugfs */
358 u8 idreg_debugfs_iter;
359
360 /* Hypercall features firmware registers' descriptor */
361 struct kvm_smccc_features smccc_feat;
362 struct maple_tree smccc_filter;
363
364 /*
365 * Emulated CPU ID registers per VM
366 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
367 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
368 *
369 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
370 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
371 */
372 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
373 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
374 u64 id_regs[KVM_ARM_ID_REG_NUM];
375
376 u64 ctr_el0;
377
378 /* Masks for VNCR-backed and general EL2 sysregs */
379 struct kvm_sysreg_masks *sysreg_masks;
380
381 /*
382 * For an untrusted host VM, 'pkvm.handle' is used to lookup
383 * the associated pKVM instance in the hypervisor.
384 */
385 struct kvm_protected_vm pkvm;
386 };
387
388 struct kvm_vcpu_fault_info {
389 u64 esr_el2; /* Hyp Syndrom Register */
390 u64 far_el2; /* Hyp Fault Address Register */
391 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
392 u64 disr_el1; /* Deferred [SError] Status Register */
393 };
394
395 /*
396 * VNCR() just places the VNCR_capable registers in the enum after
397 * __VNCR_START__, and the value (after correction) to be an 8-byte offset
398 * from the VNCR base. As we don't require the enum to be otherwise ordered,
399 * we need the terrible hack below to ensure that we correctly size the
400 * sys_regs array, no matter what.
401 *
402 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
403 * treasure trove of bit hacks:
404 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
405 */
406 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y))))
407 #define VNCR(r) \
408 __before_##r, \
409 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
410 __after_##r = __MAX__(__before_##r - 1, r)
411
412 #define MARKER(m) \
413 m, __after_##m = m - 1
414
415 enum vcpu_sysreg {
416 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
417 MPIDR_EL1, /* MultiProcessor Affinity Register */
418 CLIDR_EL1, /* Cache Level ID Register */
419 CSSELR_EL1, /* Cache Size Selection Register */
420 TPIDR_EL0, /* Thread ID, User R/W */
421 TPIDRRO_EL0, /* Thread ID, User R/O */
422 TPIDR_EL1, /* Thread ID, Privileged */
423 CNTKCTL_EL1, /* Timer Control Register (EL1) */
424 PAR_EL1, /* Physical Address Register */
425 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
426 OSLSR_EL1, /* OS Lock Status Register */
427 DISR_EL1, /* Deferred Interrupt Status Register */
428
429 /* Performance Monitors Registers */
430 PMCR_EL0, /* Control Register */
431 PMSELR_EL0, /* Event Counter Selection Register */
432 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
433 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
434 PMCCNTR_EL0, /* Cycle Counter Register */
435 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
436 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
437 PMCCFILTR_EL0, /* Cycle Count Filter Register */
438 PMCNTENSET_EL0, /* Count Enable Set Register */
439 PMINTENSET_EL1, /* Interrupt Enable Set Register */
440 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
441 PMUSERENR_EL0, /* User Enable Register */
442
443 /* Pointer Authentication Registers in a strict increasing order. */
444 APIAKEYLO_EL1,
445 APIAKEYHI_EL1,
446 APIBKEYLO_EL1,
447 APIBKEYHI_EL1,
448 APDAKEYLO_EL1,
449 APDAKEYHI_EL1,
450 APDBKEYLO_EL1,
451 APDBKEYHI_EL1,
452 APGAKEYLO_EL1,
453 APGAKEYHI_EL1,
454
455 /* Memory Tagging Extension registers */
456 RGSR_EL1, /* Random Allocation Tag Seed Register */
457 GCR_EL1, /* Tag Control Register */
458 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
459
460 POR_EL0, /* Permission Overlay Register 0 (EL0) */
461
462 /* FP/SIMD/SVE */
463 SVCR,
464 FPMR,
465
466 /* 32bit specific registers. */
467 DACR32_EL2, /* Domain Access Control Register */
468 IFSR32_EL2, /* Instruction Fault Status Register */
469 FPEXC32_EL2, /* Floating-Point Exception Control Register */
470 DBGVCR32_EL2, /* Debug Vector Catch Register */
471
472 /* EL2 registers */
473 SCTLR_EL2, /* System Control Register (EL2) */
474 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
475 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
476 HACR_EL2, /* Hypervisor Auxiliary Control Register */
477 ZCR_EL2, /* SVE Control Register (EL2) */
478 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
479 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
480 TCR_EL2, /* Translation Control Register (EL2) */
481 PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */
482 PIR_EL2, /* Permission Indirection Register 1 (EL2) */
483 POR_EL2, /* Permission Overlay Register 2 (EL2) */
484 SPSR_EL2, /* EL2 saved program status register */
485 ELR_EL2, /* EL2 exception link register */
486 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
487 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
488 ESR_EL2, /* Exception Syndrome Register (EL2) */
489 FAR_EL2, /* Fault Address Register (EL2) */
490 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
491 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
492 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
493 VBAR_EL2, /* Vector Base Address Register (EL2) */
494 RVBAR_EL2, /* Reset Vector Base Address Register */
495 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
496 SP_EL2, /* EL2 Stack Pointer */
497 CNTHP_CTL_EL2,
498 CNTHP_CVAL_EL2,
499 CNTHV_CTL_EL2,
500 CNTHV_CVAL_EL2,
501
502 /* Anything from this can be RES0/RES1 sanitised */
503 MARKER(__SANITISED_REG_START__),
504 TCR2_EL2, /* Extended Translation Control Register (EL2) */
505 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
506 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
507
508 /* Any VNCR-capable reg goes after this point */
509 MARKER(__VNCR_START__),
510
511 VNCR(SCTLR_EL1),/* System Control Register */
512 VNCR(ACTLR_EL1),/* Auxiliary Control Register */
513 VNCR(CPACR_EL1),/* Coprocessor Access Control */
514 VNCR(ZCR_EL1), /* SVE Control */
515 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
516 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
517 VNCR(TCR_EL1), /* Translation Control Register */
518 VNCR(TCR2_EL1), /* Extended Translation Control Register */
519 VNCR(ESR_EL1), /* Exception Syndrome Register */
520 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
521 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
522 VNCR(FAR_EL1), /* Fault Address Register */
523 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
524 VNCR(VBAR_EL1), /* Vector Base Address Register */
525 VNCR(CONTEXTIDR_EL1), /* Context ID Register */
526 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
527 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
528 VNCR(ELR_EL1),
529 VNCR(SP_EL1),
530 VNCR(SPSR_EL1),
531 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
532 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
533 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
534 VNCR(HCR_EL2), /* Hypervisor Configuration Register */
535 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
536 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
537 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
538 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
539 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
540
541 /* Permission Indirection Extension registers */
542 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */
543 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */
544
545 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */
546
547 VNCR(HFGRTR_EL2),
548 VNCR(HFGWTR_EL2),
549 VNCR(HFGITR_EL2),
550 VNCR(HDFGRTR_EL2),
551 VNCR(HDFGWTR_EL2),
552 VNCR(HAFGRTR_EL2),
553
554 VNCR(CNTVOFF_EL2),
555 VNCR(CNTV_CVAL_EL0),
556 VNCR(CNTV_CTL_EL0),
557 VNCR(CNTP_CVAL_EL0),
558 VNCR(CNTP_CTL_EL0),
559
560 VNCR(ICH_HCR_EL2),
561
562 NR_SYS_REGS /* Nothing after this line! */
563 };
564
565 struct kvm_sysreg_masks {
566 struct {
567 u64 res0;
568 u64 res1;
569 } mask[NR_SYS_REGS - __SANITISED_REG_START__];
570 };
571
572 struct kvm_cpu_context {
573 struct user_pt_regs regs; /* sp = sp_el0 */
574
575 u64 spsr_abt;
576 u64 spsr_und;
577 u64 spsr_irq;
578 u64 spsr_fiq;
579
580 struct user_fpsimd_state fp_regs;
581
582 u64 sys_regs[NR_SYS_REGS];
583
584 struct kvm_vcpu *__hyp_running_vcpu;
585
586 /* This pointer has to be 4kB aligned. */
587 u64 *vncr_array;
588 };
589
590 struct cpu_sve_state {
591 __u64 zcr_el1;
592
593 /*
594 * Ordering is important since __sve_save_state/__sve_restore_state
595 * relies on it.
596 */
597 __u32 fpsr;
598 __u32 fpcr;
599
600 /* Must be SVE_VQ_BYTES (128 bit) aligned. */
601 __u8 sve_regs[];
602 };
603
604 /*
605 * This structure is instantiated on a per-CPU basis, and contains
606 * data that is:
607 *
608 * - tied to a single physical CPU, and
609 * - either have a lifetime that does not extend past vcpu_put()
610 * - or is an invariant for the lifetime of the system
611 *
612 * Use host_data_ptr(field) as a way to access a pointer to such a
613 * field.
614 */
615 struct kvm_host_data {
616 #define KVM_HOST_DATA_FLAG_HAS_SPE 0
617 #define KVM_HOST_DATA_FLAG_HAS_TRBE 1
618 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED 4
619 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED 5
620 unsigned long flags;
621
622 struct kvm_cpu_context host_ctxt;
623
624 /*
625 * Hyp VA.
626 * sve_state is only used in pKVM and if system_supports_sve().
627 */
628 struct cpu_sve_state *sve_state;
629
630 /* Used by pKVM only. */
631 u64 fpmr;
632
633 /* Ownership of the FP regs */
634 enum {
635 FP_STATE_FREE,
636 FP_STATE_HOST_OWNED,
637 FP_STATE_GUEST_OWNED,
638 } fp_owner;
639
640 /*
641 * host_debug_state contains the host registers which are
642 * saved and restored during world switches.
643 */
644 struct {
645 /* {Break,watch}point registers */
646 struct kvm_guest_debug_arch regs;
647 /* Statistical profiling extension */
648 u64 pmscr_el1;
649 /* Self-hosted trace */
650 u64 trfcr_el1;
651 /* Values of trap registers for the host before guest entry. */
652 u64 mdcr_el2;
653 } host_debug_state;
654
655 /* Guest trace filter value */
656 u64 trfcr_while_in_guest;
657
658 /* Number of programmable event counters (PMCR_EL0.N) for this CPU */
659 unsigned int nr_event_counters;
660
661 /* Number of debug breakpoints/watchpoints for this CPU (minus 1) */
662 unsigned int debug_brps;
663 unsigned int debug_wrps;
664 };
665
666 struct kvm_host_psci_config {
667 /* PSCI version used by host. */
668 u32 version;
669 u32 smccc_version;
670
671 /* Function IDs used by host if version is v0.1. */
672 struct psci_0_1_function_ids function_ids_0_1;
673
674 bool psci_0_1_cpu_suspend_implemented;
675 bool psci_0_1_cpu_on_implemented;
676 bool psci_0_1_cpu_off_implemented;
677 bool psci_0_1_migrate_implemented;
678 };
679
680 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
681 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
682
683 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
684 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
685
686 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
687 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
688
689 struct vcpu_reset_state {
690 unsigned long pc;
691 unsigned long r0;
692 bool be;
693 bool reset;
694 };
695
696 struct kvm_vcpu_arch {
697 struct kvm_cpu_context ctxt;
698
699 /*
700 * Guest floating point state
701 *
702 * The architecture has two main floating point extensions,
703 * the original FPSIMD and SVE. These have overlapping
704 * register views, with the FPSIMD V registers occupying the
705 * low 128 bits of the SVE Z registers. When the core
706 * floating point code saves the register state of a task it
707 * records which view it saved in fp_type.
708 */
709 void *sve_state;
710 enum fp_type fp_type;
711 unsigned int sve_max_vl;
712
713 /* Stage 2 paging state used by the hardware on next switch */
714 struct kvm_s2_mmu *hw_mmu;
715
716 /* Values of trap registers for the guest. */
717 u64 hcr_el2;
718 u64 hcrx_el2;
719 u64 mdcr_el2;
720
721 /* Exception Information */
722 struct kvm_vcpu_fault_info fault;
723
724 /* Configuration flags, set once and for all before the vcpu can run */
725 u8 cflags;
726
727 /* Input flags to the hypervisor code, potentially cleared after use */
728 u8 iflags;
729
730 /* State flags for kernel bookkeeping, unused by the hypervisor code */
731 u8 sflags;
732
733 /*
734 * Don't run the guest (internal implementation need).
735 *
736 * Contrary to the flags above, this is set/cleared outside of
737 * a vcpu context, and thus cannot be mixed with the flags
738 * themselves (or the flag accesses need to be made atomic).
739 */
740 bool pause;
741
742 /*
743 * We maintain more than a single set of debug registers to support
744 * debugging the guest from the host and to maintain separate host and
745 * guest state during world switches. vcpu_debug_state are the debug
746 * registers of the vcpu as the guest sees them.
747 *
748 * external_debug_state contains the debug values we want to debug the
749 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl.
750 */
751 struct kvm_guest_debug_arch vcpu_debug_state;
752 struct kvm_guest_debug_arch external_debug_state;
753 u64 external_mdscr_el1;
754
755 enum {
756 VCPU_DEBUG_FREE,
757 VCPU_DEBUG_HOST_OWNED,
758 VCPU_DEBUG_GUEST_OWNED,
759 } debug_owner;
760
761 /* VGIC state */
762 struct vgic_cpu vgic_cpu;
763 struct arch_timer_cpu timer_cpu;
764 struct kvm_pmu pmu;
765
766 /* vcpu power state */
767 struct kvm_mp_state mp_state;
768 spinlock_t mp_state_lock;
769
770 /* Cache some mmu pages needed inside spinlock regions */
771 struct kvm_mmu_memory_cache mmu_page_cache;
772
773 /* Pages to top-up the pKVM/EL2 guest pool */
774 struct kvm_hyp_memcache pkvm_memcache;
775
776 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
777 u64 vsesr_el2;
778
779 /* Additional reset state */
780 struct vcpu_reset_state reset_state;
781
782 /* Guest PV state */
783 struct {
784 u64 last_steal;
785 gpa_t base;
786 } steal;
787
788 /* Per-vcpu CCSIDR override or NULL */
789 u32 *ccsidr;
790 };
791
792 /*
793 * Each 'flag' is composed of a comma-separated triplet:
794 *
795 * - the flag-set it belongs to in the vcpu->arch structure
796 * - the value for that flag
797 * - the mask for that flag
798 *
799 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
800 * unpack_vcpu_flag() extract the flag value from the triplet for
801 * direct use outside of the flag accessors.
802 */
803 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
804
805 #define __unpack_flag(_set, _f, _m) _f
806 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
807
808 #define __build_check_flag(v, flagset, f, m) \
809 do { \
810 typeof(v->arch.flagset) *_fset; \
811 \
812 /* Check that the flags fit in the mask */ \
813 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
814 /* Check that the flags fit in the type */ \
815 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
816 } while (0)
817
818 #define __vcpu_get_flag(v, flagset, f, m) \
819 ({ \
820 __build_check_flag(v, flagset, f, m); \
821 \
822 READ_ONCE(v->arch.flagset) & (m); \
823 })
824
825 /*
826 * Note that the set/clear accessors must be preempt-safe in order to
827 * avoid nesting them with load/put which also manipulate flags...
828 */
829 #ifdef __KVM_NVHE_HYPERVISOR__
830 /* the nVHE hypervisor is always non-preemptible */
831 #define __vcpu_flags_preempt_disable()
832 #define __vcpu_flags_preempt_enable()
833 #else
834 #define __vcpu_flags_preempt_disable() preempt_disable()
835 #define __vcpu_flags_preempt_enable() preempt_enable()
836 #endif
837
838 #define __vcpu_set_flag(v, flagset, f, m) \
839 do { \
840 typeof(v->arch.flagset) *fset; \
841 \
842 __build_check_flag(v, flagset, f, m); \
843 \
844 fset = &v->arch.flagset; \
845 __vcpu_flags_preempt_disable(); \
846 if (HWEIGHT(m) > 1) \
847 *fset &= ~(m); \
848 *fset |= (f); \
849 __vcpu_flags_preempt_enable(); \
850 } while (0)
851
852 #define __vcpu_clear_flag(v, flagset, f, m) \
853 do { \
854 typeof(v->arch.flagset) *fset; \
855 \
856 __build_check_flag(v, flagset, f, m); \
857 \
858 fset = &v->arch.flagset; \
859 __vcpu_flags_preempt_disable(); \
860 *fset &= ~(m); \
861 __vcpu_flags_preempt_enable(); \
862 } while (0)
863
864 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
865 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
866 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
867
868 /* KVM_ARM_VCPU_INIT completed */
869 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0))
870 /* SVE config completed */
871 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
872
873 /* Exception pending */
874 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
875 /*
876 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
877 * be set together with an exception...
878 */
879 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
880 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
881 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
882
883 /* Helpers to encode exceptions with minimum fuss */
884 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
885 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
886 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
887
888 /*
889 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
890 * values:
891 *
892 * For AArch32 EL1:
893 */
894 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
895 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
896 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
897 /* For AArch64: */
898 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
899 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
900 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
901 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
902 /* For AArch64 with NV: */
903 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
904 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
905 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
906 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
907
908 /* Physical CPU not in supported_cpus */
909 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(0))
910 /* WFIT instruction trapped */
911 #define IN_WFIT __vcpu_single_flag(sflags, BIT(1))
912 /* vcpu system registers loaded on physical CPU */
913 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(2))
914 /* Software step state is Active-pending for external debug */
915 #define HOST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(3))
916 /* Software step state is Active pending for guest debug */
917 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4))
918 /* PMUSERENR for the guest EL0 is on physical CPU */
919 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(5))
920 /* WFI instruction trapped */
921 #define IN_WFI __vcpu_single_flag(sflags, BIT(6))
922
923
924 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
925 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
926 sve_ffr_offset((vcpu)->arch.sve_max_vl))
927
928 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
929
930 #define vcpu_sve_zcr_elx(vcpu) \
931 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1)
932
933 #define vcpu_sve_state_size(vcpu) ({ \
934 size_t __size_ret; \
935 unsigned int __vcpu_vq; \
936 \
937 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
938 __size_ret = 0; \
939 } else { \
940 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
941 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
942 } \
943 \
944 __size_ret; \
945 })
946
947 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
948 KVM_GUESTDBG_USE_SW_BP | \
949 KVM_GUESTDBG_USE_HW | \
950 KVM_GUESTDBG_SINGLESTEP)
951
952 #define kvm_has_sve(kvm) (system_supports_sve() && \
953 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags))
954
955 #ifdef __KVM_NVHE_HYPERVISOR__
956 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm))
957 #else
958 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm)
959 #endif
960
961 #ifdef CONFIG_ARM64_PTR_AUTH
962 #define vcpu_has_ptrauth(vcpu) \
963 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
964 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
965 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \
966 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)))
967 #else
968 #define vcpu_has_ptrauth(vcpu) false
969 #endif
970
971 #define vcpu_on_unsupported_cpu(vcpu) \
972 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
973
974 #define vcpu_set_on_unsupported_cpu(vcpu) \
975 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
976
977 #define vcpu_clear_on_unsupported_cpu(vcpu) \
978 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
979
980 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
981
982 /*
983 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
984 * memory backed version of a register, and not the one most recently
985 * accessed by a running VCPU. For example, for userspace access or
986 * for system registers that are never context switched, but only
987 * emulated.
988 *
989 * Don't bother with VNCR-based accesses in the nVHE code, it has no
990 * business dealing with NV.
991 */
___ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)992 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
993 {
994 #if !defined (__KVM_NVHE_HYPERVISOR__)
995 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
996 r >= __VNCR_START__ && ctxt->vncr_array))
997 return &ctxt->vncr_array[r - __VNCR_START__];
998 #endif
999 return (u64 *)&ctxt->sys_regs[r];
1000 }
1001
1002 #define __ctxt_sys_reg(c,r) \
1003 ({ \
1004 BUILD_BUG_ON(__builtin_constant_p(r) && \
1005 (r) >= NR_SYS_REGS); \
1006 ___ctxt_sys_reg(c, r); \
1007 })
1008
1009 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
1010
1011 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
1012 #define __vcpu_sys_reg(v,r) \
1013 (*({ \
1014 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
1015 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \
1016 if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
1017 *__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
1018 __r; \
1019 }))
1020
1021 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
1022 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
1023
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)1024 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
1025 {
1026 /*
1027 * *** VHE ONLY ***
1028 *
1029 * System registers listed in the switch are not saved on every
1030 * exit from the guest but are only saved on vcpu_put.
1031 *
1032 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1033 * should never be listed below, because the guest cannot modify its
1034 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1035 * thread when emulating cross-VCPU communication.
1036 */
1037 if (!has_vhe())
1038 return false;
1039
1040 switch (reg) {
1041 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
1042 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
1043 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
1044 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
1045 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
1046 case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break;
1047 case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break;
1048 case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break;
1049 case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break;
1050 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
1051 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
1052 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
1053 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
1054 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
1055 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
1056 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
1057 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
1058 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
1059 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
1060 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
1061 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
1062 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
1063 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
1064 case PAR_EL1: *val = read_sysreg_par(); break;
1065 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
1066 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
1067 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
1068 case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break;
1069 default: return false;
1070 }
1071
1072 return true;
1073 }
1074
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)1075 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
1076 {
1077 /*
1078 * *** VHE ONLY ***
1079 *
1080 * System registers listed in the switch are not restored on every
1081 * entry to the guest but are only restored on vcpu_load.
1082 *
1083 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1084 * should never be listed below, because the MPIDR should only be set
1085 * once, before running the VCPU, and never changed later.
1086 */
1087 if (!has_vhe())
1088 return false;
1089
1090 switch (reg) {
1091 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
1092 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
1093 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
1094 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
1095 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
1096 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
1097 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
1098 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
1099 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
1100 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
1101 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
1102 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
1103 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
1104 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
1105 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
1106 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
1107 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
1108 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
1109 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
1110 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
1111 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
1112 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
1113 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
1114 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
1115 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
1116 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
1117 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
1118 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
1119 default: return false;
1120 }
1121
1122 return true;
1123 }
1124
1125 struct kvm_vm_stat {
1126 struct kvm_vm_stat_generic generic;
1127 };
1128
1129 struct kvm_vcpu_stat {
1130 struct kvm_vcpu_stat_generic generic;
1131 u64 hvc_exit_stat;
1132 u64 wfe_exit_stat;
1133 u64 wfi_exit_stat;
1134 u64 mmio_exit_user;
1135 u64 mmio_exit_kernel;
1136 u64 signal_exits;
1137 u64 exits;
1138 };
1139
1140 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
1141 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
1142 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1143 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1144
1145 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
1146 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
1147
1148 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
1149 struct kvm_vcpu_events *events);
1150
1151 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
1152 struct kvm_vcpu_events *events);
1153
1154 void kvm_arm_halt_guest(struct kvm *kvm);
1155 void kvm_arm_resume_guest(struct kvm *kvm);
1156
1157 #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid))
1158
1159 #ifndef __KVM_NVHE_HYPERVISOR__
1160 #define kvm_call_hyp_nvhe(f, ...) \
1161 ({ \
1162 struct arm_smccc_res res; \
1163 \
1164 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
1165 ##__VA_ARGS__, &res); \
1166 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
1167 \
1168 res.a1; \
1169 })
1170
1171 /*
1172 * The couple of isb() below are there to guarantee the same behaviour
1173 * on VHE as on !VHE, where the eret to EL1 acts as a context
1174 * synchronization event.
1175 */
1176 #define kvm_call_hyp(f, ...) \
1177 do { \
1178 if (has_vhe()) { \
1179 f(__VA_ARGS__); \
1180 isb(); \
1181 } else { \
1182 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1183 } \
1184 } while(0)
1185
1186 #define kvm_call_hyp_ret(f, ...) \
1187 ({ \
1188 typeof(f(__VA_ARGS__)) ret; \
1189 \
1190 if (has_vhe()) { \
1191 ret = f(__VA_ARGS__); \
1192 isb(); \
1193 } else { \
1194 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1195 } \
1196 \
1197 ret; \
1198 })
1199 #else /* __KVM_NVHE_HYPERVISOR__ */
1200 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
1201 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
1202 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
1203 #endif /* __KVM_NVHE_HYPERVISOR__ */
1204
1205 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
1206 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
1207
1208 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
1209 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
1210 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
1211 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
1212 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
1213 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
1214 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
1215
1216 void kvm_sys_regs_create_debugfs(struct kvm *kvm);
1217 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
1218
1219 int __init kvm_sys_reg_table_init(void);
1220 struct sys_reg_desc;
1221 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
1222 unsigned int idx);
1223 int __init populate_nv_trap_config(void);
1224
1225 bool lock_all_vcpus(struct kvm *kvm);
1226 void unlock_all_vcpus(struct kvm *kvm);
1227
1228 void kvm_calculate_traps(struct kvm_vcpu *vcpu);
1229
1230 /* MMIO helpers */
1231 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
1232 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
1233
1234 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1235 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1236
1237 /*
1238 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1239 * arrived in guest context. For arm64, any event that arrives while a vCPU is
1240 * loaded is considered to be "in guest".
1241 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1242 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1243 {
1244 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1245 }
1246
1247 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1248 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1249 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1250
1251 bool kvm_arm_pvtime_supported(void);
1252 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1253 struct kvm_device_attr *attr);
1254 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1255 struct kvm_device_attr *attr);
1256 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1257 struct kvm_device_attr *attr);
1258
1259 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1260 int __init kvm_arm_vmid_alloc_init(void);
1261 void __init kvm_arm_vmid_alloc_free(void);
1262 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1263 void kvm_arm_vmid_clear_active(void);
1264
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1265 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1266 {
1267 vcpu_arch->steal.base = INVALID_GPA;
1268 }
1269
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1270 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1271 {
1272 return (vcpu_arch->steal.base != INVALID_GPA);
1273 }
1274
1275 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1276
1277 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1278
1279 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1280
1281 /*
1282 * How we access per-CPU host data depends on the where we access it from,
1283 * and the mode we're in:
1284 *
1285 * - VHE and nVHE hypervisor bits use their locally defined instance
1286 *
1287 * - the rest of the kernel use either the VHE or nVHE one, depending on
1288 * the mode we're running in.
1289 *
1290 * Unless we're in protected mode, fully deprivileged, and the nVHE
1291 * per-CPU stuff is exclusively accessible to the protected EL2 code.
1292 * In this case, the EL1 code uses the *VHE* data as its private state
1293 * (which makes sense in a way as there shouldn't be any shared state
1294 * between the host and the hypervisor).
1295 *
1296 * Yes, this is all totally trivial. Shoot me now.
1297 */
1298 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
1299 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f)
1300 #else
1301 #define host_data_ptr(f) \
1302 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \
1303 &this_cpu_ptr(&kvm_host_data)->f : \
1304 &this_cpu_ptr_hyp_sym(kvm_host_data)->f)
1305 #endif
1306
1307 #define host_data_test_flag(flag) \
1308 (test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)))
1309 #define host_data_set_flag(flag) \
1310 set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1311 #define host_data_clear_flag(flag) \
1312 clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1313
1314 /* Check whether the FP regs are owned by the guest */
guest_owns_fp_regs(void)1315 static inline bool guest_owns_fp_regs(void)
1316 {
1317 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED;
1318 }
1319
1320 /* Check whether the FP regs are owned by the host */
host_owns_fp_regs(void)1321 static inline bool host_owns_fp_regs(void)
1322 {
1323 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED;
1324 }
1325
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1326 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1327 {
1328 /* The host's MPIDR is immutable, so let's set it up at boot time */
1329 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1330 }
1331
kvm_system_needs_idmapped_vectors(void)1332 static inline bool kvm_system_needs_idmapped_vectors(void)
1333 {
1334 return cpus_have_final_cap(ARM64_SPECTRE_V3A);
1335 }
1336
kvm_arch_sync_events(struct kvm * kvm)1337 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1338
1339 void kvm_init_host_debug_data(void);
1340 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu);
1341 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu);
1342 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu);
1343 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val);
1344
1345 #define kvm_vcpu_os_lock_enabled(vcpu) \
1346 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1347
1348 #define kvm_debug_regs_in_use(vcpu) \
1349 ((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE)
1350 #define kvm_host_owns_debug_regs(vcpu) \
1351 ((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED)
1352 #define kvm_guest_owns_debug_regs(vcpu) \
1353 ((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED)
1354
1355 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1356 struct kvm_device_attr *attr);
1357 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1358 struct kvm_device_attr *attr);
1359 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1360 struct kvm_device_attr *attr);
1361
1362 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1363 struct kvm_arm_copy_mte_tags *copy_tags);
1364 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1365 struct kvm_arm_counter_offset *offset);
1366 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
1367 struct reg_mask_range *range);
1368
1369 /* Guest/host FPSIMD coordination helpers */
1370 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1371 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1372 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1373 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1374 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1375
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1376 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1377 {
1378 return (!has_vhe() && attr->exclude_host);
1379 }
1380
1381 #ifdef CONFIG_KVM
1382 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr);
1383 void kvm_clr_pmu_events(u64 clr);
1384 bool kvm_set_pmuserenr(u64 val);
1385 void kvm_enable_trbe(void);
1386 void kvm_disable_trbe(void);
1387 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest);
1388 #else
kvm_set_pmu_events(u64 set,struct perf_event_attr * attr)1389 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u64 clr)1390 static inline void kvm_clr_pmu_events(u64 clr) {}
kvm_set_pmuserenr(u64 val)1391 static inline bool kvm_set_pmuserenr(u64 val)
1392 {
1393 return false;
1394 }
kvm_enable_trbe(void)1395 static inline void kvm_enable_trbe(void) {}
kvm_disable_trbe(void)1396 static inline void kvm_disable_trbe(void) {}
kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest)1397 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {}
1398 #endif
1399
1400 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
1401 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
1402
1403 int __init kvm_set_ipa_limit(void);
1404 u32 kvm_get_pa_bits(struct kvm *kvm);
1405
1406 #define __KVM_HAVE_ARCH_VM_ALLOC
1407 struct kvm *kvm_arch_alloc_vm(void);
1408
1409 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1410
1411 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1412
1413 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled)
1414
1415 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm)
1416
1417 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1418 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1419
1420 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1421
1422 #define kvm_has_mte(kvm) \
1423 (system_supports_mte() && \
1424 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1425
1426 #define kvm_supports_32bit_el0() \
1427 (system_supports_32bit_el0() && \
1428 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1429
1430 #define kvm_vm_has_ran_once(kvm) \
1431 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1432
__vcpu_has_feature(const struct kvm_arch * ka,int feature)1433 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
1434 {
1435 return test_bit(feature, ka->vcpu_features);
1436 }
1437
1438 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f))
1439 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f))
1440
1441 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED)
1442
1443 int kvm_trng_call(struct kvm_vcpu *vcpu);
1444 #ifdef CONFIG_KVM
1445 extern phys_addr_t hyp_mem_base;
1446 extern phys_addr_t hyp_mem_size;
1447 void __init kvm_hyp_reserve(void);
1448 #else
kvm_hyp_reserve(void)1449 static inline void kvm_hyp_reserve(void) { }
1450 #endif
1451
1452 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1453 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1454
__vm_id_reg(struct kvm_arch * ka,u32 reg)1455 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg)
1456 {
1457 switch (reg) {
1458 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7):
1459 return &ka->id_regs[IDREG_IDX(reg)];
1460 case SYS_CTR_EL0:
1461 return &ka->ctr_el0;
1462 default:
1463 WARN_ON_ONCE(1);
1464 return NULL;
1465 }
1466 }
1467
1468 #define kvm_read_vm_id_reg(kvm, reg) \
1469 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; })
1470
1471 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
1472
1473 #define __expand_field_sign_unsigned(id, fld, val) \
1474 ((u64)SYS_FIELD_VALUE(id, fld, val))
1475
1476 #define __expand_field_sign_signed(id, fld, val) \
1477 ({ \
1478 u64 __val = SYS_FIELD_VALUE(id, fld, val); \
1479 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1480 })
1481
1482 #define get_idreg_field_unsigned(kvm, id, fld) \
1483 ({ \
1484 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \
1485 FIELD_GET(id##_##fld##_MASK, __val); \
1486 })
1487
1488 #define get_idreg_field_signed(kvm, id, fld) \
1489 ({ \
1490 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \
1491 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1492 })
1493
1494 #define get_idreg_field_enum(kvm, id, fld) \
1495 get_idreg_field_unsigned(kvm, id, fld)
1496
1497 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \
1498 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit))
1499
1500 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \
1501 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit))
1502
1503 #define kvm_cmp_feat(kvm, id, fld, op, limit) \
1504 (id##_##fld##_SIGNED ? \
1505 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \
1506 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit))
1507
1508 #define kvm_has_feat(kvm, id, fld, limit) \
1509 kvm_cmp_feat(kvm, id, fld, >=, limit)
1510
1511 #define kvm_has_feat_enum(kvm, id, fld, val) \
1512 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val)
1513
1514 #define kvm_has_feat_range(kvm, id, fld, min, max) \
1515 (kvm_cmp_feat(kvm, id, fld, >=, min) && \
1516 kvm_cmp_feat(kvm, id, fld, <=, max))
1517
1518 /* Check for a given level of PAuth support */
1519 #define kvm_has_pauth(k, l) \
1520 ({ \
1521 bool pa, pi, pa3; \
1522 \
1523 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \
1524 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \
1525 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \
1526 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \
1527 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \
1528 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \
1529 \
1530 (pa + pi + pa3) == 1; \
1531 })
1532
1533 #define kvm_has_fpmr(k) \
1534 (system_supports_fpmr() && \
1535 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
1536
1537 #define kvm_has_tcr2(k) \
1538 (kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP))
1539
1540 #define kvm_has_s1pie(k) \
1541 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP))
1542
1543 #define kvm_has_s1poe(k) \
1544 (kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP))
1545
1546 #endif /* __ARM64_KVM_HOST_H__ */
1547