1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors 4 * 5 * Copyright (c) 2010 Ericsson AB. 6 * 7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>. 8 * 9 * JC42.4 compliant temperature sensors are typically used on memory modules. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/slab.h> 18 #include <linux/jiffies.h> 19 #include <linux/i2c.h> 20 #include <linux/hwmon.h> 21 #include <linux/err.h> 22 #include <linux/regmap.h> 23 24 /* Addresses to scan */ 25 static const unsigned short normal_i2c[] = { 26 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END }; 27 28 /* JC42 registers. All registers are 16 bit. */ 29 #define JC42_REG_CAP 0x00 30 #define JC42_REG_CONFIG 0x01 31 #define JC42_REG_TEMP_UPPER 0x02 32 #define JC42_REG_TEMP_LOWER 0x03 33 #define JC42_REG_TEMP_CRITICAL 0x04 34 #define JC42_REG_TEMP 0x05 35 #define JC42_REG_MANID 0x06 36 #define JC42_REG_DEVICEID 0x07 37 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */ 38 39 /* Status bits in temperature register */ 40 #define JC42_ALARM_CRIT BIT(15) 41 #define JC42_ALARM_MAX BIT(14) 42 #define JC42_ALARM_MIN BIT(13) 43 44 /* Configuration register defines */ 45 #define JC42_CFG_CRIT_ONLY BIT(2) 46 #define JC42_CFG_TCRIT_LOCK BIT(6) 47 #define JC42_CFG_EVENT_LOCK BIT(7) 48 #define JC42_CFG_SHUTDOWN BIT(8) 49 #define JC42_CFG_HYST_MASK GENMASK(10, 9) 50 51 /* Capabilities */ 52 #define JC42_CAP_RANGE BIT(2) 53 54 /* Manufacturer IDs */ 55 #define ADT_MANID 0x11d4 /* Analog Devices */ 56 #define ATMEL_MANID 0x001f /* Atmel */ 57 #define ATMEL_MANID2 0x1114 /* Atmel */ 58 #define MAX_MANID 0x004d /* Maxim */ 59 #define IDT_MANID 0x00b3 /* IDT */ 60 #define MCP_MANID 0x0054 /* Microchip */ 61 #define NXP_MANID 0x1131 /* NXP Semiconductors */ 62 #define ONS_MANID 0x1b09 /* ON Semiconductor */ 63 #define STM_MANID 0x104a /* ST Microelectronics */ 64 #define GT_MANID 0x1c68 /* Giantec */ 65 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */ 66 #define SI_MANID 0x1c85 /* Seiko Instruments */ 67 68 /* SMBUS register */ 69 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */ 70 71 /* Supported chips */ 72 73 /* Analog Devices */ 74 #define ADT7408_DEVID 0x0801 75 #define ADT7408_DEVID_MASK 0xffff 76 77 /* Atmel */ 78 #define AT30TS00_DEVID 0x8201 79 #define AT30TS00_DEVID_MASK 0xffff 80 81 #define GT34TS02_DEVID 0x3300 82 #define GT34TS02_DEVID_MASK 0xff00 83 84 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */ 85 #define TS3000_DEVID_MASK 0xff00 86 87 #define TS3001_DEVID 0x3000 88 #define TS3001_DEVID_MASK 0xff00 89 90 /* Maxim */ 91 #define MAX6604_DEVID 0x3e00 92 #define MAX6604_DEVID_MASK 0xffff 93 94 /* Microchip */ 95 #define MCP9804_DEVID 0x0200 96 #define MCP9804_DEVID_MASK 0xfffc 97 98 #define MCP9808_DEVID 0x0400 99 #define MCP9808_DEVID_MASK 0xfffc 100 101 #define MCP98242_DEVID 0x2000 102 #define MCP98242_DEVID_MASK 0xfffc 103 104 #define MCP98243_DEVID 0x2100 105 #define MCP98243_DEVID_MASK 0xfffc 106 107 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */ 108 #define MCP9843_DEVID_MASK 0xfffe 109 110 /* NXP */ 111 #define SE97_DEVID 0xa200 112 #define SE97_DEVID_MASK 0xfffc 113 114 #define SE98_DEVID 0xa100 115 #define SE98_DEVID_MASK 0xfffc 116 117 /* ON Semiconductor */ 118 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */ 119 #define CAT6095_DEVID_MASK 0xffe0 120 121 #define CAT34TS02C_DEVID 0x0a00 122 #define CAT34TS02C_DEVID_MASK 0xfff0 123 124 /* ST Microelectronics */ 125 #define STTS424_DEVID 0x0101 126 #define STTS424_DEVID_MASK 0xffff 127 128 #define STTS424E_DEVID 0x0000 129 #define STTS424E_DEVID_MASK 0xfffe 130 131 #define STTS2002_DEVID 0x0300 132 #define STTS2002_DEVID_MASK 0xffff 133 134 #define STTS3000_DEVID 0x0200 135 #define STTS3000_DEVID_MASK 0xffff 136 137 /* TSE2004 compliant sensors */ 138 #define TSE2004_DEVID 0x2200 139 #define TSE2004_DEVID_MASK 0xff00 140 141 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 }; 142 143 struct jc42_chips { 144 u16 manid; 145 u16 devid; 146 u16 devid_mask; 147 }; 148 149 static struct jc42_chips jc42_chips[] = { 150 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK }, 151 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK }, 152 { ATMEL_MANID2, TSE2004_DEVID, TSE2004_DEVID_MASK }, 153 { GT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 154 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK }, 155 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 156 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK }, 157 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK }, 158 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK }, 159 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK }, 160 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK }, 161 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK }, 162 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK }, 163 { MCP_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 164 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK }, 165 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK }, 166 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK }, 167 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK }, 168 { ONS_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 169 { ONS_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 170 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK }, 171 { SI_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 172 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK }, 173 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK }, 174 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK }, 175 { STM_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK }, 176 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK }, 177 }; 178 179 /* Each client has this additional data */ 180 struct jc42_data { 181 struct regmap *regmap; 182 bool extended; /* true if extended range supported */ 183 bool valid; 184 u16 orig_config; /* original configuration */ 185 u16 config; /* current configuration */ 186 }; 187 188 #define JC42_TEMP_MIN_EXTENDED (-40000) 189 #define JC42_TEMP_MIN 0 190 #define JC42_TEMP_MAX 125000 191 192 static u16 jc42_temp_to_reg(long temp, bool extended) 193 { 194 int ntemp = clamp_val(temp, 195 extended ? JC42_TEMP_MIN_EXTENDED : 196 JC42_TEMP_MIN, JC42_TEMP_MAX); 197 198 /* convert from 0.001 to 0.0625 resolution */ 199 return (ntemp * 2 / 125) & 0x1fff; 200 } 201 202 static int jc42_temp_from_reg(s16 reg) 203 { 204 reg = sign_extend32(reg, 12); 205 206 /* convert from 0.0625 to 0.001 resolution */ 207 return reg * 125 / 2; 208 } 209 210 static int jc42_read(struct device *dev, enum hwmon_sensor_types type, 211 u32 attr, int channel, long *val) 212 { 213 struct jc42_data *data = dev_get_drvdata(dev); 214 unsigned int regval; 215 int ret, temp, hyst; 216 217 switch (attr) { 218 case hwmon_temp_input: 219 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val); 220 if (ret) 221 break; 222 223 *val = jc42_temp_from_reg(regval); 224 break; 225 case hwmon_temp_min: 226 ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, ®val); 227 if (ret) 228 break; 229 230 *val = jc42_temp_from_reg(regval); 231 break; 232 case hwmon_temp_max: 233 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val); 234 if (ret) 235 break; 236 237 *val = jc42_temp_from_reg(regval); 238 break; 239 case hwmon_temp_crit: 240 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL, 241 ®val); 242 if (ret) 243 break; 244 245 *val = jc42_temp_from_reg(regval); 246 break; 247 case hwmon_temp_max_hyst: 248 ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, ®val); 249 if (ret) 250 break; 251 252 temp = jc42_temp_from_reg(regval); 253 hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK, 254 data->config)]; 255 *val = temp - hyst; 256 break; 257 case hwmon_temp_crit_hyst: 258 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL, 259 ®val); 260 if (ret) 261 break; 262 263 temp = jc42_temp_from_reg(regval); 264 hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK, 265 data->config)]; 266 *val = temp - hyst; 267 break; 268 case hwmon_temp_min_alarm: 269 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val); 270 if (ret) 271 break; 272 273 *val = FIELD_GET(JC42_ALARM_MIN, regval); 274 break; 275 case hwmon_temp_max_alarm: 276 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val); 277 if (ret) 278 break; 279 280 *val = FIELD_GET(JC42_ALARM_MAX, regval); 281 break; 282 case hwmon_temp_crit_alarm: 283 ret = regmap_read(data->regmap, JC42_REG_TEMP, ®val); 284 if (ret) 285 break; 286 287 *val = FIELD_GET(JC42_ALARM_CRIT, regval); 288 break; 289 default: 290 ret = -EOPNOTSUPP; 291 break; 292 } 293 294 return ret; 295 } 296 297 static int jc42_write(struct device *dev, enum hwmon_sensor_types type, 298 u32 attr, int channel, long val) 299 { 300 struct jc42_data *data = dev_get_drvdata(dev); 301 unsigned int regval; 302 int diff, hyst; 303 int ret; 304 305 switch (attr) { 306 case hwmon_temp_min: 307 ret = regmap_write(data->regmap, JC42_REG_TEMP_LOWER, 308 jc42_temp_to_reg(val, data->extended)); 309 break; 310 case hwmon_temp_max: 311 ret = regmap_write(data->regmap, JC42_REG_TEMP_UPPER, 312 jc42_temp_to_reg(val, data->extended)); 313 break; 314 case hwmon_temp_crit: 315 ret = regmap_write(data->regmap, JC42_REG_TEMP_CRITICAL, 316 jc42_temp_to_reg(val, data->extended)); 317 break; 318 case hwmon_temp_crit_hyst: 319 ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL, 320 ®val); 321 if (ret) 322 break; 323 324 /* 325 * JC42.4 compliant chips only support four hysteresis values. 326 * Pick best choice and go from there. 327 */ 328 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED 329 : JC42_TEMP_MIN) - 6000, 330 JC42_TEMP_MAX); 331 diff = jc42_temp_from_reg(regval) - val; 332 hyst = 0; 333 if (diff > 0) { 334 if (diff < 2250) 335 hyst = 1; /* 1.5 degrees C */ 336 else if (diff < 4500) 337 hyst = 2; /* 3.0 degrees C */ 338 else 339 hyst = 3; /* 6.0 degrees C */ 340 } 341 data->config = (data->config & ~JC42_CFG_HYST_MASK) | 342 FIELD_PREP(JC42_CFG_HYST_MASK, hyst); 343 ret = regmap_write(data->regmap, JC42_REG_CONFIG, 344 data->config); 345 break; 346 default: 347 ret = -EOPNOTSUPP; 348 break; 349 } 350 351 return ret; 352 } 353 354 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type, 355 u32 attr, int channel) 356 { 357 const struct jc42_data *data = _data; 358 unsigned int config = data->config; 359 umode_t mode = 0444; 360 361 switch (attr) { 362 case hwmon_temp_min: 363 case hwmon_temp_max: 364 if (!(config & JC42_CFG_EVENT_LOCK)) 365 mode |= 0200; 366 break; 367 case hwmon_temp_crit: 368 if (!(config & JC42_CFG_TCRIT_LOCK)) 369 mode |= 0200; 370 break; 371 case hwmon_temp_crit_hyst: 372 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK))) 373 mode |= 0200; 374 break; 375 case hwmon_temp_input: 376 case hwmon_temp_max_hyst: 377 case hwmon_temp_min_alarm: 378 case hwmon_temp_max_alarm: 379 case hwmon_temp_crit_alarm: 380 break; 381 default: 382 mode = 0; 383 break; 384 } 385 return mode; 386 } 387 388 /* Return 0 if detection is successful, -ENODEV otherwise */ 389 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info) 390 { 391 struct i2c_adapter *adapter = client->adapter; 392 int i, config, cap, manid, devid; 393 394 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | 395 I2C_FUNC_SMBUS_WORD_DATA)) 396 return -ENODEV; 397 398 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP); 399 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG); 400 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID); 401 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID); 402 403 if (cap < 0 || config < 0 || manid < 0 || devid < 0) 404 return -ENODEV; 405 406 if ((cap & 0xff00) || (config & 0xf820)) 407 return -ENODEV; 408 409 if ((devid & TSE2004_DEVID_MASK) == TSE2004_DEVID && 410 (cap & 0x0062) != 0x0062) 411 return -ENODEV; 412 413 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) { 414 struct jc42_chips *chip = &jc42_chips[i]; 415 if (manid == chip->manid && 416 (devid & chip->devid_mask) == chip->devid) { 417 strscpy(info->type, "jc42", I2C_NAME_SIZE); 418 return 0; 419 } 420 } 421 return -ENODEV; 422 } 423 424 static const struct hwmon_channel_info * const jc42_info[] = { 425 HWMON_CHANNEL_INFO(chip, 426 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL), 427 HWMON_CHANNEL_INFO(temp, 428 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | 429 HWMON_T_CRIT | HWMON_T_MAX_HYST | 430 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM | 431 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM), 432 NULL 433 }; 434 435 static const struct hwmon_ops jc42_hwmon_ops = { 436 .is_visible = jc42_is_visible, 437 .read = jc42_read, 438 .write = jc42_write, 439 }; 440 441 static const struct hwmon_chip_info jc42_chip_info = { 442 .ops = &jc42_hwmon_ops, 443 .info = jc42_info, 444 }; 445 446 static bool jc42_readable_reg(struct device *dev, unsigned int reg) 447 { 448 return (reg >= JC42_REG_CAP && reg <= JC42_REG_DEVICEID) || 449 reg == JC42_REG_SMBUS; 450 } 451 452 static bool jc42_writable_reg(struct device *dev, unsigned int reg) 453 { 454 return (reg >= JC42_REG_CONFIG && reg <= JC42_REG_TEMP_CRITICAL) || 455 reg == JC42_REG_SMBUS; 456 } 457 458 static bool jc42_volatile_reg(struct device *dev, unsigned int reg) 459 { 460 return reg == JC42_REG_CONFIG || reg == JC42_REG_TEMP; 461 } 462 463 static const struct regmap_config jc42_regmap_config = { 464 .reg_bits = 8, 465 .val_bits = 16, 466 .val_format_endian = REGMAP_ENDIAN_BIG, 467 .max_register = JC42_REG_SMBUS, 468 .writeable_reg = jc42_writable_reg, 469 .readable_reg = jc42_readable_reg, 470 .volatile_reg = jc42_volatile_reg, 471 .cache_type = REGCACHE_MAPLE, 472 }; 473 474 static int jc42_probe(struct i2c_client *client) 475 { 476 struct device *dev = &client->dev; 477 struct device *hwmon_dev; 478 unsigned int config, cap; 479 struct jc42_data *data; 480 int ret; 481 482 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL); 483 if (!data) 484 return -ENOMEM; 485 486 data->regmap = devm_regmap_init_i2c(client, &jc42_regmap_config); 487 if (IS_ERR(data->regmap)) 488 return PTR_ERR(data->regmap); 489 490 i2c_set_clientdata(client, data); 491 492 ret = regmap_read(data->regmap, JC42_REG_CAP, &cap); 493 if (ret) 494 return ret; 495 496 data->extended = !!(cap & JC42_CAP_RANGE); 497 498 if (device_property_read_bool(dev, "smbus-timeout-disable")) { 499 /* 500 * Not all chips support this register, but from a 501 * quick read of various datasheets no chip appears 502 * incompatible with the below attempt to disable 503 * the timeout. And the whole thing is opt-in... 504 */ 505 ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS, 506 SMBUS_STMOUT); 507 if (ret) 508 return ret; 509 } 510 511 ret = regmap_read(data->regmap, JC42_REG_CONFIG, &config); 512 if (ret) 513 return ret; 514 515 data->orig_config = config; 516 if (config & JC42_CFG_SHUTDOWN) { 517 config &= ~JC42_CFG_SHUTDOWN; 518 regmap_write(data->regmap, JC42_REG_CONFIG, config); 519 } 520 data->config = config; 521 522 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42", 523 data, &jc42_chip_info, 524 NULL); 525 return PTR_ERR_OR_ZERO(hwmon_dev); 526 } 527 528 static void jc42_remove(struct i2c_client *client) 529 { 530 struct jc42_data *data = i2c_get_clientdata(client); 531 532 /* Restore original configuration except hysteresis */ 533 if ((data->config & ~JC42_CFG_HYST_MASK) != 534 (data->orig_config & ~JC42_CFG_HYST_MASK)) { 535 int config; 536 537 config = (data->orig_config & ~JC42_CFG_HYST_MASK) 538 | (data->config & JC42_CFG_HYST_MASK); 539 regmap_write(data->regmap, JC42_REG_CONFIG, config); 540 } 541 } 542 543 #ifdef CONFIG_PM 544 545 static int jc42_suspend(struct device *dev) 546 { 547 struct jc42_data *data = dev_get_drvdata(dev); 548 549 data->config |= JC42_CFG_SHUTDOWN; 550 regmap_write(data->regmap, JC42_REG_CONFIG, data->config); 551 552 regcache_cache_only(data->regmap, true); 553 regcache_mark_dirty(data->regmap); 554 555 return 0; 556 } 557 558 static int jc42_resume(struct device *dev) 559 { 560 struct jc42_data *data = dev_get_drvdata(dev); 561 562 regcache_cache_only(data->regmap, false); 563 564 data->config &= ~JC42_CFG_SHUTDOWN; 565 regmap_write(data->regmap, JC42_REG_CONFIG, data->config); 566 567 /* Restore cached register values to hardware */ 568 return regcache_sync(data->regmap); 569 } 570 571 static const struct dev_pm_ops jc42_dev_pm_ops = { 572 .suspend = jc42_suspend, 573 .resume = jc42_resume, 574 }; 575 576 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops) 577 #else 578 #define JC42_DEV_PM_OPS NULL 579 #endif /* CONFIG_PM */ 580 581 static const struct i2c_device_id jc42_id[] = { 582 { "jc42" }, 583 { } 584 }; 585 MODULE_DEVICE_TABLE(i2c, jc42_id); 586 587 static const struct of_device_id jc42_of_ids[] = { 588 { .compatible = "jedec,jc-42.4-temp", }, 589 { } 590 }; 591 MODULE_DEVICE_TABLE(of, jc42_of_ids); 592 593 static struct i2c_driver jc42_driver = { 594 .class = I2C_CLASS_HWMON, 595 .driver = { 596 .name = "jc42", 597 .pm = JC42_DEV_PM_OPS, 598 .of_match_table = jc42_of_ids, 599 }, 600 .probe = jc42_probe, 601 .remove = jc42_remove, 602 .id_table = jc42_id, 603 .detect = jc42_detect, 604 .address_list = normal_i2c, 605 }; 606 607 module_i2c_driver(jc42_driver); 608 609 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>"); 610 MODULE_DESCRIPTION("JC42 driver"); 611 MODULE_LICENSE("GPL"); 612