xref: /linux/drivers/iio/adc/stm32-adc-core.h (revision c26f4fbd58375bd6ef74f95eb73d61762ad97c59)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * This file is part of STM32 ADC driver
4  *
5  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7  *
8  */
9 
10 #ifndef __STM32_ADC_H
11 #define __STM32_ADC_H
12 
13 #include <linux/bitfield.h>
14 #include <linux/bits.h>
15 
16 /*
17  * STM32 - ADC global register map
18  * ________________________________________________________
19  * | Offset |                 Register                    |
20  * --------------------------------------------------------
21  * | 0x000  |                Master ADC1                  |
22  * --------------------------------------------------------
23  * | 0x100  |                Slave ADC2                   |
24  * --------------------------------------------------------
25  * | 0x200  |                Slave ADC3                   |
26  * --------------------------------------------------------
27  * | 0x300  |         Master & Slave common regs          |
28  * --------------------------------------------------------
29  */
30 /* Maximum ADC instances number per ADC block for all supported SoCs */
31 #define STM32_ADC_MAX_ADCS		3
32 #define STM32_ADC_OFFSET		0x100
33 #define STM32_ADCX_COMN_OFFSET		0x300
34 
35 /* STM32F4 - Registers for each ADC instance */
36 #define STM32F4_ADC_SR			0x00
37 #define STM32F4_ADC_CR1			0x04
38 #define STM32F4_ADC_CR2			0x08
39 #define STM32F4_ADC_SMPR1		0x0C
40 #define STM32F4_ADC_SMPR2		0x10
41 #define STM32F4_ADC_HTR			0x24
42 #define STM32F4_ADC_LTR			0x28
43 #define STM32F4_ADC_SQR1		0x2C
44 #define STM32F4_ADC_SQR2		0x30
45 #define STM32F4_ADC_SQR3		0x34
46 #define STM32F4_ADC_JSQR		0x38
47 #define STM32F4_ADC_JDR1		0x3C
48 #define STM32F4_ADC_JDR2		0x40
49 #define STM32F4_ADC_JDR3		0x44
50 #define STM32F4_ADC_JDR4		0x48
51 #define STM32F4_ADC_DR			0x4C
52 
53 /* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
54 #define STM32F4_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
55 #define STM32F4_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x04)
56 
57 /* STM32F4_ADC_SR - bit fields */
58 #define STM32F4_OVR			BIT(5)
59 #define STM32F4_STRT			BIT(4)
60 #define STM32F4_EOC			BIT(1)
61 
62 /* STM32F4_ADC_CR1 - bit fields */
63 #define STM32F4_OVRIE			BIT(26)
64 #define STM32F4_RES_SHIFT		24
65 #define STM32F4_RES_MASK		GENMASK(25, 24)
66 #define STM32F4_SCAN			BIT(8)
67 #define STM32F4_EOCIE			BIT(5)
68 
69 /* STM32F4_ADC_CR2 - bit fields */
70 #define STM32F4_SWSTART			BIT(30)
71 #define STM32F4_EXTEN_SHIFT		28
72 #define STM32F4_EXTEN_MASK		GENMASK(29, 28)
73 #define STM32F4_EXTSEL_SHIFT		24
74 #define STM32F4_EXTSEL_MASK		GENMASK(27, 24)
75 #define STM32F4_EOCS			BIT(10)
76 #define STM32F4_DDS			BIT(9)
77 #define STM32F4_DMA			BIT(8)
78 #define STM32F4_ADON			BIT(0)
79 
80 /* STM32F4_ADC_CSR - bit fields */
81 #define STM32F4_OVR3			BIT(21)
82 #define STM32F4_EOC3			BIT(17)
83 #define STM32F4_OVR2			BIT(13)
84 #define STM32F4_EOC2			BIT(9)
85 #define STM32F4_OVR1			BIT(5)
86 #define STM32F4_EOC1			BIT(1)
87 
88 /* STM32F4_ADC_CCR - bit fields */
89 #define STM32F4_ADC_ADCPRE_SHIFT	16
90 #define STM32F4_ADC_ADCPRE_MASK		GENMASK(17, 16)
91 
92 /* STM32H7 - Registers for each ADC instance */
93 #define STM32H7_ADC_ISR			0x00
94 #define STM32H7_ADC_IER			0x04
95 #define STM32H7_ADC_CR			0x08
96 #define STM32H7_ADC_CFGR		0x0C
97 #define STM32H7_ADC_CFGR2		0x10
98 #define STM32H7_ADC_SMPR1		0x14
99 #define STM32H7_ADC_SMPR2		0x18
100 #define STM32H7_ADC_PCSEL		0x1C
101 #define STM32H7_ADC_SQR1		0x30
102 #define STM32H7_ADC_SQR2		0x34
103 #define STM32H7_ADC_SQR3		0x38
104 #define STM32H7_ADC_SQR4		0x3C
105 #define STM32H7_ADC_DR			0x40
106 #define STM32H7_ADC_DIFSEL		0xC0
107 #define STM32H7_ADC_CALFACT		0xC4
108 #define STM32H7_ADC_CALFACT2		0xC8
109 
110 /* STM32MP1 - ADC2 instance option register */
111 #define STM32MP1_ADC2_OR		0xD0
112 
113 /* STM32MP1 - Identification registers */
114 #define STM32MP1_ADC_HWCFGR0		0x3F0
115 #define STM32MP1_ADC_VERR		0x3F4
116 #define STM32MP1_ADC_IPDR		0x3F8
117 #define STM32MP1_ADC_SIDR		0x3FC
118 
119 /* STM32MP13 - Registers for each ADC instance */
120 #define STM32MP13_ADC_DIFSEL		0xB0
121 #define STM32MP13_ADC_CALFACT		0xB4
122 #define STM32MP13_ADC2_OR		0xC8
123 
124 /* STM32H7 - common registers for all ADC instances */
125 #define STM32H7_ADC_CSR			(STM32_ADCX_COMN_OFFSET + 0x00)
126 #define STM32H7_ADC_CCR			(STM32_ADCX_COMN_OFFSET + 0x08)
127 
128 /* STM32H7_ADC_ISR - bit fields */
129 #define STM32MP1_VREGREADY		BIT(12)
130 #define STM32H7_OVR			BIT(4)
131 #define STM32H7_EOC			BIT(2)
132 #define STM32H7_ADRDY			BIT(0)
133 
134 /* STM32H7_ADC_IER - bit fields */
135 #define STM32H7_OVRIE			STM32H7_OVR
136 #define STM32H7_EOCIE			STM32H7_EOC
137 
138 /* STM32H7_ADC_CR - bit fields */
139 #define STM32H7_ADCAL			BIT(31)
140 #define STM32H7_ADCALDIF		BIT(30)
141 #define STM32H7_DEEPPWD			BIT(29)
142 #define STM32H7_ADVREGEN		BIT(28)
143 #define STM32H7_LINCALRDYW6		BIT(27)
144 #define STM32H7_LINCALRDYW5		BIT(26)
145 #define STM32H7_LINCALRDYW4		BIT(25)
146 #define STM32H7_LINCALRDYW3		BIT(24)
147 #define STM32H7_LINCALRDYW2		BIT(23)
148 #define STM32H7_LINCALRDYW1		BIT(22)
149 #define STM32H7_LINCALRDYW_MASK		GENMASK(27, 22)
150 #define STM32H7_ADCALLIN		BIT(16)
151 #define STM32H7_BOOST			BIT(8)
152 #define STM32H7_ADSTP			BIT(4)
153 #define STM32H7_ADSTART			BIT(2)
154 #define STM32H7_ADDIS			BIT(1)
155 #define STM32H7_ADEN			BIT(0)
156 
157 /* STM32H7_ADC_CFGR bit fields */
158 #define STM32H7_EXTEN_SHIFT		10
159 #define STM32H7_EXTEN_MASK		GENMASK(11, 10)
160 #define STM32H7_EXTSEL_SHIFT		5
161 #define STM32H7_EXTSEL_MASK		GENMASK(9, 5)
162 #define STM32H7_RES_SHIFT		2
163 #define STM32H7_RES_MASK		GENMASK(4, 2)
164 #define STM32H7_DMNGT_SHIFT		0
165 #define STM32H7_DMNGT_MASK		GENMASK(1, 0)
166 
167 /* STM32H7_ADC_CFGR2 bit fields */
168 #define STM32H7_OVSR_MASK		GENMASK(25, 16) /* Correspond to OSVR field in datasheet */
169 #define STM32H7_OVSR(v)			FIELD_PREP(STM32H7_OVSR_MASK, v)
170 #define STM32H7_OVSS_MASK		GENMASK(8, 5)
171 #define STM32H7_OVSS(v)			FIELD_PREP(STM32H7_OVSS_MASK, v)
172 #define STM32H7_ROVSE			BIT(0)
173 
174 enum stm32h7_adc_dmngt {
175 	STM32H7_DMNGT_DR_ONLY,		/* Regular data in DR only */
176 	STM32H7_DMNGT_DMA_ONESHOT,	/* DMA one shot mode */
177 	STM32H7_DMNGT_DFSDM,		/* DFSDM mode */
178 	STM32H7_DMNGT_DMA_CIRC,		/* DMA circular mode */
179 };
180 
181 /* STM32H7_ADC_DIFSEL - bit fields */
182 #define STM32H7_DIFSEL_MASK		GENMASK(19, 0)
183 
184 /* STM32H7_ADC_CALFACT - bit fields */
185 #define STM32H7_CALFACT_D_SHIFT		16
186 #define STM32H7_CALFACT_D_MASK		GENMASK(26, 16)
187 #define STM32H7_CALFACT_S_SHIFT		0
188 #define STM32H7_CALFACT_S_MASK		GENMASK(10, 0)
189 
190 /* STM32H7_ADC_CALFACT2 - bit fields */
191 #define STM32H7_LINCALFACT_SHIFT	0
192 #define STM32H7_LINCALFACT_MASK		GENMASK(29, 0)
193 
194 /* STM32H7_ADC_CSR - bit fields */
195 #define STM32H7_OVR_SLV			BIT(20)
196 #define STM32H7_EOC_SLV			BIT(18)
197 #define STM32H7_OVR_MST			BIT(4)
198 #define STM32H7_EOC_MST			BIT(2)
199 
200 /* STM32H7_ADC_CCR - bit fields */
201 #define STM32H7_VBATEN			BIT(24)
202 #define STM32H7_VREFEN			BIT(22)
203 #define STM32H7_PRESC_SHIFT		18
204 #define STM32H7_PRESC_MASK		GENMASK(21, 18)
205 #define STM32H7_CKMODE_SHIFT		16
206 #define STM32H7_CKMODE_MASK		GENMASK(17, 16)
207 
208 /* STM32MP1_ADC2_OR - bit fields */
209 #define STM32MP1_VDDCOREEN		BIT(0)
210 
211 /* STM32MP1_ADC_HWCFGR0 - bit fields */
212 #define STM32MP1_ADCNUM_SHIFT		0
213 #define STM32MP1_ADCNUM_MASK		GENMASK(3, 0)
214 #define STM32MP1_MULPIPE_SHIFT		4
215 #define STM32MP1_MULPIPE_MASK		GENMASK(7, 4)
216 #define STM32MP1_OPBITS_SHIFT		8
217 #define STM32MP1_OPBITS_MASK		GENMASK(11, 8)
218 #define STM32MP1_IDLEVALUE_SHIFT	12
219 #define STM32MP1_IDLEVALUE_MASK	GENMASK(15, 12)
220 
221 /* STM32MP1_ADC_VERR - bit fields */
222 #define STM32MP1_MINREV_SHIFT		0
223 #define STM32MP1_MINREV_MASK		GENMASK(3, 0)
224 #define STM32MP1_MAJREV_SHIFT		4
225 #define STM32MP1_MAJREV_MASK		GENMASK(7, 4)
226 
227 /* STM32MP1_ADC_IPDR - bit fields */
228 #define STM32MP1_IPIDR_MASK		GENMASK(31, 0)
229 
230 /* STM32MP1_ADC_SIDR - bit fields */
231 #define STM32MP1_SIDR_MASK		GENMASK(31, 0)
232 
233 /* STM32MP13_ADC_CFGR specific bit fields */
234 #define STM32MP13_DMAEN			BIT(0)
235 #define STM32MP13_DMACFG		BIT(1)
236 #define STM32MP13_DFSDMCFG		BIT(2)
237 #define STM32MP13_RES_SHIFT		3
238 #define STM32MP13_RES_MASK		GENMASK(4, 3)
239 
240 /* STM32MP13_ADC_CFGR2 bit fields */
241 #define STM32MP13_OVSR_MASK		GENMASK(4, 2)
242 #define STM32MP13_OVSR(v)		FIELD_PREP(STM32MP13_OVSR_MASK, v)
243 #define STM32MP13_OVSS_MASK		GENMASK(8, 5)
244 #define STM32MP13_OVSS(v)		FIELD_PREP(STM32MP13_OVSS_MASK, v)
245 
246 /* STM32MP13_ADC_DIFSEL - bit fields */
247 #define STM32MP13_DIFSEL_MASK		GENMASK(18, 0)
248 
249 /* STM32MP13_ADC_CALFACT - bit fields */
250 #define STM32MP13_CALFACT_D_SHIFT	16
251 #define STM32MP13_CALFACT_D_MASK	GENMASK(22, 16)
252 #define STM32MP13_CALFACT_S_SHIFT	0
253 #define STM32MP13_CALFACT_S_MASK	GENMASK(6, 0)
254 
255 /* STM32MP13_ADC2_OR - bit fields */
256 #define STM32MP13_OP2			BIT(2)
257 #define STM32MP13_OP1			BIT(1)
258 #define STM32MP13_OP0			BIT(0)
259 
260 #define STM32MP15_IPIDR_NUMBER		0x00110005
261 #define STM32MP13_IPIDR_NUMBER		0x00110006
262 
263 /**
264  * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
265  * @base:		control registers base cpu addr
266  * @phys_base:		control registers base physical addr
267  * @rate:		clock rate used for analog circuitry
268  * @vref_mv:		vref voltage (mv)
269  * @lock:		spinlock
270  */
271 struct stm32_adc_common {
272 	void __iomem			*base;
273 	phys_addr_t			phys_base;
274 	unsigned long			rate;
275 	int				vref_mv;
276 	spinlock_t			lock;		/* lock for common register */
277 };
278 
279 #endif
280