1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
4 *
5 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
6 */
7
8 #include <linux/spinlock.h>
9 #include <linux/interrupt.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/memstick.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17
18 #define DRIVER_NAME "jmb38x_ms"
19
20 static bool no_dma;
21 module_param(no_dma, bool, 0644);
22
23 enum {
24 DMA_ADDRESS = 0x00,
25 BLOCK = 0x04,
26 DMA_CONTROL = 0x08,
27 TPC_P0 = 0x0c,
28 TPC_P1 = 0x10,
29 TPC = 0x14,
30 HOST_CONTROL = 0x18,
31 DATA = 0x1c,
32 STATUS = 0x20,
33 INT_STATUS = 0x24,
34 INT_STATUS_ENABLE = 0x28,
35 INT_SIGNAL_ENABLE = 0x2c,
36 TIMER = 0x30,
37 TIMER_CONTROL = 0x34,
38 PAD_OUTPUT_ENABLE = 0x38,
39 PAD_PU_PD = 0x3c,
40 CLOCK_DELAY = 0x40,
41 ADMA_ADDRESS = 0x44,
42 CLOCK_CONTROL = 0x48,
43 LED_CONTROL = 0x4c,
44 VERSION = 0x50
45 };
46
47 struct jmb38x_ms_host {
48 struct jmb38x_ms *chip;
49 void __iomem *addr;
50 spinlock_t lock;
51 struct tasklet_struct notify;
52 int id;
53 char host_id[32];
54 int irq;
55 unsigned int block_pos;
56 unsigned long timeout_jiffies;
57 struct timer_list timer;
58 struct memstick_host *msh;
59 struct memstick_request *req;
60 unsigned char cmd_flags;
61 unsigned char io_pos;
62 unsigned char ifmode;
63 unsigned int io_word[2];
64 };
65
66 struct jmb38x_ms {
67 struct pci_dev *pdev;
68 int host_cnt;
69 struct memstick_host *hosts[] __counted_by(host_cnt);
70 };
71
72 #define BLOCK_COUNT_MASK 0xffff0000
73 #define BLOCK_SIZE_MASK 0x00000fff
74
75 #define DMA_CONTROL_ENABLE 0x00000001
76
77 #define TPC_DATA_SEL 0x00008000
78 #define TPC_DIR 0x00004000
79 #define TPC_WAIT_INT 0x00002000
80 #define TPC_GET_INT 0x00000800
81 #define TPC_CODE_SZ_MASK 0x00000700
82 #define TPC_DATA_SZ_MASK 0x00000007
83
84 #define HOST_CONTROL_TDELAY_EN 0x00040000
85 #define HOST_CONTROL_HW_OC_P 0x00010000
86 #define HOST_CONTROL_RESET_REQ 0x00008000
87 #define HOST_CONTROL_REI 0x00004000
88 #define HOST_CONTROL_LED 0x00000400
89 #define HOST_CONTROL_FAST_CLK 0x00000200
90 #define HOST_CONTROL_RESET 0x00000100
91 #define HOST_CONTROL_POWER_EN 0x00000080
92 #define HOST_CONTROL_CLOCK_EN 0x00000040
93 #define HOST_CONTROL_REO 0x00000008
94 #define HOST_CONTROL_IF_SHIFT 4
95
96 #define HOST_CONTROL_IF_SERIAL 0x0
97 #define HOST_CONTROL_IF_PAR4 0x1
98 #define HOST_CONTROL_IF_PAR8 0x3
99
100 #define STATUS_BUSY 0x00080000
101 #define STATUS_MS_DAT7 0x00040000
102 #define STATUS_MS_DAT6 0x00020000
103 #define STATUS_MS_DAT5 0x00010000
104 #define STATUS_MS_DAT4 0x00008000
105 #define STATUS_MS_DAT3 0x00004000
106 #define STATUS_MS_DAT2 0x00002000
107 #define STATUS_MS_DAT1 0x00001000
108 #define STATUS_MS_DAT0 0x00000800
109 #define STATUS_HAS_MEDIA 0x00000400
110 #define STATUS_FIFO_EMPTY 0x00000200
111 #define STATUS_FIFO_FULL 0x00000100
112 #define STATUS_MS_CED 0x00000080
113 #define STATUS_MS_ERR 0x00000040
114 #define STATUS_MS_BRQ 0x00000020
115 #define STATUS_MS_CNK 0x00000001
116
117 #define INT_STATUS_TPC_ERR 0x00080000
118 #define INT_STATUS_CRC_ERR 0x00040000
119 #define INT_STATUS_TIMER_TO 0x00020000
120 #define INT_STATUS_HSK_TO 0x00010000
121 #define INT_STATUS_ANY_ERR 0x00008000
122 #define INT_STATUS_FIFO_WRDY 0x00000080
123 #define INT_STATUS_FIFO_RRDY 0x00000040
124 #define INT_STATUS_MEDIA_OUT 0x00000010
125 #define INT_STATUS_MEDIA_IN 0x00000008
126 #define INT_STATUS_DMA_BOUNDARY 0x00000004
127 #define INT_STATUS_EOTRAN 0x00000002
128 #define INT_STATUS_EOTPC 0x00000001
129
130 #define INT_STATUS_ALL 0x000f801f
131
132 #define PAD_OUTPUT_ENABLE_MS 0x0F3F
133
134 #define PAD_PU_PD_OFF 0x7FFF0000
135 #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
136 #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
137
138 #define CLOCK_CONTROL_BY_MMIO 0x00000008
139 #define CLOCK_CONTROL_40MHZ 0x00000001
140 #define CLOCK_CONTROL_50MHZ 0x00000002
141 #define CLOCK_CONTROL_60MHZ 0x00000010
142 #define CLOCK_CONTROL_62_5MHZ 0x00000004
143 #define CLOCK_CONTROL_OFF 0x00000000
144
145 #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0
146
147 enum {
148 CMD_READY = 0x01,
149 FIFO_READY = 0x02,
150 REG_DATA = 0x04,
151 DMA_DATA = 0x08
152 };
153
jmb38x_ms_read_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)154 static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
155 unsigned char *buf, unsigned int length)
156 {
157 unsigned int off = 0;
158
159 while (host->io_pos && length) {
160 buf[off++] = host->io_word[0] & 0xff;
161 host->io_word[0] >>= 8;
162 length--;
163 host->io_pos--;
164 }
165
166 if (!length)
167 return off;
168
169 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
170 if (length < 4)
171 break;
172 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
173 length -= 4;
174 off += 4;
175 }
176
177 if (length
178 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
179 host->io_word[0] = readl(host->addr + DATA);
180 for (host->io_pos = 4; host->io_pos; --host->io_pos) {
181 buf[off++] = host->io_word[0] & 0xff;
182 host->io_word[0] >>= 8;
183 length--;
184 if (!length)
185 break;
186 }
187 }
188
189 return off;
190 }
191
jmb38x_ms_read_reg_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)192 static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
193 unsigned char *buf,
194 unsigned int length)
195 {
196 unsigned int off = 0;
197
198 while (host->io_pos > 4 && length) {
199 buf[off++] = host->io_word[0] & 0xff;
200 host->io_word[0] >>= 8;
201 length--;
202 host->io_pos--;
203 }
204
205 if (!length)
206 return off;
207
208 while (host->io_pos && length) {
209 buf[off++] = host->io_word[1] & 0xff;
210 host->io_word[1] >>= 8;
211 length--;
212 host->io_pos--;
213 }
214
215 return off;
216 }
217
jmb38x_ms_write_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)218 static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
219 unsigned char *buf,
220 unsigned int length)
221 {
222 unsigned int off = 0;
223
224 if (host->io_pos) {
225 while (host->io_pos < 4 && length) {
226 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
227 host->io_pos++;
228 length--;
229 }
230 }
231
232 if (host->io_pos == 4
233 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
234 writel(host->io_word[0], host->addr + DATA);
235 host->io_pos = 0;
236 host->io_word[0] = 0;
237 } else if (host->io_pos) {
238 return off;
239 }
240
241 if (!length)
242 return off;
243
244 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
245 if (length < 4)
246 break;
247
248 __raw_writel(*(unsigned int *)(buf + off),
249 host->addr + DATA);
250 length -= 4;
251 off += 4;
252 }
253
254 switch (length) {
255 case 3:
256 host->io_word[0] |= buf[off + 2] << 16;
257 host->io_pos++;
258 fallthrough;
259 case 2:
260 host->io_word[0] |= buf[off + 1] << 8;
261 host->io_pos++;
262 fallthrough;
263 case 1:
264 host->io_word[0] |= buf[off];
265 host->io_pos++;
266 }
267
268 off += host->io_pos;
269
270 return off;
271 }
272
jmb38x_ms_write_reg_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)273 static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
274 unsigned char *buf,
275 unsigned int length)
276 {
277 unsigned int off = 0;
278
279 while (host->io_pos < 4 && length) {
280 host->io_word[0] &= ~(0xff << (host->io_pos * 8));
281 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
282 host->io_pos++;
283 length--;
284 }
285
286 if (!length)
287 return off;
288
289 while (host->io_pos < 8 && length) {
290 host->io_word[1] &= ~(0xff << (host->io_pos * 8));
291 host->io_word[1] |= buf[off++] << (host->io_pos * 8);
292 host->io_pos++;
293 length--;
294 }
295
296 return off;
297 }
298
jmb38x_ms_transfer_data(struct jmb38x_ms_host * host)299 static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
300 {
301 unsigned int length;
302 unsigned int off;
303 unsigned int t_size, p_cnt;
304 unsigned char *buf;
305 struct page *pg;
306 unsigned long flags = 0;
307
308 if (host->req->long_data) {
309 length = host->req->sg.length - host->block_pos;
310 off = host->req->sg.offset + host->block_pos;
311 } else {
312 length = host->req->data_len - host->block_pos;
313 off = 0;
314 }
315
316 while (length) {
317 unsigned int p_off;
318
319 if (host->req->long_data) {
320 pg = sg_page(&host->req->sg) + (off >> PAGE_SHIFT);
321 p_off = offset_in_page(off);
322 p_cnt = PAGE_SIZE - p_off;
323 p_cnt = min(p_cnt, length);
324
325 local_irq_save(flags);
326 buf = kmap_atomic(pg) + p_off;
327 } else {
328 buf = host->req->data + host->block_pos;
329 p_cnt = host->req->data_len - host->block_pos;
330 }
331
332 if (host->req->data_dir == WRITE)
333 t_size = !(host->cmd_flags & REG_DATA)
334 ? jmb38x_ms_write_data(host, buf, p_cnt)
335 : jmb38x_ms_write_reg_data(host, buf, p_cnt);
336 else
337 t_size = !(host->cmd_flags & REG_DATA)
338 ? jmb38x_ms_read_data(host, buf, p_cnt)
339 : jmb38x_ms_read_reg_data(host, buf, p_cnt);
340
341 if (host->req->long_data) {
342 kunmap_atomic(buf - p_off);
343 local_irq_restore(flags);
344 }
345
346 if (!t_size)
347 break;
348 host->block_pos += t_size;
349 length -= t_size;
350 off += t_size;
351 }
352
353 if (!length && host->req->data_dir == WRITE) {
354 if (host->cmd_flags & REG_DATA) {
355 writel(host->io_word[0], host->addr + TPC_P0);
356 writel(host->io_word[1], host->addr + TPC_P1);
357 } else if (host->io_pos) {
358 writel(host->io_word[0], host->addr + DATA);
359 }
360 }
361
362 return length;
363 }
364
jmb38x_ms_issue_cmd(struct memstick_host * msh)365 static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
366 {
367 struct jmb38x_ms_host *host = memstick_priv(msh);
368 unsigned int data_len, cmd, t_val;
369
370 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
371 dev_dbg(&msh->dev, "no media status\n");
372 host->req->error = -ETIME;
373 return host->req->error;
374 }
375
376 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL));
377 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
378 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
379
380 host->cmd_flags = 0;
381 host->block_pos = 0;
382 host->io_pos = 0;
383 host->io_word[0] = 0;
384 host->io_word[1] = 0;
385
386 cmd = host->req->tpc << 16;
387 cmd |= TPC_DATA_SEL;
388
389 if (host->req->data_dir == READ)
390 cmd |= TPC_DIR;
391
392 if (host->req->need_card_int) {
393 if (host->ifmode == MEMSTICK_SERIAL)
394 cmd |= TPC_GET_INT;
395 else
396 cmd |= TPC_WAIT_INT;
397 }
398
399 if (!no_dma)
400 host->cmd_flags |= DMA_DATA;
401
402 if (host->req->long_data) {
403 data_len = host->req->sg.length;
404 } else {
405 data_len = host->req->data_len;
406 host->cmd_flags &= ~DMA_DATA;
407 }
408
409 if (data_len <= 8) {
410 cmd &= ~(TPC_DATA_SEL | 0xf);
411 host->cmd_flags |= REG_DATA;
412 cmd |= data_len & 0xf;
413 host->cmd_flags &= ~DMA_DATA;
414 }
415
416 if (host->cmd_flags & DMA_DATA) {
417 if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1,
418 host->req->data_dir == READ
419 ? DMA_FROM_DEVICE
420 : DMA_TO_DEVICE)) {
421 host->req->error = -ENOMEM;
422 return host->req->error;
423 }
424 data_len = sg_dma_len(&host->req->sg);
425 writel(sg_dma_address(&host->req->sg),
426 host->addr + DMA_ADDRESS);
427 writel(((1 << 16) & BLOCK_COUNT_MASK)
428 | (data_len & BLOCK_SIZE_MASK),
429 host->addr + BLOCK);
430 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
431 } else if (!(host->cmd_flags & REG_DATA)) {
432 writel(((1 << 16) & BLOCK_COUNT_MASK)
433 | (data_len & BLOCK_SIZE_MASK),
434 host->addr + BLOCK);
435 t_val = readl(host->addr + INT_STATUS_ENABLE);
436 t_val |= host->req->data_dir == READ
437 ? INT_STATUS_FIFO_RRDY
438 : INT_STATUS_FIFO_WRDY;
439
440 writel(t_val, host->addr + INT_STATUS_ENABLE);
441 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
442 } else {
443 cmd &= ~(TPC_DATA_SEL | 0xf);
444 host->cmd_flags |= REG_DATA;
445 cmd |= data_len & 0xf;
446
447 if (host->req->data_dir == WRITE) {
448 jmb38x_ms_transfer_data(host);
449 writel(host->io_word[0], host->addr + TPC_P0);
450 writel(host->io_word[1], host->addr + TPC_P1);
451 }
452 }
453
454 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
455 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
456 host->addr + HOST_CONTROL);
457 host->req->error = 0;
458
459 writel(cmd, host->addr + TPC);
460 dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
461
462 return 0;
463 }
464
jmb38x_ms_complete_cmd(struct memstick_host * msh,int last)465 static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
466 {
467 struct jmb38x_ms_host *host = memstick_priv(msh);
468 unsigned int t_val = 0;
469 int rc;
470
471 timer_delete(&host->timer);
472
473 dev_dbg(&msh->dev, "c control %08x\n",
474 readl(host->addr + HOST_CONTROL));
475 dev_dbg(&msh->dev, "c status %08x\n",
476 readl(host->addr + INT_STATUS));
477 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
478
479 host->req->int_reg = readl(host->addr + STATUS) & 0xff;
480
481 writel(0, host->addr + BLOCK);
482 writel(0, host->addr + DMA_CONTROL);
483
484 if (host->cmd_flags & DMA_DATA) {
485 dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1,
486 host->req->data_dir == READ
487 ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
488 } else {
489 t_val = readl(host->addr + INT_STATUS_ENABLE);
490 if (host->req->data_dir == READ)
491 t_val &= ~INT_STATUS_FIFO_RRDY;
492 else
493 t_val &= ~INT_STATUS_FIFO_WRDY;
494
495 writel(t_val, host->addr + INT_STATUS_ENABLE);
496 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
497 }
498
499 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
500 host->addr + HOST_CONTROL);
501
502 if (!last) {
503 do {
504 rc = memstick_next_req(msh, &host->req);
505 } while (!rc && jmb38x_ms_issue_cmd(msh));
506 } else {
507 do {
508 rc = memstick_next_req(msh, &host->req);
509 if (!rc)
510 host->req->error = -ETIME;
511 } while (!rc);
512 }
513 }
514
jmb38x_ms_isr(int irq,void * dev_id)515 static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
516 {
517 struct memstick_host *msh = dev_id;
518 struct jmb38x_ms_host *host = memstick_priv(msh);
519 unsigned int irq_status;
520
521 spin_lock(&host->lock);
522 irq_status = readl(host->addr + INT_STATUS);
523 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
524 if (irq_status == 0 || irq_status == (~0)) {
525 spin_unlock(&host->lock);
526 return IRQ_NONE;
527 }
528
529 if (host->req) {
530 if (irq_status & INT_STATUS_ANY_ERR) {
531 if (irq_status & INT_STATUS_CRC_ERR)
532 host->req->error = -EILSEQ;
533 else if (irq_status & INT_STATUS_TPC_ERR) {
534 dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
535 jmb38x_ms_complete_cmd(msh, 0);
536 } else
537 host->req->error = -ETIME;
538 } else {
539 if (host->cmd_flags & DMA_DATA) {
540 if (irq_status & INT_STATUS_EOTRAN)
541 host->cmd_flags |= FIFO_READY;
542 } else {
543 if (irq_status & (INT_STATUS_FIFO_RRDY
544 | INT_STATUS_FIFO_WRDY))
545 jmb38x_ms_transfer_data(host);
546
547 if (irq_status & INT_STATUS_EOTRAN) {
548 jmb38x_ms_transfer_data(host);
549 host->cmd_flags |= FIFO_READY;
550 }
551 }
552
553 if (irq_status & INT_STATUS_EOTPC) {
554 host->cmd_flags |= CMD_READY;
555 if (host->cmd_flags & REG_DATA) {
556 if (host->req->data_dir == READ) {
557 host->io_word[0]
558 = readl(host->addr
559 + TPC_P0);
560 host->io_word[1]
561 = readl(host->addr
562 + TPC_P1);
563 host->io_pos = 8;
564
565 jmb38x_ms_transfer_data(host);
566 }
567 host->cmd_flags |= FIFO_READY;
568 }
569 }
570 }
571 }
572
573 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
574 dev_dbg(&host->chip->pdev->dev, "media changed\n");
575 memstick_detect_change(msh);
576 }
577
578 writel(irq_status, host->addr + INT_STATUS);
579
580 if (host->req
581 && (((host->cmd_flags & CMD_READY)
582 && (host->cmd_flags & FIFO_READY))
583 || host->req->error))
584 jmb38x_ms_complete_cmd(msh, 0);
585
586 spin_unlock(&host->lock);
587 return IRQ_HANDLED;
588 }
589
jmb38x_ms_abort(struct timer_list * t)590 static void jmb38x_ms_abort(struct timer_list *t)
591 {
592 struct jmb38x_ms_host *host = timer_container_of(host, t, timer);
593 struct memstick_host *msh = host->msh;
594 unsigned long flags;
595
596 dev_dbg(&host->chip->pdev->dev, "abort\n");
597 spin_lock_irqsave(&host->lock, flags);
598 if (host->req) {
599 host->req->error = -ETIME;
600 jmb38x_ms_complete_cmd(msh, 0);
601 }
602 spin_unlock_irqrestore(&host->lock, flags);
603 }
604
jmb38x_ms_req_tasklet(unsigned long data)605 static void jmb38x_ms_req_tasklet(unsigned long data)
606 {
607 struct memstick_host *msh = (struct memstick_host *)data;
608 struct jmb38x_ms_host *host = memstick_priv(msh);
609 unsigned long flags;
610 int rc;
611
612 spin_lock_irqsave(&host->lock, flags);
613 if (!host->req) {
614 do {
615 rc = memstick_next_req(msh, &host->req);
616 dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc);
617 } while (!rc && jmb38x_ms_issue_cmd(msh));
618 }
619 spin_unlock_irqrestore(&host->lock, flags);
620 }
621
jmb38x_ms_dummy_submit(struct memstick_host * msh)622 static void jmb38x_ms_dummy_submit(struct memstick_host *msh)
623 {
624 return;
625 }
626
jmb38x_ms_submit_req(struct memstick_host * msh)627 static void jmb38x_ms_submit_req(struct memstick_host *msh)
628 {
629 struct jmb38x_ms_host *host = memstick_priv(msh);
630
631 tasklet_schedule(&host->notify);
632 }
633
jmb38x_ms_reset(struct jmb38x_ms_host * host)634 static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
635 {
636 int cnt;
637
638 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
639 | readl(host->addr + HOST_CONTROL),
640 host->addr + HOST_CONTROL);
641
642 for (cnt = 0; cnt < 20; ++cnt) {
643 if (!(HOST_CONTROL_RESET_REQ
644 & readl(host->addr + HOST_CONTROL)))
645 goto reset_next;
646
647 ndelay(20);
648 }
649 dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
650
651 reset_next:
652 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
653 | readl(host->addr + HOST_CONTROL),
654 host->addr + HOST_CONTROL);
655
656 for (cnt = 0; cnt < 20; ++cnt) {
657 if (!(HOST_CONTROL_RESET
658 & readl(host->addr + HOST_CONTROL)))
659 goto reset_ok;
660
661 ndelay(20);
662 }
663 dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
664 return -EIO;
665
666 reset_ok:
667 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
668 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
669 return 0;
670 }
671
jmb38x_ms_set_param(struct memstick_host * msh,enum memstick_param param,int value)672 static int jmb38x_ms_set_param(struct memstick_host *msh,
673 enum memstick_param param,
674 int value)
675 {
676 struct jmb38x_ms_host *host = memstick_priv(msh);
677 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
678 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0;
679 int rc = 0;
680
681 switch (param) {
682 case MEMSTICK_POWER:
683 if (value == MEMSTICK_POWER_ON) {
684 rc = jmb38x_ms_reset(host);
685 if (rc)
686 return rc;
687
688 host_ctl = 7;
689 host_ctl |= HOST_CONTROL_POWER_EN
690 | HOST_CONTROL_CLOCK_EN;
691 writel(host_ctl, host->addr + HOST_CONTROL);
692
693 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
694 : PAD_PU_PD_ON_MS_SOCK0,
695 host->addr + PAD_PU_PD);
696
697 writel(PAD_OUTPUT_ENABLE_MS,
698 host->addr + PAD_OUTPUT_ENABLE);
699
700 msleep(10);
701 dev_dbg(&host->chip->pdev->dev, "power on\n");
702 } else if (value == MEMSTICK_POWER_OFF) {
703 host_ctl &= ~(HOST_CONTROL_POWER_EN
704 | HOST_CONTROL_CLOCK_EN);
705 writel(host_ctl, host->addr + HOST_CONTROL);
706 writel(0, host->addr + PAD_OUTPUT_ENABLE);
707 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
708 dev_dbg(&host->chip->pdev->dev, "power off\n");
709 } else
710 return -EINVAL;
711 break;
712 case MEMSTICK_INTERFACE:
713 dev_dbg(&host->chip->pdev->dev,
714 "Set Host Interface Mode to %d\n", value);
715 host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI |
716 HOST_CONTROL_REO);
717 host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P;
718 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
719
720 if (value == MEMSTICK_SERIAL) {
721 host_ctl |= HOST_CONTROL_IF_SERIAL
722 << HOST_CONTROL_IF_SHIFT;
723 host_ctl |= HOST_CONTROL_REI;
724 clock_ctl |= CLOCK_CONTROL_40MHZ;
725 clock_delay = 0;
726 } else if (value == MEMSTICK_PAR4) {
727 host_ctl |= HOST_CONTROL_FAST_CLK;
728 host_ctl |= HOST_CONTROL_IF_PAR4
729 << HOST_CONTROL_IF_SHIFT;
730 host_ctl |= HOST_CONTROL_REO;
731 clock_ctl |= CLOCK_CONTROL_40MHZ;
732 clock_delay = 4;
733 } else if (value == MEMSTICK_PAR8) {
734 host_ctl |= HOST_CONTROL_FAST_CLK;
735 host_ctl |= HOST_CONTROL_IF_PAR8
736 << HOST_CONTROL_IF_SHIFT;
737 clock_ctl |= CLOCK_CONTROL_50MHZ;
738 clock_delay = 0;
739 } else
740 return -EINVAL;
741
742 writel(host_ctl, host->addr + HOST_CONTROL);
743 writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
744 writel(clock_ctl, host->addr + CLOCK_CONTROL);
745 pci_write_config_byte(host->chip->pdev,
746 PCI_CTL_CLOCK_DLY_ADDR + 1,
747 clock_delay);
748 host->ifmode = value;
749 break;
750 }
751 return 0;
752 }
753
754 #define PCI_PMOS0_CONTROL 0xae
755 #define PMOS0_ENABLE 0x01
756 #define PMOS0_OVERCURRENT_LEVEL_2_4V 0x06
757 #define PMOS0_EN_OVERCURRENT_DEBOUNCE 0x40
758 #define PMOS0_SW_LED_POLARITY_ENABLE 0x80
759 #define PMOS0_ACTIVE_BITS (PMOS0_ENABLE | PMOS0_EN_OVERCURRENT_DEBOUNCE | \
760 PMOS0_OVERCURRENT_LEVEL_2_4V)
761 #define PCI_PMOS1_CONTROL 0xbd
762 #define PMOS1_ACTIVE_BITS 0x4a
763 #define PCI_CLOCK_CTL 0xb9
764
jmb38x_ms_pmos(struct pci_dev * pdev,int flag)765 static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag)
766 {
767 unsigned char val;
768
769 pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val);
770 if (flag)
771 val |= PMOS0_ACTIVE_BITS;
772 else
773 val &= ~PMOS0_ACTIVE_BITS;
774 pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val);
775 dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val);
776
777 if (pci_resource_flags(pdev, 1)) {
778 pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val);
779 if (flag)
780 val |= PMOS1_ACTIVE_BITS;
781 else
782 val &= ~PMOS1_ACTIVE_BITS;
783 pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val);
784 dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val);
785 }
786
787 pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val);
788 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f);
789 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01);
790 dev_dbg(&pdev->dev, "Clock Control by PCI config is disabled!\n");
791
792 return 0;
793 }
794
jmb38x_ms_suspend(struct device * dev)795 static int __maybe_unused jmb38x_ms_suspend(struct device *dev)
796 {
797 struct jmb38x_ms *jm = dev_get_drvdata(dev);
798
799 int cnt;
800
801 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
802 if (!jm->hosts[cnt])
803 break;
804 memstick_suspend_host(jm->hosts[cnt]);
805 }
806
807 device_wakeup_disable(dev);
808
809 return 0;
810 }
811
jmb38x_ms_resume(struct device * dev)812 static int __maybe_unused jmb38x_ms_resume(struct device *dev)
813 {
814 struct jmb38x_ms *jm = dev_get_drvdata(dev);
815 int rc;
816
817 jmb38x_ms_pmos(to_pci_dev(dev), 1);
818
819 for (rc = 0; rc < jm->host_cnt; ++rc) {
820 if (!jm->hosts[rc])
821 break;
822 memstick_resume_host(jm->hosts[rc]);
823 memstick_detect_change(jm->hosts[rc]);
824 }
825
826 return 0;
827 }
828
jmb38x_ms_count_slots(struct pci_dev * pdev)829 static int jmb38x_ms_count_slots(struct pci_dev *pdev)
830 {
831 int cnt, rc = 0;
832
833 for (cnt = 0; cnt < PCI_STD_NUM_BARS; ++cnt) {
834 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
835 break;
836
837 if (256 != pci_resource_len(pdev, cnt))
838 break;
839
840 ++rc;
841 }
842 return rc;
843 }
844
jmb38x_ms_alloc_host(struct jmb38x_ms * jm,int cnt)845 static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
846 {
847 struct memstick_host *msh;
848 struct jmb38x_ms_host *host;
849
850 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
851 &jm->pdev->dev);
852 if (!msh)
853 return NULL;
854
855 host = memstick_priv(msh);
856 host->msh = msh;
857 host->chip = jm;
858 host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
859 pci_resource_len(jm->pdev, cnt));
860 if (!host->addr)
861 goto err_out_free;
862
863 spin_lock_init(&host->lock);
864 host->id = cnt;
865 snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d",
866 host->id);
867 host->irq = jm->pdev->irq;
868 host->timeout_jiffies = msecs_to_jiffies(1000);
869
870 tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh);
871 msh->request = jmb38x_ms_submit_req;
872 msh->set_param = jmb38x_ms_set_param;
873
874 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
875
876 timer_setup(&host->timer, jmb38x_ms_abort, 0);
877
878 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
879 msh))
880 return msh;
881
882 iounmap(host->addr);
883 err_out_free:
884 memstick_free_host(msh);
885 return NULL;
886 }
887
jmb38x_ms_free_host(struct memstick_host * msh)888 static void jmb38x_ms_free_host(struct memstick_host *msh)
889 {
890 struct jmb38x_ms_host *host = memstick_priv(msh);
891
892 free_irq(host->irq, msh);
893 iounmap(host->addr);
894 memstick_free_host(msh);
895 }
896
jmb38x_ms_probe(struct pci_dev * pdev,const struct pci_device_id * dev_id)897 static int jmb38x_ms_probe(struct pci_dev *pdev,
898 const struct pci_device_id *dev_id)
899 {
900 struct jmb38x_ms *jm;
901 int pci_dev_busy = 0;
902 int rc, cnt;
903
904 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
905 if (rc)
906 return rc;
907
908 rc = pci_enable_device(pdev);
909 if (rc)
910 return rc;
911
912 pci_set_master(pdev);
913
914 rc = pci_request_regions(pdev, DRIVER_NAME);
915 if (rc) {
916 pci_dev_busy = 1;
917 goto err_out;
918 }
919
920 jmb38x_ms_pmos(pdev, 1);
921
922 cnt = jmb38x_ms_count_slots(pdev);
923 if (!cnt) {
924 rc = -ENODEV;
925 pci_dev_busy = 1;
926 goto err_out_int;
927 }
928
929 jm = kzalloc(struct_size(jm, hosts, cnt), GFP_KERNEL);
930 if (!jm) {
931 rc = -ENOMEM;
932 goto err_out_int;
933 }
934
935 jm->pdev = pdev;
936 jm->host_cnt = cnt;
937 pci_set_drvdata(pdev, jm);
938
939 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
940 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
941 if (!jm->hosts[cnt])
942 break;
943
944 rc = memstick_add_host(jm->hosts[cnt]);
945
946 if (rc) {
947 jmb38x_ms_free_host(jm->hosts[cnt]);
948 jm->hosts[cnt] = NULL;
949 break;
950 }
951 }
952
953 if (cnt)
954 return 0;
955
956 rc = -ENODEV;
957
958 pci_set_drvdata(pdev, NULL);
959 kfree(jm);
960 err_out_int:
961 pci_release_regions(pdev);
962 err_out:
963 if (!pci_dev_busy)
964 pci_disable_device(pdev);
965 return rc;
966 }
967
jmb38x_ms_remove(struct pci_dev * dev)968 static void jmb38x_ms_remove(struct pci_dev *dev)
969 {
970 struct jmb38x_ms *jm = pci_get_drvdata(dev);
971 struct jmb38x_ms_host *host;
972 int cnt;
973 unsigned long flags;
974
975 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
976 if (!jm->hosts[cnt])
977 break;
978
979 host = memstick_priv(jm->hosts[cnt]);
980
981 jm->hosts[cnt]->request = jmb38x_ms_dummy_submit;
982 tasklet_kill(&host->notify);
983 writel(0, host->addr + INT_SIGNAL_ENABLE);
984 writel(0, host->addr + INT_STATUS_ENABLE);
985 dev_dbg(&jm->pdev->dev, "interrupts off\n");
986 spin_lock_irqsave(&host->lock, flags);
987 if (host->req) {
988 host->req->error = -ETIME;
989 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
990 }
991 spin_unlock_irqrestore(&host->lock, flags);
992
993 memstick_remove_host(jm->hosts[cnt]);
994 dev_dbg(&jm->pdev->dev, "host removed\n");
995
996 jmb38x_ms_free_host(jm->hosts[cnt]);
997 }
998
999 jmb38x_ms_pmos(dev, 0);
1000
1001 pci_set_drvdata(dev, NULL);
1002 pci_release_regions(dev);
1003 pci_disable_device(dev);
1004 kfree(jm);
1005 }
1006
1007 static struct pci_device_id jmb38x_ms_id_tbl [] = {
1008 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS) },
1009 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB385_MS) },
1010 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB390_MS) },
1011 { }
1012 };
1013
1014 static SIMPLE_DEV_PM_OPS(jmb38x_ms_pm_ops, jmb38x_ms_suspend, jmb38x_ms_resume);
1015
1016 static struct pci_driver jmb38x_ms_driver = {
1017 .name = DRIVER_NAME,
1018 .id_table = jmb38x_ms_id_tbl,
1019 .probe = jmb38x_ms_probe,
1020 .remove = jmb38x_ms_remove,
1021 .driver.pm = &jmb38x_ms_pm_ops,
1022 };
1023
1024 module_pci_driver(jmb38x_ms_driver);
1025
1026 MODULE_AUTHOR("Alex Dubov");
1027 MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
1028 MODULE_LICENSE("GPL");
1029 MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
1030