1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_MDSS_H 8 #define _DPU_HW_MDSS_H 9 10 #include <linux/kernel.h> 11 #include <linux/err.h> 12 13 #include "msm_drv.h" 14 15 #include "disp/mdp_format.h" 16 17 #define DPU_DBG_NAME "dpu" 18 19 #define DPU_NONE 0 20 21 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 22 #define DPU_CSC_MATRIX_COEFF_SIZE 9 23 #endif 24 25 #ifndef DPU_CSC_CLAMP_SIZE 26 #define DPU_CSC_CLAMP_SIZE 6 27 #endif 28 29 #ifndef DPU_CSC_BIAS_SIZE 30 #define DPU_CSC_BIAS_SIZE 3 31 #endif 32 33 #ifndef DPU_MAX_PLANES 34 #define DPU_MAX_PLANES 4 35 #endif 36 37 #define STAGES_PER_PLANE 2 38 #define PIPES_PER_STAGE 2 39 #define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) 40 #ifndef DPU_MAX_DE_CURVES 41 #define DPU_MAX_DE_CURVES 3 42 #endif 43 44 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 45 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 46 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 47 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 48 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 49 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 50 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 51 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 52 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 53 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 54 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 55 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 56 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 57 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 58 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 59 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 60 61 enum dpu_vsync_source { 62 DPU_VSYNC_SOURCE_GPIO_0, 63 DPU_VSYNC_SOURCE_GPIO_1, 64 DPU_VSYNC_SOURCE_GPIO_2, 65 DPU_VSYNC_SOURCE_INTF_0 = 3, 66 DPU_VSYNC_SOURCE_INTF_1, 67 DPU_VSYNC_SOURCE_INTF_2, 68 DPU_VSYNC_SOURCE_INTF_3, 69 DPU_VSYNC_SOURCE_WD_TIMER_4 = 11, 70 DPU_VSYNC_SOURCE_WD_TIMER_3, 71 DPU_VSYNC_SOURCE_WD_TIMER_2, 72 DPU_VSYNC_SOURCE_WD_TIMER_1, 73 DPU_VSYNC_SOURCE_WD_TIMER_0, 74 }; 75 76 enum dpu_hw_blk_type { 77 DPU_HW_BLK_TOP = 0, 78 DPU_HW_BLK_SSPP, 79 DPU_HW_BLK_LM, 80 DPU_HW_BLK_CTL, 81 DPU_HW_BLK_PINGPONG, 82 DPU_HW_BLK_DCWB_PINGPONG, 83 DPU_HW_BLK_INTF, 84 DPU_HW_BLK_WB, 85 DPU_HW_BLK_DSPP, 86 DPU_HW_BLK_MERGE_3D, 87 DPU_HW_BLK_DSC, 88 DPU_HW_BLK_CDM, 89 DPU_HW_BLK_CWB, 90 DPU_HW_BLK_MAX, 91 }; 92 93 enum dpu_sspp { 94 SSPP_NONE, 95 SSPP_VIG0, 96 SSPP_VIG1, 97 SSPP_VIG2, 98 SSPP_VIG3, 99 SSPP_RGB0, 100 SSPP_RGB1, 101 SSPP_RGB2, 102 SSPP_RGB3, 103 SSPP_DMA0, 104 SSPP_DMA1, 105 SSPP_DMA2, 106 SSPP_DMA3, 107 SSPP_DMA4, 108 SSPP_DMA5, 109 SSPP_CURSOR0, 110 SSPP_CURSOR1, 111 SSPP_MAX 112 }; 113 114 enum dpu_sspp_type { 115 SSPP_TYPE_VIG, 116 SSPP_TYPE_RGB, 117 SSPP_TYPE_DMA, 118 SSPP_TYPE_CURSOR, 119 SSPP_TYPE_MAX 120 }; 121 122 enum dpu_lm { 123 LM_0 = 1, 124 LM_1, 125 LM_2, 126 LM_3, 127 LM_4, 128 LM_5, 129 LM_6, 130 LM_7, 131 LM_MAX 132 }; 133 134 enum dpu_stage { 135 DPU_STAGE_BASE = 0, 136 DPU_STAGE_0, 137 DPU_STAGE_1, 138 DPU_STAGE_2, 139 DPU_STAGE_3, 140 DPU_STAGE_4, 141 DPU_STAGE_5, 142 DPU_STAGE_6, 143 DPU_STAGE_7, 144 DPU_STAGE_8, 145 DPU_STAGE_9, 146 DPU_STAGE_10, 147 DPU_STAGE_MAX 148 }; 149 enum dpu_dspp { 150 DSPP_0 = 1, 151 DSPP_1, 152 DSPP_2, 153 DSPP_3, 154 DSPP_4, 155 DSPP_5, 156 DSPP_6, 157 DSPP_7, 158 DSPP_MAX 159 }; 160 161 enum dpu_ctl { 162 CTL_0 = 1, 163 CTL_1, 164 CTL_2, 165 CTL_3, 166 CTL_4, 167 CTL_5, 168 CTL_6, 169 CTL_7, 170 CTL_MAX 171 }; 172 173 enum dpu_dsc { 174 DSC_NONE = 0, 175 DSC_0, 176 DSC_1, 177 DSC_2, 178 DSC_3, 179 DSC_4, 180 DSC_5, 181 DSC_6, 182 DSC_7, 183 DSC_MAX 184 }; 185 186 enum dpu_cdm { 187 CDM_0 = 1, 188 CDM_MAX 189 }; 190 191 enum dpu_pingpong { 192 PINGPONG_NONE, 193 PINGPONG_0, 194 PINGPONG_1, 195 PINGPONG_2, 196 PINGPONG_3, 197 PINGPONG_4, 198 PINGPONG_5, 199 PINGPONG_6, 200 PINGPONG_7, 201 PINGPONG_CWB_0, 202 PINGPONG_CWB_1, 203 PINGPONG_CWB_2, 204 PINGPONG_CWB_3, 205 PINGPONG_S0, 206 PINGPONG_MAX 207 }; 208 209 enum dpu_merge_3d { 210 MERGE_3D_0 = 1, 211 MERGE_3D_1, 212 MERGE_3D_2, 213 MERGE_3D_3, 214 MERGE_3D_4, 215 MERGE_3D_5, 216 MERGE_3D_MAX 217 }; 218 219 enum dpu_intf { 220 INTF_0 = 1, 221 INTF_1, 222 INTF_2, 223 INTF_3, 224 INTF_4, 225 INTF_5, 226 INTF_6, 227 INTF_7, 228 INTF_8, 229 INTF_MAX 230 }; 231 232 /* 233 * Historically these values correspond to the values written to the 234 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 235 * generations this register is NOP, but we keep the values for historical 236 * reasons. 237 */ 238 enum dpu_intf_type { 239 INTF_NONE = 0x0, 240 INTF_DSI = 0x1, 241 INTF_HDMI = 0x3, 242 INTF_LCDC = 0x5, 243 /* old eDP found on 8x74 and 8x84 */ 244 INTF_EDP = 0x9, 245 /* both DP and eDP, handled by the new DP driver */ 246 INTF_DP = 0xa, 247 248 /* virtual interfaces */ 249 INTF_WB = 0x100, 250 }; 251 252 enum dpu_intf_mode { 253 INTF_MODE_NONE = 0, 254 INTF_MODE_CMD, 255 INTF_MODE_VIDEO, 256 INTF_MODE_WB_BLOCK, 257 INTF_MODE_WB_LINE, 258 INTF_MODE_MAX 259 }; 260 261 enum dpu_wb { 262 WB_0 = 1, 263 WB_1, 264 WB_2, 265 WB_3, 266 WB_MAX 267 }; 268 269 enum dpu_cwb { 270 CWB_0 = 0x1, 271 CWB_1, 272 CWB_2, 273 CWB_3, 274 CWB_MAX 275 }; 276 277 enum dpu_wd_timer { 278 WD_TIMER_0 = 0x1, 279 WD_TIMER_1, 280 WD_TIMER_2, 281 WD_TIMER_3, 282 WD_TIMER_4, 283 WD_TIMER_5, 284 WD_TIMER_MAX 285 }; 286 287 enum dpu_vbif { 288 VBIF_RT, 289 VBIF_NRT, 290 VBIF_MAX, 291 }; 292 293 /** 294 * enum dpu_3d_blend_mode 295 * Desribes how the 3d data is blended 296 * @BLEND_3D_NONE : 3d blending not enabled 297 * @BLEND_3D_FRAME_INT : Frame interleaving 298 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 299 * @BLEND_3D_V_ROW_INT : vertical row interleaving 300 * @BLEND_3D_COL_INT : column interleaving 301 * @BLEND_3D_MAX : 302 */ 303 enum dpu_3d_blend_mode { 304 BLEND_3D_NONE = 0, 305 BLEND_3D_FRAME_INT, 306 BLEND_3D_H_ROW_INT, 307 BLEND_3D_V_ROW_INT, 308 BLEND_3D_COL_INT, 309 BLEND_3D_MAX 310 }; 311 312 /** 313 * struct dpu_hw_fmt_layout - format information of the source pixel data 314 * @num_planes: number of planes (including meta data planes) 315 * @width: image width 316 * @height: image height 317 * @total_size: total size in bytes 318 * @plane_addr: address of each plane 319 * @plane_size: length of each plane 320 * @plane_pitch: pitch of each plane 321 */ 322 struct dpu_hw_fmt_layout { 323 uint32_t num_planes; 324 uint32_t width; 325 uint32_t height; 326 uint32_t total_size; 327 uint32_t plane_addr[DPU_MAX_PLANES]; 328 uint32_t plane_size[DPU_MAX_PLANES]; 329 uint32_t plane_pitch[DPU_MAX_PLANES]; 330 }; 331 332 struct dpu_csc_cfg { 333 /* matrix coefficients in S15.16 format */ 334 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 335 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 336 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 337 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 338 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 339 }; 340 341 /** 342 * struct dpu_mdss_color - mdss color description 343 * color 0 : green 344 * color 1 : blue 345 * color 2 : red 346 * color 3 : alpha 347 */ 348 struct dpu_mdss_color { 349 u32 color_0; 350 u32 color_1; 351 u32 color_2; 352 u32 color_3; 353 }; 354 355 /* 356 * Define bit masks for h/w logging. 357 */ 358 #define DPU_DBG_MASK_NONE (1 << 0) 359 #define DPU_DBG_MASK_INTF (1 << 1) 360 #define DPU_DBG_MASK_LM (1 << 2) 361 #define DPU_DBG_MASK_CTL (1 << 3) 362 #define DPU_DBG_MASK_PINGPONG (1 << 4) 363 #define DPU_DBG_MASK_SSPP (1 << 5) 364 #define DPU_DBG_MASK_WB (1 << 6) 365 #define DPU_DBG_MASK_TOP (1 << 7) 366 #define DPU_DBG_MASK_VBIF (1 << 8) 367 #define DPU_DBG_MASK_ROT (1 << 9) 368 #define DPU_DBG_MASK_DSPP (1 << 10) 369 #define DPU_DBG_MASK_DSC (1 << 11) 370 #define DPU_DBG_MASK_CDM (1 << 12) 371 #define DPU_DBG_MASK_CWB (1 << 13) 372 373 /** 374 * struct dpu_hw_tear_check - Struct contains parameters to configure 375 * tear-effect module. This structure is used to configure tear-check 376 * logic present either in ping-pong or in interface module. 377 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 378 * by no of lines 379 * @sync_cfg_height: Total vertical lines (display height - 1) 380 * @vsync_init_val: Init value to which the read pointer gets loaded at 381 * vsync edge 382 * @sync_threshold_start: Read pointer threshold start ROI for write operation 383 * @sync_threshold_continue: The minimum number of lines the write pointer 384 * needs to be above the read pointer 385 * @start_pos: The position from which the start_threshold value is added 386 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 387 * @hw_vsync_mode: Sync with external frame sync input 388 */ 389 struct dpu_hw_tear_check { 390 /* 391 * This is ratio of MDP VSYNC clk freq(Hz) to 392 * refresh rate divided by no of lines 393 */ 394 u32 vsync_count; 395 u32 sync_cfg_height; 396 u32 vsync_init_val; 397 u32 sync_threshold_start; 398 u32 sync_threshold_continue; 399 u32 start_pos; 400 u32 rd_ptr_irq; 401 u8 hw_vsync_mode; 402 }; 403 404 /** 405 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 406 * read and write pointers for command mode panels 407 * @rd_ptr_init_val: Value of rd pointer at vsync edge 408 * @rd_ptr_frame_count: Num frames sent since enabling interface 409 * @rd_ptr_line_count: Current line on panel (rd ptr) 410 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 411 * @intf_frame_count: Frames read from intf 412 */ 413 struct dpu_hw_pp_vsync_info { 414 u32 rd_ptr_init_val; 415 u32 rd_ptr_frame_count; 416 u32 rd_ptr_line_count; 417 u32 wr_ptr_line_count; 418 u32 intf_frame_count; 419 }; 420 421 #endif /* _DPU_HW_MDSS_H */ 422