1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Hardware definitions for SSI. 3 * 4 * Copyright (C) 2010 Nokia Corporation. All rights reserved. 5 * 6 * Contact: Carlos Chinea <carlos.chinea@nokia.com> 7 */ 8 9 #ifndef __OMAP_SSI_REGS_H__ 10 #define __OMAP_SSI_REGS_H__ 11 12 /* 13 * SSI SYS registers 14 */ 15 #define SSI_REVISION_REG 0 16 # define SSI_REV_MAJOR 0xf0 17 # define SSI_REV_MINOR 0xf 18 #define SSI_SYSCONFIG_REG 0x10 19 # define SSI_AUTOIDLE (1 << 0) 20 # define SSI_SOFTRESET (1 << 1) 21 # define SSI_SIDLEMODE_FORCE 0 22 # define SSI_SIDLEMODE_NO (1 << 3) 23 # define SSI_SIDLEMODE_SMART (1 << 4) 24 # define SSI_SIDLEMODE_MASK 0x18 25 # define SSI_MIDLEMODE_FORCE 0 26 # define SSI_MIDLEMODE_NO (1 << 12) 27 # define SSI_MIDLEMODE_SMART (1 << 13) 28 # define SSI_MIDLEMODE_MASK 0x3000 29 #define SSI_SYSSTATUS_REG 0x14 30 # define SSI_RESETDONE 1 31 #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2)) 32 #define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8)) 33 # define SSI_DATAACCEPT(channel) (1 << (channel)) 34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) 35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) 36 # define SSI_ERROROCCURED (1 << 24) 37 # define SSI_BREAKDETECTED (1 << 25) 38 #define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800 39 #define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804 40 # define SSI_GDD_LCH(channel) (1 << (channel)) 41 #define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10)) 42 #define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10)) 43 #define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10)) 44 # define SSI_WAKE(channel) (1 << (channel)) 45 # define SSI_WAKE_MASK 0xff 46 47 /* 48 * SSI SST registers 49 */ 50 #define SSI_SST_ID_REG 0 51 #define SSI_SST_MODE_REG 4 52 # define SSI_MODE_VAL_MASK 3 53 # define SSI_MODE_SLEEP 0 54 # define SSI_MODE_STREAM 1 55 # define SSI_MODE_FRAME 2 56 # define SSI_MODE_MULTIPOINTS 3 57 #define SSI_SST_FRAMESIZE_REG 8 58 # define SSI_FRAMESIZE_DEFAULT 31 59 #define SSI_SST_TXSTATE_REG 0xc 60 # define SSI_TXSTATE_IDLE 0 61 #define SSI_SST_BUFSTATE_REG 0x10 62 # define SSI_FULL(channel) (1 << (channel)) 63 #define SSI_SST_DIVISOR_REG 0x18 64 # define SSI_MAX_DIVISOR 127 65 #define SSI_SST_BREAK_REG 0x20 66 #define SSI_SST_CHANNELS_REG 0x24 67 # define SSI_CHANNELS_DEFAULT 4 68 #define SSI_SST_ARBMODE_REG 0x28 69 # define SSI_ARBMODE_ROUNDROBIN 0 70 # define SSI_ARBMODE_PRIORITY 1 71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) 72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) 73 74 /* 75 * SSI SSR registers 76 */ 77 #define SSI_SSR_ID_REG 0 78 #define SSI_SSR_MODE_REG 4 79 #define SSI_SSR_FRAMESIZE_REG 8 80 #define SSI_SSR_RXSTATE_REG 0xc 81 #define SSI_SSR_BUFSTATE_REG 0x10 82 # define SSI_NOTEMPTY(channel) (1 << (channel)) 83 #define SSI_SSR_BREAK_REG 0x1c 84 #define SSI_SSR_ERROR_REG 0x20 85 #define SSI_SSR_ERRORACK_REG 0x24 86 #define SSI_SSR_OVERRUN_REG 0x2c 87 #define SSI_SSR_OVERRUNACK_REG 0x30 88 #define SSI_SSR_TIMEOUT_REG 0x34 89 # define SSI_TIMEOUT_DEFAULT 0 90 #define SSI_SSR_CHANNELS_REG 0x28 91 #define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) 92 #define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) 93 94 /* 95 * SSI GDD registers 96 */ 97 #define SSI_GDD_HW_ID_REG 0 98 #define SSI_GDD_PPORT_ID_REG 0x10 99 #define SSI_GDD_MPORT_ID_REG 0x14 100 #define SSI_GDD_PPORT_SR_REG 0x20 101 #define SSI_GDD_MPORT_SR_REG 0x24 102 # define SSI_ACTIVE_LCH_NUM_MASK 0xff 103 #define SSI_GDD_TEST_REG 0x40 104 # define SSI_TEST 1 105 #define SSI_GDD_GCR_REG 0x100 106 # define SSI_CLK_AUTOGATING_ON (1 << 3) 107 # define SSI_FREE (1 << 2) 108 # define SSI_SWITCH_OFF (1 << 0) 109 #define SSI_GDD_GRST_REG 0x200 110 # define SSI_SWRESET 1 111 #define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40)) 112 # define SSI_DST_BURST_EN_MASK 0xc000 113 # define SSI_DST_SINGLE_ACCESS0 0 114 # define SSI_DST_SINGLE_ACCESS (1 << 14) 115 # define SSI_DST_BURST_4x32_BIT (2 << 14) 116 # define SSI_DST_BURST_8x32_BIT (3 << 14) 117 # define SSI_DST_MASK 0x1e00 118 # define SSI_DST_MEMORY_PORT (8 << 9) 119 # define SSI_DST_PERIPHERAL_PORT (9 << 9) 120 # define SSI_SRC_BURST_EN_MASK 0x180 121 # define SSI_SRC_SINGLE_ACCESS0 0 122 # define SSI_SRC_SINGLE_ACCESS (1 << 7) 123 # define SSI_SRC_BURST_4x32_BIT (2 << 7) 124 # define SSI_SRC_BURST_8x32_BIT (3 << 7) 125 # define SSI_SRC_MASK 0x3c 126 # define SSI_SRC_MEMORY_PORT (8 << 2) 127 # define SSI_SRC_PERIPHERAL_PORT (9 << 2) 128 # define SSI_DATA_TYPE_MASK 3 129 # define SSI_DATA_TYPE_S32 2 130 #define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40)) 131 # define SSI_DST_AMODE_MASK (3 << 14) 132 # define SSI_DST_AMODE_CONST 0 133 # define SSI_DST_AMODE_POSTINC (1 << 12) 134 # define SSI_SRC_AMODE_MASK (3 << 12) 135 # define SSI_SRC_AMODE_CONST 0 136 # define SSI_SRC_AMODE_POSTINC (1 << 12) 137 # define SSI_CCR_ENABLE (1 << 7) 138 # define SSI_CCR_SYNC_MASK 0x1f 139 #define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40)) 140 # define SSI_BLOCK_IE (1 << 5) 141 # define SSI_HALF_IE (1 << 2) 142 # define SSI_TOUT_IE (1 << 0) 143 #define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40)) 144 # define SSI_CSR_SYNC (1 << 6) 145 # define SSI_CSR_BLOCK (1 << 5) 146 # define SSI_CSR_HALF (1 << 2) 147 # define SSI_CSR_TOUR (1 << 0) 148 #define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40)) 149 #define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40)) 150 #define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40)) 151 #define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40)) 152 #define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40)) 153 #define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40)) 154 # define SSI_ENABLE_LNK (1 << 15) 155 # define SSI_STOP_LNK (1 << 14) 156 # define SSI_NEXT_CH_ID_MASK 0xf 157 158 #endif /* __OMAP_SSI_REGS_H__ */ 159