1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/soc.h> 17 18 /* REGISTER OFFSET */ 19 #define SSICR 0x000 20 #define SSISR 0x004 21 #define SSIFCR 0x010 22 #define SSIFSR 0x014 23 #define SSIFTDR 0x018 24 #define SSIFRDR 0x01c 25 #define SSIOFR 0x020 26 #define SSISCR 0x024 27 28 /* SSI REGISTER BITS */ 29 #define SSICR_DWL(x) (((x) & 0x7) << 19) 30 #define SSICR_SWL(x) (((x) & 0x7) << 16) 31 32 #define SSICR_CKS BIT(30) 33 #define SSICR_TUIEN BIT(29) 34 #define SSICR_TOIEN BIT(28) 35 #define SSICR_RUIEN BIT(27) 36 #define SSICR_ROIEN BIT(26) 37 #define SSICR_MST BIT(14) 38 #define SSICR_BCKP BIT(13) 39 #define SSICR_LRCKP BIT(12) 40 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 41 #define SSICR_TEN BIT(1) 42 #define SSICR_REN BIT(0) 43 44 #define SSISR_TUIRQ BIT(29) 45 #define SSISR_TOIRQ BIT(28) 46 #define SSISR_RUIRQ BIT(27) 47 #define SSISR_ROIRQ BIT(26) 48 #define SSISR_IIRQ BIT(25) 49 50 #define SSIFCR_AUCKE BIT(31) 51 #define SSIFCR_SSIRST BIT(16) 52 #define SSIFCR_TIE BIT(3) 53 #define SSIFCR_RIE BIT(2) 54 #define SSIFCR_TFRST BIT(1) 55 #define SSIFCR_RFRST BIT(0) 56 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 57 58 #define SSIFSR_TDC_MASK 0x3f 59 #define SSIFSR_TDC_SHIFT 24 60 #define SSIFSR_RDC_MASK 0x3f 61 #define SSIFSR_RDC_SHIFT 8 62 63 #define SSIFSR_TDE BIT(16) 64 #define SSIFSR_RDF BIT(0) 65 66 #define SSIOFR_LRCONT BIT(8) 67 68 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 69 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 70 71 /* Pre allocated buffers sizes */ 72 #define PREALLOC_BUFFER (SZ_32K) 73 #define PREALLOC_BUFFER_MAX (SZ_32K) 74 75 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 76 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 77 #define SSI_CHAN_MIN 2 78 #define SSI_CHAN_MAX 2 79 #define SSI_FIFO_DEPTH 32 80 81 struct rz_ssi_priv; 82 83 struct rz_ssi_stream { 84 struct rz_ssi_priv *priv; 85 struct snd_pcm_substream *substream; 86 int fifo_sample_size; /* sample capacity of SSI FIFO */ 87 int dma_buffer_pos; /* The address for the next DMA descriptor */ 88 int period_counter; /* for keeping track of periods transferred */ 89 int sample_width; 90 int buffer_pos; /* current frame position in the buffer */ 91 int running; /* 0=stopped, 1=running */ 92 93 int uerr_num; 94 int oerr_num; 95 96 struct dma_chan *dma_ch; 97 98 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 99 }; 100 101 struct rz_ssi_priv { 102 void __iomem *base; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 /* Full duplex communication support */ 136 struct { 137 unsigned int rate; 138 unsigned int channels; 139 unsigned int sample_width; 140 unsigned int sample_bits; 141 } hw_params_cache; 142 }; 143 144 static void rz_ssi_dma_complete(void *data); 145 146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 147 { 148 writel(data, (priv->base + reg)); 149 } 150 151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 152 { 153 return readl(priv->base + reg); 154 } 155 156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 157 u32 bclr, u32 bset) 158 { 159 u32 val; 160 161 val = readl(priv->base + reg); 162 val = (val & ~bclr) | bset; 163 writel(val, (priv->base + reg)); 164 } 165 166 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream) 167 { 168 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 169 } 170 171 static inline struct rz_ssi_stream * 172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 173 { 174 struct rz_ssi_stream *stream = &ssi->playback; 175 176 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 177 stream = &ssi->capture; 178 179 return stream; 180 } 181 182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 183 { 184 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 185 } 186 187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 188 struct snd_pcm_substream *substream) 189 { 190 struct rz_ssi_priv *ssi = strm->priv; 191 192 guard(spinlock_irqsave)(&ssi->lock); 193 194 strm->substream = substream; 195 } 196 197 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 198 struct rz_ssi_stream *strm) 199 { 200 guard(spinlock_irqsave)(&ssi->lock); 201 202 return strm->substream && strm->substream->runtime; 203 } 204 205 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 206 { 207 return strm->substream && strm->running; 208 } 209 210 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 211 struct snd_pcm_substream *substream) 212 { 213 struct snd_pcm_runtime *runtime = substream->runtime; 214 215 rz_ssi_set_substream(strm, substream); 216 strm->sample_width = samples_to_bytes(runtime, 1); 217 strm->dma_buffer_pos = 0; 218 strm->period_counter = 0; 219 strm->buffer_pos = 0; 220 221 strm->oerr_num = 0; 222 strm->uerr_num = 0; 223 strm->running = 0; 224 225 /* fifo init */ 226 strm->fifo_sample_size = SSI_FIFO_DEPTH; 227 } 228 229 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 230 struct rz_ssi_stream *strm) 231 { 232 struct device *dev = ssi->dev; 233 234 rz_ssi_set_substream(strm, NULL); 235 236 if (strm->oerr_num > 0) 237 dev_info(dev, "overrun = %d\n", strm->oerr_num); 238 239 if (strm->uerr_num > 0) 240 dev_info(dev, "underrun = %d\n", strm->uerr_num); 241 } 242 243 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 244 unsigned int channels) 245 { 246 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 247 unsigned int channel_bits = 32; /* System Word Length */ 248 unsigned long bclk_rate = rate * channels * channel_bits; 249 unsigned int div; 250 unsigned int i; 251 u32 ssicr = 0; 252 u32 clk_ckdv; 253 254 /* Clear AUCKE so we can set MST */ 255 rz_ssi_reg_writel(ssi, SSIFCR, 0); 256 257 /* Continue to output LRCK pin even when idle */ 258 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 259 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 260 if (ssi->audio_clk_1 % bclk_rate) 261 ssi->audio_mck = ssi->audio_clk_2; 262 else 263 ssi->audio_mck = ssi->audio_clk_1; 264 } 265 266 /* Clock setting */ 267 ssicr |= SSICR_MST; 268 if (ssi->audio_mck == ssi->audio_clk_1) 269 ssicr |= SSICR_CKS; 270 if (ssi->bckp_rise) 271 ssicr |= SSICR_BCKP; 272 if (ssi->lrckp_fsync_fall) 273 ssicr |= SSICR_LRCKP; 274 275 /* Determine the clock divider */ 276 clk_ckdv = 0; 277 div = ssi->audio_mck / bclk_rate; 278 /* try to find an match */ 279 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 280 if (ckdv[i] == div) { 281 clk_ckdv = i; 282 break; 283 } 284 } 285 286 if (i == ARRAY_SIZE(ckdv)) { 287 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 288 return -EINVAL; 289 } 290 291 /* 292 * DWL: Data Word Length = 16 bits 293 * SWL: System Word Length = 32 bits 294 */ 295 ssicr |= SSICR_CKDV(clk_ckdv); 296 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 297 rz_ssi_reg_writel(ssi, SSICR, ssicr); 298 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 299 300 return 0; 301 } 302 303 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 304 { 305 u32 tmp; 306 int ret; 307 308 /* Disable irqs */ 309 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 310 SSICR_RUIEN | SSICR_ROIEN, 0); 311 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 312 313 /* Clear all error flags */ 314 rz_ssi_reg_mask_setl(ssi, SSISR, 315 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 316 SSISR_RUIRQ), 0); 317 318 /* Wait for idle */ 319 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100); 320 if (ret) 321 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n"); 322 323 /* Hold FIFOs in reset */ 324 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 325 } 326 327 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 328 { 329 bool is_play = rz_ssi_stream_is_play(strm->substream); 330 bool is_full_duplex; 331 u32 ssicr, ssifcr; 332 333 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 334 rz_ssi_is_stream_running(&ssi->capture); 335 ssicr = rz_ssi_reg_readl(ssi, SSICR); 336 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 337 if (!is_full_duplex) { 338 ssifcr &= ~0xF; 339 } else { 340 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 341 rz_ssi_set_idle(ssi); 342 ssifcr &= ~SSIFCR_FIFO_RST; 343 } 344 345 /* FIFO interrupt thresholds */ 346 if (rz_ssi_is_dma_enabled(ssi)) 347 rz_ssi_reg_writel(ssi, SSISCR, 0); 348 else 349 rz_ssi_reg_writel(ssi, SSISCR, 350 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 351 SSISCR_RDFS(0)); 352 353 /* enable IRQ */ 354 if (is_play) { 355 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 356 ssifcr |= SSIFCR_TIE; 357 if (!is_full_duplex) 358 ssifcr |= SSIFCR_RFRST; 359 } else { 360 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 361 ssifcr |= SSIFCR_RIE; 362 if (!is_full_duplex) 363 ssifcr |= SSIFCR_TFRST; 364 } 365 366 rz_ssi_reg_writel(ssi, SSICR, ssicr); 367 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 368 369 /* Clear all error flags */ 370 rz_ssi_reg_mask_setl(ssi, SSISR, 371 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 372 SSISR_RUIRQ), 0); 373 374 strm->running = 1; 375 if (is_full_duplex) 376 ssicr |= SSICR_TEN | SSICR_REN; 377 else 378 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 379 380 rz_ssi_reg_writel(ssi, SSICR, ssicr); 381 382 return 0; 383 } 384 385 static int rz_ssi_swreset(struct rz_ssi_priv *ssi) 386 { 387 u32 tmp; 388 389 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 390 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 391 return readl_poll_timeout_atomic(ssi->base + SSIFCR, tmp, !(tmp & SSIFCR_SSIRST), 1, 5); 392 } 393 394 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 395 { 396 strm->running = 0; 397 398 if (rz_ssi_is_stream_running(&ssi->playback) || 399 rz_ssi_is_stream_running(&ssi->capture)) 400 return 0; 401 402 /* Disable TX/RX */ 403 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 404 405 /* Cancel all remaining DMA transactions */ 406 if (rz_ssi_is_dma_enabled(ssi)) { 407 if (ssi->playback.dma_ch) 408 dmaengine_terminate_async(ssi->playback.dma_ch); 409 if (ssi->capture.dma_ch) 410 dmaengine_terminate_async(ssi->capture.dma_ch); 411 } 412 413 rz_ssi_set_idle(ssi); 414 415 return 0; 416 } 417 418 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 419 { 420 struct snd_pcm_substream *substream = strm->substream; 421 struct snd_pcm_runtime *runtime; 422 int current_period; 423 424 if (!strm->running || !substream || !substream->runtime) 425 return; 426 427 runtime = substream->runtime; 428 strm->buffer_pos += frames; 429 WARN_ON(strm->buffer_pos > runtime->buffer_size); 430 431 /* ring buffer */ 432 if (strm->buffer_pos == runtime->buffer_size) 433 strm->buffer_pos = 0; 434 435 current_period = strm->buffer_pos / runtime->period_size; 436 if (strm->period_counter != current_period) { 437 snd_pcm_period_elapsed(strm->substream); 438 strm->period_counter = current_period; 439 } 440 } 441 442 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 443 { 444 struct snd_pcm_substream *substream = strm->substream; 445 struct snd_pcm_runtime *runtime; 446 u16 *buf; 447 int fifo_samples; 448 int frames_left; 449 int samples; 450 int i; 451 452 if (!rz_ssi_stream_is_valid(ssi, strm)) 453 return -EINVAL; 454 455 runtime = substream->runtime; 456 457 do { 458 /* frames left in this period */ 459 frames_left = runtime->period_size - 460 (strm->buffer_pos % runtime->period_size); 461 if (!frames_left) 462 frames_left = runtime->period_size; 463 464 /* Samples in RX FIFO */ 465 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 466 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 467 468 /* Only read full frames at a time */ 469 samples = 0; 470 while (frames_left && (fifo_samples >= runtime->channels)) { 471 samples += runtime->channels; 472 fifo_samples -= runtime->channels; 473 frames_left--; 474 } 475 476 /* not enough samples yet */ 477 if (!samples) 478 break; 479 480 /* calculate new buffer index */ 481 buf = (u16 *)runtime->dma_area; 482 buf += strm->buffer_pos * runtime->channels; 483 484 /* Note, only supports 16-bit samples */ 485 for (i = 0; i < samples; i++) 486 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 487 488 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 489 rz_ssi_pointer_update(strm, samples / runtime->channels); 490 } while (!frames_left && fifo_samples >= runtime->channels); 491 492 return 0; 493 } 494 495 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 496 { 497 struct snd_pcm_substream *substream = strm->substream; 498 struct snd_pcm_runtime *runtime = substream->runtime; 499 int sample_space; 500 int samples = 0; 501 int frames_left; 502 int i; 503 u32 ssifsr; 504 u16 *buf; 505 506 if (!rz_ssi_stream_is_valid(ssi, strm)) 507 return -EINVAL; 508 509 /* frames left in this period */ 510 frames_left = runtime->period_size - (strm->buffer_pos % 511 runtime->period_size); 512 if (frames_left == 0) 513 frames_left = runtime->period_size; 514 515 sample_space = strm->fifo_sample_size; 516 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 517 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 518 if (sample_space < 0) 519 return -EINVAL; 520 521 /* Only add full frames at a time */ 522 while (frames_left && (sample_space >= runtime->channels)) { 523 samples += runtime->channels; 524 sample_space -= runtime->channels; 525 frames_left--; 526 } 527 528 /* no space to send anything right now */ 529 if (samples == 0) 530 return 0; 531 532 /* calculate new buffer index */ 533 buf = (u16 *)(runtime->dma_area); 534 buf += strm->buffer_pos * runtime->channels; 535 536 /* Note, only supports 16-bit samples */ 537 for (i = 0; i < samples; i++) 538 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 539 540 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 541 rz_ssi_pointer_update(strm, samples / runtime->channels); 542 543 return 0; 544 } 545 546 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 547 { 548 struct rz_ssi_stream *strm_playback = NULL; 549 struct rz_ssi_stream *strm_capture = NULL; 550 struct rz_ssi_priv *ssi = data; 551 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 552 553 if (ssi->playback.substream) 554 strm_playback = &ssi->playback; 555 if (ssi->capture.substream) 556 strm_capture = &ssi->capture; 557 558 if (!strm_playback && !strm_capture) 559 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 560 561 if (irq == ssi->irq_int) { /* error or idle */ 562 bool is_stopped = false; 563 int i, count; 564 565 if (rz_ssi_is_dma_enabled(ssi)) 566 count = 4; 567 else 568 count = 1; 569 570 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 571 is_stopped = true; 572 573 if (ssi->capture.substream && is_stopped) { 574 if (ssisr & SSISR_RUIRQ) 575 strm_capture->uerr_num++; 576 if (ssisr & SSISR_ROIRQ) 577 strm_capture->oerr_num++; 578 579 rz_ssi_stop(ssi, strm_capture); 580 } 581 582 if (ssi->playback.substream && is_stopped) { 583 if (ssisr & SSISR_TUIRQ) 584 strm_playback->uerr_num++; 585 if (ssisr & SSISR_TOIRQ) 586 strm_playback->oerr_num++; 587 588 rz_ssi_stop(ssi, strm_playback); 589 } 590 591 /* Clear all flags */ 592 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 593 SSISR_ROIRQ | SSISR_RUIRQ, 0); 594 595 /* Add/remove more data */ 596 if (ssi->capture.substream && is_stopped) { 597 for (i = 0; i < count; i++) 598 strm_capture->transfer(ssi, strm_capture); 599 } 600 601 if (ssi->playback.substream && is_stopped) { 602 for (i = 0; i < count; i++) 603 strm_playback->transfer(ssi, strm_playback); 604 } 605 606 /* Resume */ 607 if (ssi->playback.substream && is_stopped) 608 rz_ssi_start(ssi, &ssi->playback); 609 if (ssi->capture.substream && is_stopped) 610 rz_ssi_start(ssi, &ssi->capture); 611 } 612 613 if (!rz_ssi_is_stream_running(&ssi->playback) && 614 !rz_ssi_is_stream_running(&ssi->capture)) 615 return IRQ_HANDLED; 616 617 /* tx data empty */ 618 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 619 strm_playback->transfer(ssi, &ssi->playback); 620 621 /* rx data full */ 622 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 623 strm_capture->transfer(ssi, &ssi->capture); 624 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 625 } 626 627 if (irq == ssi->irq_rt) { 628 if (ssi->playback.substream) { 629 strm_playback->transfer(ssi, &ssi->playback); 630 } else { 631 strm_capture->transfer(ssi, &ssi->capture); 632 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 633 } 634 } 635 636 return IRQ_HANDLED; 637 } 638 639 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 640 struct dma_chan *dma_ch, bool is_play) 641 { 642 struct dma_slave_config cfg; 643 644 memset(&cfg, 0, sizeof(cfg)); 645 646 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 647 cfg.dst_addr = ssi->phys + SSIFTDR; 648 cfg.src_addr = ssi->phys + SSIFRDR; 649 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 650 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 651 652 return dmaengine_slave_config(dma_ch, &cfg); 653 } 654 655 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 656 struct rz_ssi_stream *strm) 657 { 658 struct snd_pcm_substream *substream = strm->substream; 659 struct dma_async_tx_descriptor *desc; 660 struct snd_pcm_runtime *runtime; 661 enum dma_transfer_direction dir; 662 u32 dma_paddr, dma_size; 663 int amount; 664 665 if (!rz_ssi_stream_is_valid(ssi, strm)) 666 return -EINVAL; 667 668 runtime = substream->runtime; 669 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 670 /* 671 * Stream is ending, so do not queue up any more DMA 672 * transfers otherwise we play partial sound clips 673 * because we can't shut off the DMA quick enough. 674 */ 675 return 0; 676 677 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 678 679 /* Always transfer 1 period */ 680 amount = runtime->period_size; 681 682 /* DMA physical address and size */ 683 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 684 strm->dma_buffer_pos); 685 dma_size = frames_to_bytes(runtime, amount); 686 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 687 dir, 688 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 689 if (!desc) { 690 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 691 return -ENOMEM; 692 } 693 694 desc->callback = rz_ssi_dma_complete; 695 desc->callback_param = strm; 696 697 if (dmaengine_submit(desc) < 0) { 698 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 699 return -EIO; 700 } 701 702 /* Update DMA pointer */ 703 strm->dma_buffer_pos += amount; 704 if (strm->dma_buffer_pos >= runtime->buffer_size) 705 strm->dma_buffer_pos = 0; 706 707 /* Start DMA */ 708 dma_async_issue_pending(strm->dma_ch); 709 710 return 0; 711 } 712 713 static void rz_ssi_dma_complete(void *data) 714 { 715 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 716 717 if (!strm->running || !strm->substream || !strm->substream->runtime) 718 return; 719 720 /* Note that next DMA transaction has probably already started */ 721 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 722 723 /* Queue up another DMA transaction */ 724 rz_ssi_dma_transfer(strm->priv, strm); 725 } 726 727 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 728 { 729 if (ssi->playback.dma_ch) { 730 dma_release_channel(ssi->playback.dma_ch); 731 ssi->playback.dma_ch = NULL; 732 if (ssi->dma_rt) 733 ssi->dma_rt = false; 734 } 735 736 if (ssi->capture.dma_ch) { 737 dma_release_channel(ssi->capture.dma_ch); 738 ssi->capture.dma_ch = NULL; 739 } 740 } 741 742 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 743 { 744 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 745 if (IS_ERR(ssi->playback.dma_ch)) 746 ssi->playback.dma_ch = NULL; 747 748 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 749 if (IS_ERR(ssi->capture.dma_ch)) 750 ssi->capture.dma_ch = NULL; 751 752 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 753 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 754 if (IS_ERR(ssi->playback.dma_ch)) { 755 ssi->playback.dma_ch = NULL; 756 goto no_dma; 757 } 758 759 ssi->dma_rt = true; 760 } 761 762 if (!rz_ssi_is_dma_enabled(ssi)) 763 goto no_dma; 764 765 if (ssi->playback.dma_ch && 766 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 767 goto no_dma; 768 769 if (ssi->capture.dma_ch && 770 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 771 goto no_dma; 772 773 return 0; 774 775 no_dma: 776 rz_ssi_release_dma_channels(ssi); 777 778 return -ENODEV; 779 } 780 781 static int rz_ssi_trigger_resume(struct rz_ssi_priv *ssi) 782 { 783 int ret; 784 785 if (rz_ssi_is_stream_running(&ssi->playback) || 786 rz_ssi_is_stream_running(&ssi->capture)) 787 return 0; 788 789 ret = rz_ssi_swreset(ssi); 790 if (ret) 791 return ret; 792 793 return rz_ssi_clk_setup(ssi, ssi->hw_params_cache.rate, 794 ssi->hw_params_cache.channels); 795 } 796 797 static void rz_ssi_streams_suspend(struct rz_ssi_priv *ssi) 798 { 799 if (rz_ssi_is_stream_running(&ssi->playback) || 800 rz_ssi_is_stream_running(&ssi->capture)) 801 return; 802 803 ssi->playback.dma_buffer_pos = 0; 804 ssi->capture.dma_buffer_pos = 0; 805 } 806 807 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 808 struct snd_soc_dai *dai) 809 { 810 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 811 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 812 int ret = 0, i, num_transfer = 1; 813 814 switch (cmd) { 815 case SNDRV_PCM_TRIGGER_RESUME: 816 ret = rz_ssi_trigger_resume(ssi); 817 if (ret) 818 return ret; 819 820 fallthrough; 821 822 case SNDRV_PCM_TRIGGER_START: 823 if (cmd == SNDRV_PCM_TRIGGER_START) 824 rz_ssi_stream_init(strm, substream); 825 826 if (ssi->dma_rt) { 827 bool is_playback; 828 829 is_playback = rz_ssi_stream_is_play(substream); 830 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 831 is_playback); 832 /* Fallback to pio */ 833 if (ret < 0) { 834 ssi->playback.transfer = rz_ssi_pio_send; 835 ssi->capture.transfer = rz_ssi_pio_recv; 836 rz_ssi_release_dma_channels(ssi); 837 } 838 } 839 840 /* For DMA, queue up multiple DMA descriptors */ 841 if (rz_ssi_is_dma_enabled(ssi)) 842 num_transfer = 4; 843 844 for (i = 0; i < num_transfer; i++) { 845 ret = strm->transfer(ssi, strm); 846 if (ret) 847 goto done; 848 } 849 850 ret = rz_ssi_start(ssi, strm); 851 break; 852 853 case SNDRV_PCM_TRIGGER_SUSPEND: 854 rz_ssi_stop(ssi, strm); 855 rz_ssi_streams_suspend(ssi); 856 break; 857 858 case SNDRV_PCM_TRIGGER_STOP: 859 rz_ssi_stop(ssi, strm); 860 rz_ssi_stream_quit(ssi, strm); 861 break; 862 } 863 864 done: 865 return ret; 866 } 867 868 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 869 { 870 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 871 872 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 873 case SND_SOC_DAIFMT_BP_FP: 874 break; 875 default: 876 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 877 return -EINVAL; 878 } 879 880 /* 881 * set clock polarity 882 * 883 * "normal" BCLK = Signal is available at rising edge of BCLK 884 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 885 */ 886 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 887 case SND_SOC_DAIFMT_NB_NF: 888 ssi->bckp_rise = false; 889 ssi->lrckp_fsync_fall = false; 890 break; 891 case SND_SOC_DAIFMT_NB_IF: 892 ssi->bckp_rise = false; 893 ssi->lrckp_fsync_fall = true; 894 break; 895 case SND_SOC_DAIFMT_IB_NF: 896 ssi->bckp_rise = true; 897 ssi->lrckp_fsync_fall = false; 898 break; 899 case SND_SOC_DAIFMT_IB_IF: 900 ssi->bckp_rise = true; 901 ssi->lrckp_fsync_fall = true; 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 /* only i2s support */ 908 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 909 case SND_SOC_DAIFMT_I2S: 910 break; 911 default: 912 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 913 return -EINVAL; 914 } 915 916 return 0; 917 } 918 919 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 920 unsigned int channels, 921 unsigned int sample_width, 922 unsigned int sample_bits) 923 { 924 if (ssi->hw_params_cache.rate != rate || 925 ssi->hw_params_cache.channels != channels || 926 ssi->hw_params_cache.sample_width != sample_width || 927 ssi->hw_params_cache.sample_bits != sample_bits) 928 return false; 929 930 return true; 931 } 932 933 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 934 unsigned int channels, 935 unsigned int sample_width, 936 unsigned int sample_bits) 937 { 938 ssi->hw_params_cache.rate = rate; 939 ssi->hw_params_cache.channels = channels; 940 ssi->hw_params_cache.sample_width = sample_width; 941 ssi->hw_params_cache.sample_bits = sample_bits; 942 } 943 944 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 945 struct snd_pcm_hw_params *params, 946 struct snd_soc_dai *dai) 947 { 948 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 949 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 950 unsigned int sample_bits = hw_param_interval(params, 951 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 952 unsigned int channels = params_channels(params); 953 unsigned int rate = params_rate(params); 954 int ret; 955 956 if (sample_bits != 16) { 957 dev_err(ssi->dev, "Unsupported sample width: %d\n", 958 sample_bits); 959 return -EINVAL; 960 } 961 962 if (channels != 2) { 963 dev_err(ssi->dev, "Number of channels not matched: %d\n", 964 channels); 965 return -EINVAL; 966 } 967 968 if (rz_ssi_is_stream_running(&ssi->playback) || 969 rz_ssi_is_stream_running(&ssi->capture)) { 970 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 971 strm->sample_width, sample_bits)) 972 return 0; 973 974 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 975 return -EINVAL; 976 } 977 978 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 979 sample_bits); 980 981 ret = rz_ssi_swreset(ssi); 982 if (ret) 983 return ret; 984 985 return rz_ssi_clk_setup(ssi, rate, channels); 986 } 987 988 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 989 .trigger = rz_ssi_dai_trigger, 990 .set_fmt = rz_ssi_dai_set_fmt, 991 .hw_params = rz_ssi_dai_hw_params, 992 }; 993 994 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 995 .info = SNDRV_PCM_INFO_INTERLEAVED | 996 SNDRV_PCM_INFO_MMAP | 997 SNDRV_PCM_INFO_MMAP_VALID | 998 SNDRV_PCM_INFO_RESUME, 999 .buffer_bytes_max = PREALLOC_BUFFER, 1000 .period_bytes_min = 32, 1001 .period_bytes_max = 8192, 1002 .channels_min = SSI_CHAN_MIN, 1003 .channels_max = SSI_CHAN_MAX, 1004 .periods_min = 1, 1005 .periods_max = 32, 1006 .fifo_size = 32 * 2, 1007 }; 1008 1009 static int rz_ssi_pcm_open(struct snd_soc_component *component, 1010 struct snd_pcm_substream *substream) 1011 { 1012 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 1013 1014 return snd_pcm_hw_constraint_integer(substream->runtime, 1015 SNDRV_PCM_HW_PARAM_PERIODS); 1016 } 1017 1018 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 1019 struct snd_pcm_substream *substream) 1020 { 1021 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1022 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 1023 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 1024 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 1025 1026 return strm->buffer_pos; 1027 } 1028 1029 static int rz_ssi_pcm_new(struct snd_soc_component *component, 1030 struct snd_soc_pcm_runtime *rtd) 1031 { 1032 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 1033 rtd->card->snd_card->dev, 1034 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1035 return 0; 1036 } 1037 1038 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1039 { 1040 .name = "rz-ssi-dai", 1041 .playback = { 1042 .rates = SSI_RATES, 1043 .formats = SSI_FMTS, 1044 .channels_min = SSI_CHAN_MIN, 1045 .channels_max = SSI_CHAN_MAX, 1046 }, 1047 .capture = { 1048 .rates = SSI_RATES, 1049 .formats = SSI_FMTS, 1050 .channels_min = SSI_CHAN_MIN, 1051 .channels_max = SSI_CHAN_MAX, 1052 }, 1053 .ops = &rz_ssi_dai_ops, 1054 }, 1055 }; 1056 1057 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1058 .name = "rz-ssi", 1059 .open = rz_ssi_pcm_open, 1060 .pointer = rz_ssi_pcm_pointer, 1061 .pcm_construct = rz_ssi_pcm_new, 1062 .legacy_dai_naming = 1, 1063 }; 1064 1065 static int rz_ssi_probe(struct platform_device *pdev) 1066 { 1067 struct device *dev = &pdev->dev; 1068 struct rz_ssi_priv *ssi; 1069 struct clk *audio_clk; 1070 struct resource *res; 1071 int ret; 1072 1073 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1074 if (!ssi) 1075 return -ENOMEM; 1076 1077 ssi->dev = dev; 1078 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1079 if (IS_ERR(ssi->base)) 1080 return PTR_ERR(ssi->base); 1081 1082 ssi->phys = res->start; 1083 ssi->clk = devm_clk_get(dev, "ssi"); 1084 if (IS_ERR(ssi->clk)) 1085 return PTR_ERR(ssi->clk); 1086 1087 ssi->sfr_clk = devm_clk_get(dev, "ssi_sfr"); 1088 if (IS_ERR(ssi->sfr_clk)) 1089 return PTR_ERR(ssi->sfr_clk); 1090 1091 audio_clk = devm_clk_get(dev, "audio_clk1"); 1092 if (IS_ERR(audio_clk)) 1093 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1094 "no audio clk1"); 1095 1096 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1097 audio_clk = devm_clk_get(dev, "audio_clk2"); 1098 if (IS_ERR(audio_clk)) 1099 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1100 "no audio clk2"); 1101 1102 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1103 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1104 return dev_err_probe(&pdev->dev, -EINVAL, 1105 "no audio clk1 or audio clk2"); 1106 1107 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1108 1109 /* Detect DMA support */ 1110 ret = rz_ssi_dma_request(ssi, dev); 1111 if (ret < 0) { 1112 dev_warn(dev, "DMA not available, using PIO\n"); 1113 ssi->playback.transfer = rz_ssi_pio_send; 1114 ssi->capture.transfer = rz_ssi_pio_recv; 1115 } else { 1116 dev_info(dev, "DMA enabled"); 1117 ssi->playback.transfer = rz_ssi_dma_transfer; 1118 ssi->capture.transfer = rz_ssi_dma_transfer; 1119 } 1120 1121 ssi->playback.priv = ssi; 1122 ssi->capture.priv = ssi; 1123 1124 spin_lock_init(&ssi->lock); 1125 dev_set_drvdata(dev, ssi); 1126 1127 /* Error Interrupt */ 1128 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1129 if (ssi->irq_int < 0) { 1130 ret = ssi->irq_int; 1131 goto err_release_dma_chs; 1132 } 1133 1134 ret = devm_request_irq(dev, ssi->irq_int, &rz_ssi_interrupt, 1135 0, dev_name(dev), ssi); 1136 if (ret < 0) { 1137 dev_err_probe(dev, ret, "irq request error (int_req)\n"); 1138 goto err_release_dma_chs; 1139 } 1140 1141 if (!rz_ssi_is_dma_enabled(ssi)) { 1142 /* Tx and Rx interrupts (pio only) */ 1143 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1144 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1145 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1146 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1147 if (ssi->irq_rt < 0) 1148 return ssi->irq_rt; 1149 1150 ret = devm_request_irq(dev, ssi->irq_rt, 1151 &rz_ssi_interrupt, 0, 1152 dev_name(dev), ssi); 1153 if (ret < 0) 1154 return dev_err_probe(dev, ret, 1155 "irq request error (dma_rt)\n"); 1156 } else { 1157 if (ssi->irq_tx < 0) 1158 return ssi->irq_tx; 1159 1160 if (ssi->irq_rx < 0) 1161 return ssi->irq_rx; 1162 1163 ret = devm_request_irq(dev, ssi->irq_tx, 1164 &rz_ssi_interrupt, 0, 1165 dev_name(dev), ssi); 1166 if (ret < 0) 1167 return dev_err_probe(dev, ret, 1168 "irq request error (dma_tx)\n"); 1169 1170 ret = devm_request_irq(dev, ssi->irq_rx, 1171 &rz_ssi_interrupt, 0, 1172 dev_name(dev), ssi); 1173 if (ret < 0) 1174 return dev_err_probe(dev, ret, 1175 "irq request error (dma_rx)\n"); 1176 } 1177 } 1178 1179 ssi->rstc = devm_reset_control_get_exclusive(dev, NULL); 1180 if (IS_ERR(ssi->rstc)) { 1181 ret = PTR_ERR(ssi->rstc); 1182 goto err_release_dma_chs; 1183 } 1184 1185 /* Default 0 for power saving. Can be overridden via sysfs. */ 1186 pm_runtime_set_autosuspend_delay(dev, 0); 1187 pm_runtime_use_autosuspend(dev); 1188 ret = devm_pm_runtime_enable(dev); 1189 if (ret < 0) { 1190 dev_err(dev, "Failed to enable runtime PM!\n"); 1191 goto err_release_dma_chs; 1192 } 1193 1194 ret = devm_snd_soc_register_component(dev, &rz_ssi_soc_component, 1195 rz_ssi_soc_dai, 1196 ARRAY_SIZE(rz_ssi_soc_dai)); 1197 if (ret < 0) { 1198 dev_err(dev, "failed to register snd component\n"); 1199 goto err_release_dma_chs; 1200 } 1201 1202 return 0; 1203 1204 err_release_dma_chs: 1205 rz_ssi_release_dma_channels(ssi); 1206 1207 return ret; 1208 } 1209 1210 static void rz_ssi_remove(struct platform_device *pdev) 1211 { 1212 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1213 1214 rz_ssi_release_dma_channels(ssi); 1215 1216 reset_control_assert(ssi->rstc); 1217 } 1218 1219 static const struct of_device_id rz_ssi_of_match[] = { 1220 { .compatible = "renesas,rz-ssi", }, 1221 {/* Sentinel */}, 1222 }; 1223 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1224 1225 static int rz_ssi_runtime_suspend(struct device *dev) 1226 { 1227 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1228 1229 return reset_control_assert(ssi->rstc); 1230 } 1231 1232 static int rz_ssi_runtime_resume(struct device *dev) 1233 { 1234 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1235 1236 return reset_control_deassert(ssi->rstc); 1237 } 1238 1239 static const struct dev_pm_ops rz_ssi_pm_ops = { 1240 RUNTIME_PM_OPS(rz_ssi_runtime_suspend, rz_ssi_runtime_resume, NULL) 1241 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1242 }; 1243 1244 static struct platform_driver rz_ssi_driver = { 1245 .driver = { 1246 .name = "rz-ssi-pcm-audio", 1247 .of_match_table = rz_ssi_of_match, 1248 .pm = pm_ptr(&rz_ssi_pm_ops), 1249 }, 1250 .probe = rz_ssi_probe, 1251 .remove = rz_ssi_remove, 1252 }; 1253 1254 module_platform_driver(rz_ssi_driver); 1255 1256 MODULE_LICENSE("GPL v2"); 1257 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1258 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1259