1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/clk.h> 4 #include <linux/delay.h> 5 #include <linux/device.h> 6 #include <linux/err.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 #include <linux/of.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/spi/spi.h> 13 #include <linux/units.h> 14 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_bridge.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_mipi_dsi.h> 19 #include <drm/drm_of.h> 20 #include <video/mipi_display.h> 21 22 #define SSD2825_DEVICE_ID_REG 0xb0 23 #define SSD2825_RGB_INTERFACE_CTRL_REG_1 0xb1 24 #define SSD2825_RGB_INTERFACE_CTRL_REG_2 0xb2 25 #define SSD2825_RGB_INTERFACE_CTRL_REG_3 0xb3 26 #define SSD2825_RGB_INTERFACE_CTRL_REG_4 0xb4 27 #define SSD2825_RGB_INTERFACE_CTRL_REG_5 0xb5 28 #define SSD2825_RGB_INTERFACE_CTRL_REG_6 0xb6 29 #define SSD2825_NON_BURST_EV BIT(2) 30 #define SSD2825_BURST BIT(3) 31 #define SSD2825_PCKL_HIGH BIT(13) 32 #define SSD2825_HSYNC_HIGH BIT(14) 33 #define SSD2825_VSYNC_HIGH BIT(15) 34 #define SSD2825_CONFIGURATION_REG 0xb7 35 #define SSD2825_CONF_REG_HS BIT(0) 36 #define SSD2825_CONF_REG_CKE BIT(1) 37 #define SSD2825_CONF_REG_SLP BIT(2) 38 #define SSD2825_CONF_REG_VEN BIT(3) 39 #define SSD2825_CONF_REG_HCLK BIT(4) 40 #define SSD2825_CONF_REG_CSS BIT(5) 41 #define SSD2825_CONF_REG_DCS BIT(6) 42 #define SSD2825_CONF_REG_REN BIT(7) 43 #define SSD2825_CONF_REG_ECD BIT(8) 44 #define SSD2825_CONF_REG_EOT BIT(9) 45 #define SSD2825_CONF_REG_LPE BIT(10) 46 #define SSD2825_VC_CTRL_REG 0xb8 47 #define SSD2825_PLL_CTRL_REG 0xb9 48 #define SSD2825_PLL_CONFIGURATION_REG 0xba 49 #define SSD2825_CLOCK_CTRL_REG 0xbb 50 #define SSD2825_PACKET_SIZE_CTRL_REG_1 0xbc 51 #define SSD2825_PACKET_SIZE_CTRL_REG_2 0xbd 52 #define SSD2825_PACKET_SIZE_CTRL_REG_3 0xbe 53 #define SSD2825_PACKET_DROP_REG 0xbf 54 #define SSD2825_OPERATION_CTRL_REG 0xc0 55 #define SSD2825_MAX_RETURN_SIZE_REG 0xc1 56 #define SSD2825_RETURN_DATA_COUNT_REG 0xc2 57 #define SSD2825_ACK_RESPONSE_REG 0xc3 58 #define SSD2825_LINE_CTRL_REG 0xc4 59 #define SSD2825_INTERRUPT_CTRL_REG 0xc5 60 #define SSD2825_INTERRUPT_STATUS_REG 0xc6 61 #define SSD2825_ERROR_STATUS_REG 0xc7 62 #define SSD2825_DATA_FORMAT_REG 0xc8 63 #define SSD2825_DELAY_ADJ_REG_1 0xc9 64 #define SSD2825_DELAY_ADJ_REG_2 0xca 65 #define SSD2825_DELAY_ADJ_REG_3 0xcb 66 #define SSD2825_DELAY_ADJ_REG_4 0xcc 67 #define SSD2825_DELAY_ADJ_REG_5 0xcd 68 #define SSD2825_DELAY_ADJ_REG_6 0xce 69 #define SSD2825_HS_TX_TIMER_REG_1 0xcf 70 #define SSD2825_HS_TX_TIMER_REG_2 0xd0 71 #define SSD2825_LP_RX_TIMER_REG_1 0xd1 72 #define SSD2825_LP_RX_TIMER_REG_2 0xd2 73 #define SSD2825_TE_STATUS_REG 0xd3 74 #define SSD2825_SPI_READ_REG 0xd4 75 #define SSD2825_SPI_READ_REG_RESET 0xfa 76 #define SSD2825_PLL_LOCK_REG 0xd5 77 #define SSD2825_TEST_REG 0xd6 78 #define SSD2825_TE_COUNT_REG 0xd7 79 #define SSD2825_ANALOG_CTRL_REG_1 0xd8 80 #define SSD2825_ANALOG_CTRL_REG_2 0xd9 81 #define SSD2825_ANALOG_CTRL_REG_3 0xda 82 #define SSD2825_ANALOG_CTRL_REG_4 0xdb 83 #define SSD2825_INTERRUPT_OUT_CTRL_REG 0xdc 84 #define SSD2825_RGB_INTERFACE_CTRL_REG_7 0xdd 85 #define SSD2825_LANE_CONFIGURATION_REG 0xde 86 #define SSD2825_DELAY_ADJ_REG_7 0xdf 87 #define SSD2825_INPUT_PIN_CTRL_REG_1 0xe0 88 #define SSD2825_INPUT_PIN_CTRL_REG_2 0xe1 89 #define SSD2825_BIDIR_PIN_CTRL_REG_1 0xe2 90 #define SSD2825_BIDIR_PIN_CTRL_REG_2 0xe3 91 #define SSD2825_BIDIR_PIN_CTRL_REG_3 0xe4 92 #define SSD2825_BIDIR_PIN_CTRL_REG_4 0xe5 93 #define SSD2825_BIDIR_PIN_CTRL_REG_5 0xe6 94 #define SSD2825_BIDIR_PIN_CTRL_REG_6 0xe7 95 #define SSD2825_BIDIR_PIN_CTRL_REG_7 0xe8 96 #define SSD2825_CABC_BRIGHTNESS_CTRL_REG_1 0xe9 97 #define SSD2825_CABC_BRIGHTNESS_CTRL_REG_2 0xea 98 #define SSD2825_CABC_BRIGHTNESS_STATUS_REG 0xeb 99 #define SSD2825_READ_REG 0xff 100 101 #define SSD2825_COM_BYTE 0x00 102 #define SSD2825_DAT_BYTE 0x01 103 104 #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3f) 105 #define SSD2825_LP_MIN_CLK 5000 /* KHz */ 106 #define SSD2825_REF_MIN_CLK 2000 /* KHz */ 107 108 static const struct regulator_bulk_data ssd2825_supplies[] = { 109 { .supply = "dvdd" }, 110 { .supply = "avdd" }, 111 { .supply = "vddio" }, 112 }; 113 114 struct ssd2825_dsi_output { 115 struct mipi_dsi_device *dev; 116 struct drm_bridge *bridge; 117 }; 118 119 struct ssd2825_priv { 120 struct spi_device *spi; 121 struct device *dev; 122 123 struct gpio_desc *reset_gpio; 124 struct regulator_bulk_data *supplies; 125 126 struct clk *tx_clk; 127 128 struct mipi_dsi_host dsi_host; 129 struct drm_bridge bridge; 130 struct ssd2825_dsi_output output; 131 132 struct mutex mlock; /* for host transfer operations */ 133 134 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 135 u32 dsi_lanes; /* number of DSI Lanes */ 136 137 /* Parameters for PLL programming */ 138 u32 pll_freq_kbps; /* PLL in kbps */ 139 u32 nibble_freq_khz; /* PLL div by 4 */ 140 141 u32 hzd; /* HS Zero Delay in ns*/ 142 u32 hpd; /* HS Prepare Delay is ns */ 143 }; 144 145 static inline struct ssd2825_priv *dsi_host_to_ssd2825(struct mipi_dsi_host *host) 146 { 147 return container_of(host, struct ssd2825_priv, dsi_host); 148 } 149 150 static inline struct ssd2825_priv *bridge_to_ssd2825(struct drm_bridge *bridge) 151 { 152 return container_of(bridge, struct ssd2825_priv, bridge); 153 } 154 155 static int ssd2825_write_raw(struct ssd2825_priv *priv, u8 high_byte, u8 low_byte) 156 { 157 struct spi_device *spi = priv->spi; 158 u8 tx_buf[2]; 159 160 /* 161 * Low byte is the value, high byte defines type of 162 * write cycle, 0 for command and 1 for data. 163 */ 164 tx_buf[0] = low_byte; 165 tx_buf[1] = high_byte; 166 167 return spi_write(spi, tx_buf, 2); 168 } 169 170 static int ssd2825_write_reg(struct ssd2825_priv *priv, u8 reg, u16 command) 171 { 172 u8 datal = (command & 0x00FF); 173 u8 datah = (command & 0xFF00) >> 8; 174 int ret; 175 176 /* Command write cycle */ 177 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg); 178 if (ret) 179 return ret; 180 181 /* Data write cycle bits 7-0 */ 182 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datal); 183 if (ret) 184 return ret; 185 186 /* Data write cycle bits 15-8 */ 187 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datah); 188 if (ret) 189 return ret; 190 191 return 0; 192 } 193 194 static int ssd2825_write_dsi(struct ssd2825_priv *priv, const u8 *command, int len) 195 { 196 int ret, i; 197 198 ret = ssd2825_write_reg(priv, SSD2825_PACKET_SIZE_CTRL_REG_1, len); 199 if (ret) 200 return ret; 201 202 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, SSD2825_PACKET_DROP_REG); 203 if (ret) 204 return ret; 205 206 for (i = 0; i < len; i++) { 207 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, command[i]); 208 if (ret) 209 return ret; 210 } 211 212 return 0; 213 } 214 215 static int ssd2825_read_raw(struct ssd2825_priv *priv, u8 cmd, u16 *data) 216 { 217 struct spi_device *spi = priv->spi; 218 struct spi_message msg; 219 struct spi_transfer xfer[2]; 220 u8 tx_buf[2]; 221 u8 rx_buf[2]; 222 int ret; 223 224 memset(&xfer, 0, sizeof(xfer)); 225 226 tx_buf[1] = (cmd & 0xFF00) >> 8; 227 tx_buf[0] = (cmd & 0x00FF); 228 229 xfer[0].tx_buf = tx_buf; 230 xfer[0].bits_per_word = 9; 231 xfer[0].len = 2; 232 233 xfer[1].rx_buf = rx_buf; 234 xfer[1].bits_per_word = 16; 235 xfer[1].len = 2; 236 237 spi_message_init(&msg); 238 spi_message_add_tail(&xfer[0], &msg); 239 spi_message_add_tail(&xfer[1], &msg); 240 241 ret = spi_sync(spi, &msg); 242 if (ret) { 243 dev_err(&spi->dev, "ssd2825 read raw failed %d\n", ret); 244 return ret; 245 } 246 247 *data = rx_buf[1] | (rx_buf[0] << 8); 248 249 return 0; 250 } 251 252 static int ssd2825_read_reg(struct ssd2825_priv *priv, u8 reg, u16 *data) 253 { 254 int ret; 255 256 /* Reset the read register */ 257 ret = ssd2825_write_reg(priv, SSD2825_SPI_READ_REG, SSD2825_SPI_READ_REG_RESET); 258 if (ret) 259 return ret; 260 261 /* Push the address to read */ 262 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg); 263 if (ret) 264 return ret; 265 266 /* Perform a reading cycle */ 267 ret = ssd2825_read_raw(priv, SSD2825_SPI_READ_REG_RESET, data); 268 if (ret) 269 return ret; 270 271 return 0; 272 } 273 274 static int ssd2825_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) 275 { 276 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 277 struct drm_bridge *bridge; 278 struct device_node *ep; 279 int ret; 280 281 if (dev->lanes > 4) { 282 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", dev->lanes); 283 return -EINVAL; 284 } 285 286 /* 287 * ssd2825 supports both Video and Pulse mode, but the driver only 288 * implements Video (event) mode currently 289 */ 290 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 291 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 292 return -EOPNOTSUPP; 293 } 294 295 bridge = of_drm_get_bridge_by_endpoint(host->dev->of_node, 1, 0); 296 if (IS_ERR(bridge)) 297 return PTR_ERR(bridge); 298 299 bridge->type = DRM_MODE_CONNECTOR_DSI; 300 301 priv->output.dev = dev; 302 priv->output.bridge = bridge; 303 304 priv->dsi_lanes = dev->lanes; 305 306 /* get input ep (port0/endpoint0) */ 307 ret = -EINVAL; 308 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 309 if (ep) { 310 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 311 of_node_put(ep); 312 } 313 314 if (ret) 315 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format); 316 317 drm_bridge_add(&priv->bridge); 318 319 return 0; 320 } 321 322 static int ssd2825_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) 323 { 324 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 325 326 drm_bridge_remove(&priv->bridge); 327 drm_bridge_put(priv->output.bridge); 328 329 return 0; 330 } 331 332 static ssize_t ssd2825_dsi_host_transfer(struct mipi_dsi_host *host, 333 const struct mipi_dsi_msg *msg) 334 { 335 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 336 u16 config; 337 int ret; 338 339 if (msg->rx_len) { 340 dev_warn(priv->dev, "MIPI rx is not supported\n"); 341 return -EOPNOTSUPP; 342 } 343 344 guard(mutex)(&priv->mlock); 345 346 ret = ssd2825_read_reg(priv, SSD2825_CONFIGURATION_REG, &config); 347 if (ret) 348 return ret; 349 350 switch (msg->type) { 351 case MIPI_DSI_DCS_SHORT_WRITE: 352 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 353 case MIPI_DSI_DCS_LONG_WRITE: 354 config |= SSD2825_CONF_REG_DCS; 355 break; 356 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 357 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 358 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 359 case MIPI_DSI_GENERIC_LONG_WRITE: 360 config &= ~SSD2825_CONF_REG_DCS; 361 break; 362 case MIPI_DSI_DCS_READ: 363 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 364 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 365 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 366 default: 367 return 0; 368 } 369 370 ret = ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 371 if (ret) 372 return ret; 373 374 ret = ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000); 375 if (ret) 376 return ret; 377 378 ret = ssd2825_write_dsi(priv, msg->tx_buf, msg->tx_len); 379 if (ret) 380 return ret; 381 382 return 0; 383 } 384 385 static const struct mipi_dsi_host_ops ssd2825_dsi_host_ops = { 386 .attach = ssd2825_dsi_host_attach, 387 .detach = ssd2825_dsi_host_detach, 388 .transfer = ssd2825_dsi_host_transfer, 389 }; 390 391 static void ssd2825_hw_reset(struct ssd2825_priv *priv) 392 { 393 gpiod_set_value_cansleep(priv->reset_gpio, 1); 394 usleep_range(5000, 6000); 395 gpiod_set_value_cansleep(priv->reset_gpio, 0); 396 usleep_range(5000, 6000); 397 } 398 399 /* 400 * PLL configuration register settings. 401 * 402 * See the "PLL Configuration Register Description" in the SSD2825 datasheet. 403 */ 404 static u16 construct_pll_config(struct ssd2825_priv *priv, 405 u32 desired_pll_freq_kbps, u32 reference_freq_khz) 406 { 407 u32 div_factor = 1, mul_factor, fr = 0; 408 409 while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK) 410 div_factor++; 411 if (div_factor > 31) 412 div_factor = 31; 413 414 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, 415 reference_freq_khz); 416 417 priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor; 418 priv->nibble_freq_khz = priv->pll_freq_kbps / 4; 419 420 if (priv->pll_freq_kbps >= 501000) 421 fr = 3; 422 else if (priv->pll_freq_kbps >= 251000) 423 fr = 2; 424 else if (priv->pll_freq_kbps >= 126000) 425 fr = 1; 426 427 return (fr << 14) | (div_factor << 8) | mul_factor; 428 } 429 430 static int ssd2825_setup_pll(struct ssd2825_priv *priv, 431 const struct drm_display_mode *mode) 432 { 433 u16 pll_config, lp_div; 434 u32 nibble_delay, pclk_mult, tx_freq_khz; 435 u8 hzd, hpd; 436 437 tx_freq_khz = clk_get_rate(priv->tx_clk) / KILO; 438 if (!tx_freq_khz) 439 tx_freq_khz = SSD2825_REF_MIN_CLK; 440 441 pclk_mult = priv->pd_lines / priv->dsi_lanes + 1; 442 pll_config = construct_pll_config(priv, pclk_mult * mode->clock, 443 tx_freq_khz); 444 445 lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8); 446 447 /* nibble_delay in nanoseconds */ 448 nibble_delay = MICRO / priv->nibble_freq_khz; 449 450 hzd = priv->hzd / nibble_delay; 451 hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay; 452 453 /* Disable PLL */ 454 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0000); 455 ssd2825_write_reg(priv, SSD2825_LINE_CTRL_REG, 0x0001); 456 457 /* Set delays */ 458 ssd2825_write_reg(priv, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd); 459 460 /* Set PLL coefficients */ 461 ssd2825_write_reg(priv, SSD2825_PLL_CONFIGURATION_REG, pll_config); 462 463 /* Clock Control Register */ 464 ssd2825_write_reg(priv, SSD2825_CLOCK_CTRL_REG, 465 SSD2828_LP_CLOCK_DIVIDER(lp_div)); 466 467 /* Enable PLL */ 468 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001); 469 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 470 471 return 0; 472 } 473 474 static void ssd2825_bridge_atomic_pre_enable(struct drm_bridge *bridge, 475 struct drm_atomic_commit *state) 476 { 477 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 478 struct mipi_dsi_device *dsi_dev = priv->output.dev; 479 const struct drm_crtc_state *crtc_state; 480 const struct drm_display_mode *mode; 481 struct drm_connector *connector; 482 struct drm_crtc *crtc; 483 u32 input_bus_flags = bridge->timings->input_bus_flags; 484 u16 flags = 0, config; 485 u8 pixel_format; 486 int ret; 487 488 /* Power Sequence */ 489 ret = clk_prepare_enable(priv->tx_clk); 490 if (ret) 491 dev_err(priv->dev, "error enabling tx_clk (%d)\n", ret); 492 493 ret = regulator_bulk_enable(ARRAY_SIZE(ssd2825_supplies), priv->supplies); 494 if (ret) 495 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 496 497 usleep_range(1000, 2000); 498 499 ssd2825_hw_reset(priv); 500 501 /* Perform SW reset */ 502 ssd2825_write_reg(priv, SSD2825_OPERATION_CTRL_REG, 0x0100); 503 504 /* Set pixel format */ 505 switch (dsi_dev->format) { 506 case MIPI_DSI_FMT_RGB565: 507 pixel_format = 0x00; 508 break; 509 case MIPI_DSI_FMT_RGB666_PACKED: 510 pixel_format = 0x01; 511 break; 512 case MIPI_DSI_FMT_RGB666: 513 pixel_format = 0x02; 514 break; 515 case MIPI_DSI_FMT_RGB888: 516 default: 517 pixel_format = 0x03; 518 break; 519 } 520 521 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 522 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 523 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 524 mode = &crtc_state->adjusted_mode; 525 526 /* Set panel timings */ 527 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_1, 528 ((mode->vtotal - mode->vsync_end) << 8) | 529 (mode->htotal - mode->hsync_end)); 530 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_2, 531 ((mode->vtotal - mode->vsync_start) << 8) | 532 (mode->htotal - mode->hsync_start)); 533 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_3, 534 ((mode->vsync_start - mode->vdisplay) << 8) | 535 (mode->hsync_start - mode->hdisplay)); 536 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_4, mode->hdisplay); 537 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_5, mode->vdisplay); 538 539 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 540 flags |= SSD2825_HSYNC_HIGH; 541 542 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 543 flags |= SSD2825_VSYNC_HIGH; 544 545 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO) 546 flags |= SSD2825_NON_BURST_EV; 547 548 if (input_bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE) 549 flags |= SSD2825_PCKL_HIGH; 550 551 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_6, flags | pixel_format); 552 ssd2825_write_reg(priv, SSD2825_LANE_CONFIGURATION_REG, dsi_dev->lanes - 1); 553 ssd2825_write_reg(priv, SSD2825_TEST_REG, 0x0004); 554 555 /* Call PLL configuration */ 556 ssd2825_setup_pll(priv, mode); 557 558 usleep_range(10000, 11000); 559 560 config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_CKE | SSD2825_CONF_REG_DCS | 561 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT; 562 563 if (dsi_dev->mode_flags & MIPI_DSI_MODE_LPM) 564 config &= ~SSD2825_CONF_REG_HS; 565 566 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 567 config &= ~SSD2825_CONF_REG_EOT; 568 569 /* Initial DSI configuration register set */ 570 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 571 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 572 } 573 574 static void ssd2825_bridge_atomic_enable(struct drm_bridge *bridge, 575 struct drm_atomic_commit *state) 576 { 577 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 578 struct mipi_dsi_device *dsi_dev = priv->output.dev; 579 u16 config; 580 581 config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_DCS | 582 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT; 583 584 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO) 585 config |= SSD2825_CONF_REG_VEN; 586 587 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 588 config &= ~SSD2825_CONF_REG_EOT; 589 590 /* Complete configuration after DSI commands were sent */ 591 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 592 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001); 593 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000); 594 } 595 596 static void ssd2825_bridge_atomic_disable(struct drm_bridge *bridge, 597 struct drm_atomic_commit *state) 598 { 599 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 600 int ret; 601 602 msleep(100); 603 604 /* Exit DSI configuration register set */ 605 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, 606 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT); 607 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 608 609 /* HW disable */ 610 gpiod_set_value_cansleep(priv->reset_gpio, 1); 611 usleep_range(5000, 6000); 612 613 ret = regulator_bulk_disable(ARRAY_SIZE(ssd2825_supplies), 614 priv->supplies); 615 if (ret < 0) 616 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 617 618 clk_disable_unprepare(priv->tx_clk); 619 } 620 621 static int ssd2825_bridge_attach(struct drm_bridge *bridge, struct drm_encoder *encoder, 622 enum drm_bridge_attach_flags flags) 623 { 624 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 625 626 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 627 flags); 628 } 629 630 static enum drm_mode_status 631 ssd2825_bridge_mode_valid(struct drm_bridge *bridge, 632 const struct drm_display_info *info, 633 const struct drm_display_mode *mode) 634 { 635 if (mode->hdisplay > 1366) 636 return MODE_H_ILLEGAL; 637 638 if (mode->vdisplay > 1366) 639 return MODE_V_ILLEGAL; 640 641 return MODE_OK; 642 } 643 644 static bool ssd2825_mode_fixup(struct drm_bridge *bridge, 645 const struct drm_display_mode *mode, 646 struct drm_display_mode *adjusted_mode) 647 { 648 /* Default to positive sync */ 649 650 if (!(adjusted_mode->flags & 651 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 652 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 653 654 if (!(adjusted_mode->flags & 655 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 656 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 657 658 return true; 659 } 660 661 static const struct drm_bridge_funcs ssd2825_bridge_funcs = { 662 .attach = ssd2825_bridge_attach, 663 .mode_valid = ssd2825_bridge_mode_valid, 664 .mode_fixup = ssd2825_mode_fixup, 665 666 .atomic_pre_enable = ssd2825_bridge_atomic_pre_enable, 667 .atomic_enable = ssd2825_bridge_atomic_enable, 668 .atomic_disable = ssd2825_bridge_atomic_disable, 669 670 .atomic_create_state = drm_atomic_helper_bridge_create_state, 671 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 672 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 673 }; 674 675 static const struct drm_bridge_timings default_ssd2825_timings = { 676 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 677 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 678 | DRM_BUS_FLAG_DE_HIGH, 679 }; 680 681 static int ssd2825_probe(struct spi_device *spi) 682 { 683 struct ssd2825_priv *priv; 684 struct device *dev = &spi->dev; 685 struct device_node *np = dev->of_node; 686 int ret; 687 688 /* Driver supports only 8 bit 3 Wire mode */ 689 spi->bits_per_word = 9; 690 691 ret = spi_setup(spi); 692 if (ret) 693 return ret; 694 695 priv = devm_drm_bridge_alloc(dev, struct ssd2825_priv, bridge, &ssd2825_bridge_funcs); 696 if (IS_ERR(priv)) 697 return PTR_ERR(priv); 698 699 spi_set_drvdata(spi, priv); 700 701 priv->spi = spi; 702 priv->dev = dev; 703 704 mutex_init(&priv->mlock); 705 706 priv->tx_clk = devm_clk_get_optional(dev, NULL); 707 if (IS_ERR(priv->tx_clk)) 708 return dev_err_probe(dev, PTR_ERR(priv->tx_clk), 709 "can't retrieve bridge tx_clk\n"); 710 711 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 712 GPIOD_OUT_HIGH); 713 if (IS_ERR(priv->reset_gpio)) 714 return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), 715 "failed to get reset GPIO\n"); 716 717 ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(ssd2825_supplies), 718 ssd2825_supplies, &priv->supplies); 719 if (ret) 720 return dev_err_probe(dev, ret, "failed to get regulators\n"); 721 722 priv->hzd = 133; /* ns */ 723 device_property_read_u32(dev, "solomon,hs-zero-delay-ns", &priv->hzd); 724 725 priv->hpd = 40; /* ns */ 726 device_property_read_u32(dev, "solomon,hs-prep-delay-ns", &priv->hpd); 727 728 priv->dsi_host.dev = dev; 729 priv->dsi_host.ops = &ssd2825_dsi_host_ops; 730 731 priv->bridge.timings = &default_ssd2825_timings; 732 priv->bridge.of_node = np; 733 734 return mipi_dsi_host_register(&priv->dsi_host); 735 } 736 737 static void ssd2825_remove(struct spi_device *spi) 738 { 739 struct ssd2825_priv *priv = spi_get_drvdata(spi); 740 741 mipi_dsi_host_unregister(&priv->dsi_host); 742 } 743 744 static const struct of_device_id ssd2825_of_match[] = { 745 { .compatible = "solomon,ssd2825" }, 746 { /* sentinel */ } 747 }; 748 MODULE_DEVICE_TABLE(of, ssd2825_of_match); 749 750 static struct spi_driver ssd2825_driver = { 751 .driver = { 752 .name = "ssd2825", 753 .of_match_table = ssd2825_of_match, 754 }, 755 .probe = ssd2825_probe, 756 .remove = ssd2825_remove, 757 }; 758 module_spi_driver(ssd2825_driver); 759 760 MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>"); 761 MODULE_DESCRIPTION("Solomon SSD2825 RGB to MIPI-DSI bridge driver SPI"); 762 MODULE_LICENSE("GPL"); 763