1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DRM driver for Solomon SSD13xx OLED displays 4 * 5 * Copyright 2022 Red Hat Inc. 6 * Author: Javier Martinez Canillas <javierm@redhat.com> 7 * 8 * Based on drivers/video/fbdev/ssd1307fb.c 9 * Copyright 2012 Free Electrons 10 */ 11 12 #include <linux/backlight.h> 13 #include <linux/bitfield.h> 14 #include <linux/bits.h> 15 #include <linux/delay.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/property.h> 18 #include <linux/pwm.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <drm/clients/drm_client_setup.h> 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_crtc_helper.h> 25 #include <drm/drm_damage_helper.h> 26 #include <drm/drm_edid.h> 27 #include <drm/drm_fbdev_shmem.h> 28 #include <drm/drm_format_helper.h> 29 #include <drm/drm_framebuffer.h> 30 #include <drm/drm_gem_atomic_helper.h> 31 #include <drm/drm_gem_framebuffer_helper.h> 32 #include <drm/drm_gem_shmem_helper.h> 33 #include <drm/drm_managed.h> 34 #include <drm/drm_modes.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include "ssd130x.h" 40 41 #define DRIVER_NAME "ssd130x" 42 #define DRIVER_DESC "DRM driver for Solomon SSD13xx OLED displays" 43 #define DRIVER_MAJOR 1 44 #define DRIVER_MINOR 0 45 46 #define SSD130X_PAGE_HEIGHT 8 47 48 #define SSD132X_SEGMENT_WIDTH 2 49 50 /* ssd13xx commands */ 51 #define SSD13XX_CONTRAST 0x81 52 #define SSD13XX_SET_SEG_REMAP 0xa0 53 #define SSD13XX_SET_MULTIPLEX_RATIO 0xa8 54 #define SSD13XX_DISPLAY_OFF 0xae 55 #define SSD13XX_DISPLAY_ON 0xaf 56 57 #define SSD13XX_SET_SEG_REMAP_MASK GENMASK(0, 0) 58 #define SSD13XX_SET_SEG_REMAP_SET(val) FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val)) 59 60 /* ssd130x commands */ 61 #define SSD130X_PAGE_COL_START_LOW 0x00 62 #define SSD130X_PAGE_COL_START_HIGH 0x10 63 #define SSD130X_SET_ADDRESS_MODE 0x20 64 #define SSD130X_SET_COL_RANGE 0x21 65 #define SSD130X_SET_PAGE_RANGE 0x22 66 #define SSD130X_SET_LOOKUP_TABLE 0x91 67 #define SSD130X_CHARGE_PUMP 0x8d 68 #define SSD130X_START_PAGE_ADDRESS 0xb0 69 #define SSD130X_SET_COM_SCAN_DIR 0xc0 70 #define SSD130X_SET_DISPLAY_OFFSET 0xd3 71 #define SSD130X_SET_CLOCK_FREQ 0xd5 72 #define SSD130X_SET_AREA_COLOR_MODE 0xd8 73 #define SSD130X_SET_PRECHARGE_PERIOD 0xd9 74 #define SSD130X_SET_COM_PINS_CONFIG 0xda 75 #define SSD130X_SET_VCOMH 0xdb 76 77 /* ssd130x commands accessors */ 78 #define SSD130X_PAGE_COL_START_MASK GENMASK(3, 0) 79 #define SSD130X_PAGE_COL_START_HIGH_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4) 80 #define SSD130X_PAGE_COL_START_LOW_SET(val) FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val)) 81 #define SSD130X_START_PAGE_ADDRESS_MASK GENMASK(2, 0) 82 #define SSD130X_START_PAGE_ADDRESS_SET(val) FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val)) 83 #define SSD130X_SET_COM_SCAN_DIR_MASK GENMASK(3, 3) 84 #define SSD130X_SET_COM_SCAN_DIR_SET(val) FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val)) 85 #define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0) 86 #define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val)) 87 #define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4) 88 #define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val)) 89 #define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0) 90 #define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val)) 91 #define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4) 92 #define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val)) 93 #define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4) 94 #define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val)) 95 #define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5) 96 #define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val)) 97 98 #define SSD130X_SET_ADDRESS_MODE_HORIZONTAL 0x00 99 #define SSD130X_SET_ADDRESS_MODE_VERTICAL 0x01 100 #define SSD130X_SET_ADDRESS_MODE_PAGE 0x02 101 102 #define SSD130X_SET_AREA_COLOR_MODE_ENABLE 0x1e 103 #define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER 0x05 104 105 /* ssd132x commands */ 106 #define SSD132X_SET_COL_RANGE 0x15 107 #define SSD132X_SET_DEACTIVATE_SCROLL 0x2e 108 #define SSD132X_SET_ROW_RANGE 0x75 109 #define SSD132X_SET_DISPLAY_START 0xa1 110 #define SSD132X_SET_DISPLAY_OFFSET 0xa2 111 #define SSD132X_SET_DISPLAY_NORMAL 0xa4 112 #define SSD132X_SET_FUNCTION_SELECT_A 0xab 113 #define SSD132X_SET_PHASE_LENGTH 0xb1 114 #define SSD132X_SET_CLOCK_FREQ 0xb3 115 #define SSD132X_SET_GPIO 0xb5 116 #define SSD132X_SET_PRECHARGE_PERIOD 0xb6 117 #define SSD132X_SET_GRAY_SCALE_TABLE 0xb8 118 #define SSD132X_SELECT_DEFAULT_TABLE 0xb9 119 #define SSD132X_SET_PRECHARGE_VOLTAGE 0xbc 120 #define SSD130X_SET_VCOMH_VOLTAGE 0xbe 121 #define SSD132X_SET_FUNCTION_SELECT_B 0xd5 122 123 /* ssd133x commands */ 124 #define SSD133X_SET_COL_RANGE 0x15 125 #define SSD133X_SET_ROW_RANGE 0x75 126 #define SSD133X_CONTRAST_A 0x81 127 #define SSD133X_CONTRAST_B 0x82 128 #define SSD133X_CONTRAST_C 0x83 129 #define SSD133X_SET_MASTER_CURRENT 0x87 130 #define SSD132X_SET_PRECHARGE_A 0x8a 131 #define SSD132X_SET_PRECHARGE_B 0x8b 132 #define SSD132X_SET_PRECHARGE_C 0x8c 133 #define SSD133X_SET_DISPLAY_START 0xa1 134 #define SSD133X_SET_DISPLAY_OFFSET 0xa2 135 #define SSD133X_SET_DISPLAY_NORMAL 0xa4 136 #define SSD133X_SET_MASTER_CONFIG 0xad 137 #define SSD133X_POWER_SAVE_MODE 0xb0 138 #define SSD133X_PHASES_PERIOD 0xb1 139 #define SSD133X_SET_CLOCK_FREQ 0xb3 140 #define SSD133X_SET_PRECHARGE_VOLTAGE 0xbb 141 #define SSD133X_SET_VCOMH_VOLTAGE 0xbe 142 143 #define MAX_CONTRAST 255 144 145 const struct ssd130x_deviceinfo ssd130x_variants[] = { 146 [SH1106_ID] = { 147 .default_vcomh = 0x40, 148 .default_dclk_div = 1, 149 .default_dclk_frq = 5, 150 .default_width = 132, 151 .default_height = 64, 152 .page_mode_only = 1, 153 .family_id = SSD130X_FAMILY, 154 }, 155 [SSD1305_ID] = { 156 .default_vcomh = 0x34, 157 .default_dclk_div = 1, 158 .default_dclk_frq = 7, 159 .default_width = 132, 160 .default_height = 64, 161 .family_id = SSD130X_FAMILY, 162 }, 163 [SSD1306_ID] = { 164 .default_vcomh = 0x20, 165 .default_dclk_div = 1, 166 .default_dclk_frq = 8, 167 .need_chargepump = 1, 168 .default_width = 128, 169 .default_height = 64, 170 .family_id = SSD130X_FAMILY, 171 }, 172 [SSD1307_ID] = { 173 .default_vcomh = 0x20, 174 .default_dclk_div = 2, 175 .default_dclk_frq = 12, 176 .need_pwm = 1, 177 .default_width = 128, 178 .default_height = 39, 179 .family_id = SSD130X_FAMILY, 180 }, 181 [SSD1309_ID] = { 182 .default_vcomh = 0x34, 183 .default_dclk_div = 1, 184 .default_dclk_frq = 10, 185 .default_width = 128, 186 .default_height = 64, 187 .family_id = SSD130X_FAMILY, 188 }, 189 /* ssd132x family */ 190 [SSD1322_ID] = { 191 .default_width = 480, 192 .default_height = 128, 193 .family_id = SSD132X_FAMILY, 194 }, 195 [SSD1325_ID] = { 196 .default_width = 128, 197 .default_height = 80, 198 .family_id = SSD132X_FAMILY, 199 }, 200 [SSD1327_ID] = { 201 .default_width = 128, 202 .default_height = 128, 203 .family_id = SSD132X_FAMILY, 204 }, 205 /* ssd133x family */ 206 [SSD1331_ID] = { 207 .default_width = 96, 208 .default_height = 64, 209 .family_id = SSD133X_FAMILY, 210 } 211 }; 212 EXPORT_SYMBOL_NS_GPL(ssd130x_variants, "DRM_SSD130X"); 213 214 struct ssd130x_crtc_state { 215 struct drm_crtc_state base; 216 /* Buffer to store pixels in HW format and written to the panel */ 217 u8 *data_array; 218 }; 219 220 struct ssd130x_plane_state { 221 struct drm_shadow_plane_state base; 222 /* Intermediate buffer to convert pixels from XRGB8888 to HW format */ 223 u8 *buffer; 224 }; 225 226 static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state) 227 { 228 return container_of(state, struct ssd130x_crtc_state, base); 229 } 230 231 static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state) 232 { 233 return container_of(state, struct ssd130x_plane_state, base.base); 234 } 235 236 static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm) 237 { 238 return container_of(drm, struct ssd130x_device, drm); 239 } 240 241 /* 242 * Helper to write data (SSD13XX_DATA) to the device. 243 */ 244 static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count) 245 { 246 return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count); 247 } 248 249 /* 250 * Helper to write command (SSD13XX_COMMAND). The fist variadic argument 251 * is the command to write and the following are the command options. 252 * 253 * Note that the ssd13xx protocol requires each command and option to be 254 * written as a SSD13XX_COMMAND device register value. That is why a call 255 * to regmap_write(..., SSD13XX_COMMAND, ...) is done for each argument. 256 */ 257 static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count, 258 /* u8 cmd, u8 option, ... */...) 259 { 260 va_list ap; 261 u8 value; 262 int ret; 263 264 va_start(ap, count); 265 266 do { 267 value = va_arg(ap, int); 268 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, value); 269 if (ret) 270 goto out_end; 271 } while (--count); 272 273 out_end: 274 va_end(ap); 275 276 return ret; 277 } 278 279 /* Set address range for horizontal/vertical addressing modes */ 280 static int ssd130x_set_col_range(struct ssd130x_device *ssd130x, 281 u8 col_start, u8 cols) 282 { 283 u8 col_end = col_start + cols - 1; 284 int ret; 285 286 if (col_start == ssd130x->col_start && col_end == ssd130x->col_end) 287 return 0; 288 289 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_COL_RANGE, col_start, col_end); 290 if (ret < 0) 291 return ret; 292 293 ssd130x->col_start = col_start; 294 ssd130x->col_end = col_end; 295 return 0; 296 } 297 298 static int ssd130x_set_page_range(struct ssd130x_device *ssd130x, 299 u8 page_start, u8 pages) 300 { 301 u8 page_end = page_start + pages - 1; 302 int ret; 303 304 if (page_start == ssd130x->page_start && page_end == ssd130x->page_end) 305 return 0; 306 307 ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_PAGE_RANGE, page_start, page_end); 308 if (ret < 0) 309 return ret; 310 311 ssd130x->page_start = page_start; 312 ssd130x->page_end = page_end; 313 return 0; 314 } 315 316 /* Set page and column start address for page addressing mode */ 317 static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x, 318 u8 page_start, u8 col_start) 319 { 320 int ret; 321 u32 page, col_low, col_high; 322 323 page = SSD130X_START_PAGE_ADDRESS | 324 SSD130X_START_PAGE_ADDRESS_SET(page_start); 325 col_low = SSD130X_PAGE_COL_START_LOW | 326 SSD130X_PAGE_COL_START_LOW_SET(col_start); 327 col_high = SSD130X_PAGE_COL_START_HIGH | 328 SSD130X_PAGE_COL_START_HIGH_SET(col_start); 329 ret = ssd130x_write_cmd(ssd130x, 3, page, col_low, col_high); 330 if (ret < 0) 331 return ret; 332 333 return 0; 334 } 335 336 static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x) 337 { 338 struct device *dev = ssd130x->dev; 339 struct pwm_state pwmstate; 340 341 ssd130x->pwm = pwm_get(dev, NULL); 342 if (IS_ERR(ssd130x->pwm)) { 343 dev_err(dev, "Could not get PWM from firmware description!\n"); 344 return PTR_ERR(ssd130x->pwm); 345 } 346 347 pwm_init_state(ssd130x->pwm, &pwmstate); 348 pwm_set_relative_duty_cycle(&pwmstate, 50, 100); 349 pwm_apply_might_sleep(ssd130x->pwm, &pwmstate); 350 351 /* Enable the PWM */ 352 pwm_enable(ssd130x->pwm); 353 354 dev_dbg(dev, "Using PWM %s with a %lluns period.\n", 355 ssd130x->pwm->label, pwm_get_period(ssd130x->pwm)); 356 357 return 0; 358 } 359 360 static void ssd130x_reset(struct ssd130x_device *ssd130x) 361 { 362 if (!ssd130x->reset) 363 return; 364 365 /* Reset the screen */ 366 gpiod_set_value_cansleep(ssd130x->reset, 1); 367 udelay(4); 368 gpiod_set_value_cansleep(ssd130x->reset, 0); 369 udelay(4); 370 } 371 372 static int ssd130x_power_on(struct ssd130x_device *ssd130x) 373 { 374 struct device *dev = ssd130x->dev; 375 int ret; 376 377 ssd130x_reset(ssd130x); 378 379 ret = regulator_enable(ssd130x->vcc_reg); 380 if (ret) { 381 dev_err(dev, "Failed to enable VCC: %d\n", ret); 382 return ret; 383 } 384 385 if (ssd130x->device_info->need_pwm) { 386 ret = ssd130x_pwm_enable(ssd130x); 387 if (ret) { 388 dev_err(dev, "Failed to enable PWM: %d\n", ret); 389 regulator_disable(ssd130x->vcc_reg); 390 return ret; 391 } 392 } 393 394 return 0; 395 } 396 397 static void ssd130x_power_off(struct ssd130x_device *ssd130x) 398 { 399 pwm_disable(ssd130x->pwm); 400 pwm_put(ssd130x->pwm); 401 402 regulator_disable(ssd130x->vcc_reg); 403 } 404 405 static int ssd130x_init(struct ssd130x_device *ssd130x) 406 { 407 u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap; 408 bool scan_mode; 409 int ret; 410 411 /* Set initial contrast */ 412 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, ssd130x->contrast); 413 if (ret < 0) 414 return ret; 415 416 /* Set segment re-map */ 417 seg_remap = (SSD13XX_SET_SEG_REMAP | 418 SSD13XX_SET_SEG_REMAP_SET(ssd130x->seg_remap)); 419 ret = ssd130x_write_cmd(ssd130x, 1, seg_remap); 420 if (ret < 0) 421 return ret; 422 423 /* Set COM direction */ 424 com_invdir = (SSD130X_SET_COM_SCAN_DIR | 425 SSD130X_SET_COM_SCAN_DIR_SET(ssd130x->com_invdir)); 426 ret = ssd130x_write_cmd(ssd130x, 1, com_invdir); 427 if (ret < 0) 428 return ret; 429 430 /* Set multiplex ratio value */ 431 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1); 432 if (ret < 0) 433 return ret; 434 435 /* set display offset value */ 436 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset); 437 if (ret < 0) 438 return ret; 439 440 /* Set clock frequency */ 441 dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) | 442 SSD130X_SET_CLOCK_FREQ_SET(ssd130x->dclk_frq)); 443 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_CLOCK_FREQ, dclk); 444 if (ret < 0) 445 return ret; 446 447 /* Set Area Color Mode ON/OFF & Low Power Display Mode */ 448 if (ssd130x->area_color_enable || ssd130x->low_power) { 449 u32 mode = 0; 450 451 if (ssd130x->area_color_enable) 452 mode |= SSD130X_SET_AREA_COLOR_MODE_ENABLE; 453 454 if (ssd130x->low_power) 455 mode |= SSD130X_SET_AREA_COLOR_MODE_LOW_POWER; 456 457 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_AREA_COLOR_MODE, mode); 458 if (ret < 0) 459 return ret; 460 } 461 462 /* Set precharge period in number of ticks from the internal clock */ 463 precharge = (SSD130X_SET_PRECHARGE_PERIOD1_SET(ssd130x->prechargep1) | 464 SSD130X_SET_PRECHARGE_PERIOD2_SET(ssd130x->prechargep2)); 465 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_PRECHARGE_PERIOD, precharge); 466 if (ret < 0) 467 return ret; 468 469 /* Set COM pins configuration */ 470 compins = BIT(1); 471 /* 472 * The COM scan mode field values are the inverse of the boolean DT 473 * property "solomon,com-seq". The value 0b means scan from COM0 to 474 * COM[N - 1] while 1b means scan from COM[N - 1] to COM0. 475 */ 476 scan_mode = !ssd130x->com_seq; 477 compins |= (SSD130X_SET_COM_PINS_CONFIG1_SET(scan_mode) | 478 SSD130X_SET_COM_PINS_CONFIG2_SET(ssd130x->com_lrremap)); 479 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_COM_PINS_CONFIG, compins); 480 if (ret < 0) 481 return ret; 482 483 /* Set VCOMH */ 484 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH, ssd130x->vcomh); 485 if (ret < 0) 486 return ret; 487 488 /* Turn on the DC-DC Charge Pump */ 489 chargepump = BIT(4); 490 491 if (ssd130x->device_info->need_chargepump) 492 chargepump |= BIT(2); 493 494 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_CHARGE_PUMP, chargepump); 495 if (ret < 0) 496 return ret; 497 498 /* Set lookup table */ 499 if (ssd130x->lookup_table_set) { 500 int i; 501 502 ret = ssd130x_write_cmd(ssd130x, 1, SSD130X_SET_LOOKUP_TABLE); 503 if (ret < 0) 504 return ret; 505 506 for (i = 0; i < ARRAY_SIZE(ssd130x->lookup_table); i++) { 507 u8 val = ssd130x->lookup_table[i]; 508 509 if (val < 31 || val > 63) 510 dev_warn(ssd130x->dev, 511 "lookup table index %d value out of range 31 <= %d <= 63\n", 512 i, val); 513 ret = ssd130x_write_cmd(ssd130x, 1, val); 514 if (ret < 0) 515 return ret; 516 } 517 } 518 519 /* Switch to page addressing mode */ 520 if (ssd130x->page_address_mode) 521 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 522 SSD130X_SET_ADDRESS_MODE_PAGE); 523 524 /* Switch to horizontal addressing mode */ 525 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE, 526 SSD130X_SET_ADDRESS_MODE_HORIZONTAL); 527 } 528 529 static int ssd132x_init(struct ssd130x_device *ssd130x) 530 { 531 int ret; 532 533 /* Set initial contrast */ 534 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, 0x80); 535 if (ret < 0) 536 return ret; 537 538 /* Set column start and end */ 539 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, 0x00, 540 ssd130x->width / SSD132X_SEGMENT_WIDTH - 1); 541 if (ret < 0) 542 return ret; 543 544 /* Set row start and end */ 545 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, 0x00, ssd130x->height - 1); 546 if (ret < 0) 547 return ret; 548 /* 549 * Horizontal Address Increment 550 * Re-map for Column Address, Nibble and COM 551 * COM Split Odd Even 552 */ 553 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x53); 554 if (ret < 0) 555 return ret; 556 557 /* Set display start and offset */ 558 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_START, 0x00); 559 if (ret < 0) 560 return ret; 561 562 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_OFFSET, 0x00); 563 if (ret < 0) 564 return ret; 565 566 /* Set display mode normal */ 567 ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SET_DISPLAY_NORMAL); 568 if (ret < 0) 569 return ret; 570 571 /* Set multiplex ratio value */ 572 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1); 573 if (ret < 0) 574 return ret; 575 576 /* Set phase length */ 577 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PHASE_LENGTH, 0x55); 578 if (ret < 0) 579 return ret; 580 581 /* Select default linear gray scale table */ 582 ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SELECT_DEFAULT_TABLE); 583 if (ret < 0) 584 return ret; 585 586 /* Set clock frequency */ 587 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_CLOCK_FREQ, 0x01); 588 if (ret < 0) 589 return ret; 590 591 /* Enable internal VDD regulator */ 592 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_A, 0x1); 593 if (ret < 0) 594 return ret; 595 596 /* Set pre-charge period */ 597 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_PERIOD, 0x01); 598 if (ret < 0) 599 return ret; 600 601 /* Set pre-charge voltage */ 602 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_VOLTAGE, 0x08); 603 if (ret < 0) 604 return ret; 605 606 /* Set VCOMH voltage */ 607 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH_VOLTAGE, 0x07); 608 if (ret < 0) 609 return ret; 610 611 /* Enable second pre-charge and internal VSL */ 612 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_B, 0x62); 613 if (ret < 0) 614 return ret; 615 616 return 0; 617 } 618 619 static int ssd133x_init(struct ssd130x_device *ssd130x) 620 { 621 int ret; 622 623 /* Set color A contrast */ 624 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_A, 0x91); 625 if (ret < 0) 626 return ret; 627 628 /* Set color B contrast */ 629 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_B, 0x50); 630 if (ret < 0) 631 return ret; 632 633 /* Set color C contrast */ 634 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_C, 0x7d); 635 if (ret < 0) 636 return ret; 637 638 /* Set master current */ 639 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CURRENT, 0x06); 640 if (ret < 0) 641 return ret; 642 643 /* Set column start and end */ 644 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, 0x00, ssd130x->width - 1); 645 if (ret < 0) 646 return ret; 647 648 /* Set row start and end */ 649 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, 0x00, ssd130x->height - 1); 650 if (ret < 0) 651 return ret; 652 653 /* 654 * Horizontal Address Increment 655 * Normal order SA,SB,SC (e.g. RGB) 656 * COM Split Odd Even 657 * 256 color format 658 */ 659 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x20); 660 if (ret < 0) 661 return ret; 662 663 /* Set display start and offset */ 664 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_START, 0x00); 665 if (ret < 0) 666 return ret; 667 668 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_OFFSET, 0x00); 669 if (ret < 0) 670 return ret; 671 672 /* Set display mode normal */ 673 ret = ssd130x_write_cmd(ssd130x, 1, SSD133X_SET_DISPLAY_NORMAL); 674 if (ret < 0) 675 return ret; 676 677 /* Set multiplex ratio value */ 678 ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1); 679 if (ret < 0) 680 return ret; 681 682 /* Set master configuration */ 683 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CONFIG, 0x8e); 684 if (ret < 0) 685 return ret; 686 687 /* Set power mode */ 688 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_POWER_SAVE_MODE, 0x0b); 689 if (ret < 0) 690 return ret; 691 692 /* Set Phase 1 and 2 period */ 693 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_PHASES_PERIOD, 0x31); 694 if (ret < 0) 695 return ret; 696 697 /* Set clock divider */ 698 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_CLOCK_FREQ, 0xf0); 699 if (ret < 0) 700 return ret; 701 702 /* Set pre-charge A */ 703 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_A, 0x64); 704 if (ret < 0) 705 return ret; 706 707 /* Set pre-charge B */ 708 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_B, 0x78); 709 if (ret < 0) 710 return ret; 711 712 /* Set pre-charge C */ 713 ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_C, 0x64); 714 if (ret < 0) 715 return ret; 716 717 /* Set pre-charge level */ 718 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_PRECHARGE_VOLTAGE, 0x3a); 719 if (ret < 0) 720 return ret; 721 722 /* Set VCOMH voltage */ 723 ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_VCOMH_VOLTAGE, 0x3e); 724 if (ret < 0) 725 return ret; 726 727 return 0; 728 } 729 730 static int ssd130x_update_rect(struct ssd130x_device *ssd130x, 731 struct drm_rect *rect, u8 *buf, 732 u8 *data_array) 733 { 734 unsigned int x = rect->x1; 735 unsigned int y = rect->y1; 736 unsigned int width = drm_rect_width(rect); 737 unsigned int height = drm_rect_height(rect); 738 unsigned int line_length = DIV_ROUND_UP(width, 8); 739 unsigned int page_height = SSD130X_PAGE_HEIGHT; 740 unsigned int pages = DIV_ROUND_UP(height, page_height); 741 struct drm_device *drm = &ssd130x->drm; 742 u32 array_idx = 0; 743 int ret, i, j, k; 744 745 drm_WARN_ONCE(drm, y % page_height != 0, "y must be aligned to screen page\n"); 746 747 /* 748 * The screen is divided in pages, each having a height of 8 749 * pixels, and the width of the screen. When sending a byte of 750 * data to the controller, it gives the 8 bits for the current 751 * column. I.e, the first byte are the 8 bits of the first 752 * column, then the 8 bits for the second column, etc. 753 * 754 * 755 * Representation of the screen, assuming it is 5 bits 756 * wide. Each letter-number combination is a bit that controls 757 * one pixel. 758 * 759 * A0 A1 A2 A3 A4 760 * B0 B1 B2 B3 B4 761 * C0 C1 C2 C3 C4 762 * D0 D1 D2 D3 D4 763 * E0 E1 E2 E3 E4 764 * F0 F1 F2 F3 F4 765 * G0 G1 G2 G3 G4 766 * H0 H1 H2 H3 H4 767 * 768 * If you want to update this screen, you need to send 5 bytes: 769 * (1) A0 B0 C0 D0 E0 F0 G0 H0 770 * (2) A1 B1 C1 D1 E1 F1 G1 H1 771 * (3) A2 B2 C2 D2 E2 F2 G2 H2 772 * (4) A3 B3 C3 D3 E3 F3 G3 H3 773 * (5) A4 B4 C4 D4 E4 F4 G4 H4 774 */ 775 776 if (!ssd130x->page_address_mode) { 777 u8 page_start; 778 779 /* Set address range for horizontal addressing mode */ 780 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width); 781 if (ret < 0) 782 return ret; 783 784 page_start = ssd130x->page_offset + y / page_height; 785 ret = ssd130x_set_page_range(ssd130x, page_start, pages); 786 if (ret < 0) 787 return ret; 788 } 789 790 for (i = 0; i < pages; i++) { 791 int m = page_height; 792 793 /* Last page may be partial */ 794 if (page_height * (y / page_height + i + 1) > ssd130x->height) 795 m = ssd130x->height % page_height; 796 797 for (j = 0; j < width; j++) { 798 u8 data = 0; 799 800 for (k = 0; k < m; k++) { 801 u32 idx = (page_height * i + k) * line_length + j / 8; 802 u8 byte = buf[idx]; 803 u8 bit = (byte >> (j % 8)) & 1; 804 805 data |= bit << k; 806 } 807 data_array[array_idx++] = data; 808 } 809 810 /* 811 * In page addressing mode, the start address needs to be reset, 812 * and each page then needs to be written out separately. 813 */ 814 if (ssd130x->page_address_mode) { 815 ret = ssd130x_set_page_pos(ssd130x, 816 ssd130x->page_offset + i, 817 ssd130x->col_offset + x); 818 if (ret < 0) 819 return ret; 820 821 ret = ssd130x_write_data(ssd130x, data_array, width); 822 if (ret < 0) 823 return ret; 824 825 array_idx = 0; 826 } 827 } 828 829 /* Write out update in one go if we aren't using page addressing mode */ 830 if (!ssd130x->page_address_mode) 831 ret = ssd130x_write_data(ssd130x, data_array, width * pages); 832 833 return ret; 834 } 835 836 static int ssd132x_update_rect(struct ssd130x_device *ssd130x, 837 struct drm_rect *rect, u8 *buf, 838 u8 *data_array) 839 { 840 unsigned int x = rect->x1; 841 unsigned int y = rect->y1; 842 unsigned int segment_width = SSD132X_SEGMENT_WIDTH; 843 unsigned int width = drm_rect_width(rect); 844 unsigned int height = drm_rect_height(rect); 845 unsigned int columns = DIV_ROUND_UP(width, segment_width); 846 unsigned int rows = height; 847 struct drm_device *drm = &ssd130x->drm; 848 u32 array_idx = 0; 849 unsigned int i, j; 850 int ret; 851 852 drm_WARN_ONCE(drm, x % segment_width != 0, "x must be aligned to screen segment\n"); 853 854 /* 855 * The screen is divided in Segment and Common outputs, where 856 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 857 * the columns. 858 * 859 * Each Segment has a 4-bit pixel and each Common output has a 860 * row of pixels. When using the (default) horizontal address 861 * increment mode, each byte of data sent to the controller has 862 * two Segments (e.g: SEG0 and SEG1) that are stored in the lower 863 * and higher nibbles of a single byte representing one column. 864 * That is, the first byte are SEG0 (D0[3:0]) and SEG1 (D0[7:4]), 865 * the second byte are SEG2 (D1[3:0]) and SEG3 (D1[7:4]) and so on. 866 */ 867 868 /* Set column start and end */ 869 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, x / segment_width, columns - 1); 870 if (ret < 0) 871 return ret; 872 873 /* Set row start and end */ 874 ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, y, rows - 1); 875 if (ret < 0) 876 return ret; 877 878 for (i = 0; i < height; i++) { 879 /* Process pair of pixels and combine them into a single byte */ 880 for (j = 0; j < width; j += segment_width) { 881 u8 n1 = buf[i * width + j]; 882 u8 n2 = buf[i * width + j + 1]; 883 884 data_array[array_idx++] = (n2 & 0xf0) | (n1 >> 4); 885 } 886 } 887 888 /* Write out update in one go since horizontal addressing mode is used */ 889 ret = ssd130x_write_data(ssd130x, data_array, columns * rows); 890 891 return ret; 892 } 893 894 static int ssd133x_update_rect(struct ssd130x_device *ssd130x, 895 struct drm_rect *rect, u8 *data_array, 896 unsigned int pitch) 897 { 898 unsigned int x = rect->x1; 899 unsigned int y = rect->y1; 900 unsigned int columns = drm_rect_width(rect); 901 unsigned int rows = drm_rect_height(rect); 902 int ret; 903 904 /* 905 * The screen is divided in Segment and Common outputs, where 906 * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are 907 * the columns. 908 * 909 * Each Segment has a 8-bit pixel and each Common output has a 910 * row of pixels. When using the (default) horizontal address 911 * increment mode, each byte of data sent to the controller has 912 * a Segment (e.g: SEG0). 913 * 914 * When using the 256 color depth format, each pixel contains 3 915 * sub-pixels for color A, B and C. These have 3 bit, 3 bit and 916 * 2 bits respectively. 917 */ 918 919 /* Set column start and end */ 920 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, x, columns - 1); 921 if (ret < 0) 922 return ret; 923 924 /* Set row start and end */ 925 ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, y, rows - 1); 926 if (ret < 0) 927 return ret; 928 929 /* Write out update in one go since horizontal addressing mode is used */ 930 ret = ssd130x_write_data(ssd130x, data_array, pitch * rows); 931 932 return ret; 933 } 934 935 static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 936 { 937 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 938 unsigned int width = ssd130x->width; 939 int ret, i; 940 941 if (!ssd130x->page_address_mode) { 942 memset(data_array, 0, width * pages); 943 944 /* Set address range for horizontal addressing mode */ 945 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset, width); 946 if (ret < 0) 947 return; 948 949 ret = ssd130x_set_page_range(ssd130x, ssd130x->page_offset, pages); 950 if (ret < 0) 951 return; 952 953 /* Write out update in one go if we aren't using page addressing mode */ 954 ssd130x_write_data(ssd130x, data_array, width * pages); 955 } else { 956 /* 957 * In page addressing mode, the start address needs to be reset, 958 * and each page then needs to be written out separately. 959 */ 960 memset(data_array, 0, width); 961 962 for (i = 0; i < pages; i++) { 963 ret = ssd130x_set_page_pos(ssd130x, 964 ssd130x->page_offset + i, 965 ssd130x->col_offset); 966 if (ret < 0) 967 return; 968 969 ret = ssd130x_write_data(ssd130x, data_array, width); 970 if (ret < 0) 971 return; 972 } 973 } 974 } 975 976 static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 977 { 978 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 979 unsigned int height = ssd130x->height; 980 981 memset(data_array, 0, columns * height); 982 983 /* Write out update in one go since horizontal addressing mode is used */ 984 ssd130x_write_data(ssd130x, data_array, columns * height); 985 } 986 987 static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array) 988 { 989 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 990 unsigned int pitch; 991 992 if (!fi) 993 return; 994 995 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 996 997 memset(data_array, 0, pitch * ssd130x->height); 998 999 /* Write out update in one go since horizontal addressing mode is used */ 1000 ssd130x_write_data(ssd130x, data_array, pitch * ssd130x->height); 1001 } 1002 1003 static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb, 1004 const struct iosys_map *vmap, 1005 struct drm_rect *rect, 1006 u8 *buf, u8 *data_array, 1007 struct drm_format_conv_state *fmtcnv_state) 1008 { 1009 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 1010 struct iosys_map dst; 1011 unsigned int dst_pitch; 1012 int ret = 0; 1013 1014 /* Align y to display page boundaries */ 1015 rect->y1 = round_down(rect->y1, SSD130X_PAGE_HEIGHT); 1016 rect->y2 = min_t(unsigned int, round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height); 1017 1018 dst_pitch = DIV_ROUND_UP(drm_rect_width(rect), 8); 1019 1020 iosys_map_set_vaddr(&dst, buf); 1021 drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 1022 1023 ssd130x_update_rect(ssd130x, rect, buf, data_array); 1024 1025 return ret; 1026 } 1027 1028 static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb, 1029 const struct iosys_map *vmap, 1030 struct drm_rect *rect, u8 *buf, 1031 u8 *data_array, 1032 struct drm_format_conv_state *fmtcnv_state) 1033 { 1034 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 1035 unsigned int dst_pitch; 1036 struct iosys_map dst; 1037 int ret = 0; 1038 1039 /* Align x to display segment boundaries */ 1040 rect->x1 = round_down(rect->x1, SSD132X_SEGMENT_WIDTH); 1041 rect->x2 = min_t(unsigned int, round_up(rect->x2, SSD132X_SEGMENT_WIDTH), 1042 ssd130x->width); 1043 1044 dst_pitch = drm_rect_width(rect); 1045 1046 iosys_map_set_vaddr(&dst, buf); 1047 drm_fb_xrgb8888_to_gray8(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 1048 1049 ssd132x_update_rect(ssd130x, rect, buf, data_array); 1050 1051 return ret; 1052 } 1053 1054 static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb, 1055 const struct iosys_map *vmap, 1056 struct drm_rect *rect, u8 *data_array, 1057 struct drm_format_conv_state *fmtcnv_state) 1058 { 1059 struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev); 1060 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 1061 unsigned int dst_pitch; 1062 struct iosys_map dst; 1063 int ret = 0; 1064 1065 if (!fi) 1066 return -EINVAL; 1067 1068 dst_pitch = drm_format_info_min_pitch(fi, 0, drm_rect_width(rect)); 1069 1070 iosys_map_set_vaddr(&dst, data_array); 1071 drm_fb_xrgb8888_to_rgb332(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state); 1072 1073 ssd133x_update_rect(ssd130x, rect, data_array, dst_pitch); 1074 1075 return ret; 1076 } 1077 1078 static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane, 1079 struct drm_atomic_state *state) 1080 { 1081 struct drm_device *drm = plane->dev; 1082 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1083 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1084 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 1085 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 1086 struct drm_crtc *crtc = plane_state->crtc; 1087 struct drm_crtc_state *crtc_state = NULL; 1088 const struct drm_format_info *fi; 1089 unsigned int pitch; 1090 int ret; 1091 1092 if (crtc) 1093 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1094 1095 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1096 DRM_PLANE_NO_SCALING, 1097 DRM_PLANE_NO_SCALING, 1098 false, false); 1099 if (ret) 1100 return ret; 1101 else if (!plane_state->visible) 1102 return 0; 1103 1104 fi = drm_format_info(DRM_FORMAT_R1); 1105 if (!fi) 1106 return -EINVAL; 1107 1108 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1109 1110 if (plane_state->fb->format != fi) { 1111 void *buf; 1112 1113 /* format conversion necessary; reserve buffer */ 1114 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1115 pitch, GFP_KERNEL); 1116 if (!buf) 1117 return -ENOMEM; 1118 } 1119 1120 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1121 if (!ssd130x_state->buffer) 1122 return -ENOMEM; 1123 1124 return 0; 1125 } 1126 1127 static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane, 1128 struct drm_atomic_state *state) 1129 { 1130 struct drm_device *drm = plane->dev; 1131 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1132 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1133 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state); 1134 struct drm_shadow_plane_state *shadow_plane_state = &ssd130x_state->base; 1135 struct drm_crtc *crtc = plane_state->crtc; 1136 struct drm_crtc_state *crtc_state = NULL; 1137 const struct drm_format_info *fi; 1138 unsigned int pitch; 1139 int ret; 1140 1141 if (crtc) 1142 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1143 1144 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1145 DRM_PLANE_NO_SCALING, 1146 DRM_PLANE_NO_SCALING, 1147 false, false); 1148 if (ret) 1149 return ret; 1150 else if (!plane_state->visible) 1151 return 0; 1152 1153 fi = drm_format_info(DRM_FORMAT_R8); 1154 if (!fi) 1155 return -EINVAL; 1156 1157 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1158 1159 if (plane_state->fb->format != fi) { 1160 void *buf; 1161 1162 /* format conversion necessary; reserve buffer */ 1163 buf = drm_format_conv_state_reserve(&shadow_plane_state->fmtcnv_state, 1164 pitch, GFP_KERNEL); 1165 if (!buf) 1166 return -ENOMEM; 1167 } 1168 1169 ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL); 1170 if (!ssd130x_state->buffer) 1171 return -ENOMEM; 1172 1173 return 0; 1174 } 1175 1176 static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane, 1177 struct drm_atomic_state *state) 1178 { 1179 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1180 struct drm_crtc *crtc = plane_state->crtc; 1181 struct drm_crtc_state *crtc_state = NULL; 1182 int ret; 1183 1184 if (crtc) 1185 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1186 1187 ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state, 1188 DRM_PLANE_NO_SCALING, 1189 DRM_PLANE_NO_SCALING, 1190 false, false); 1191 if (ret) 1192 return ret; 1193 else if (!plane_state->visible) 1194 return 0; 1195 1196 return 0; 1197 } 1198 1199 static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane, 1200 struct drm_atomic_state *state) 1201 { 1202 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1203 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1204 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1205 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1206 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1207 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1208 struct drm_framebuffer *fb = plane_state->fb; 1209 struct drm_atomic_helper_damage_iter iter; 1210 struct drm_device *drm = plane->dev; 1211 struct drm_rect dst_clip; 1212 struct drm_rect damage; 1213 int idx; 1214 1215 if (!drm_dev_enter(drm, &idx)) 1216 return; 1217 1218 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1219 goto out_drm_dev_exit; 1220 1221 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1222 drm_atomic_for_each_plane_damage(&iter, &damage) { 1223 dst_clip = plane_state->dst; 1224 1225 if (!drm_rect_intersect(&dst_clip, &damage)) 1226 continue; 1227 1228 ssd130x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1229 ssd130x_plane_state->buffer, 1230 ssd130x_crtc_state->data_array, 1231 &shadow_plane_state->fmtcnv_state); 1232 } 1233 1234 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1235 1236 out_drm_dev_exit: 1237 drm_dev_exit(idx); 1238 } 1239 1240 static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane, 1241 struct drm_atomic_state *state) 1242 { 1243 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1244 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1245 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1246 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1247 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1248 struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state); 1249 struct drm_framebuffer *fb = plane_state->fb; 1250 struct drm_atomic_helper_damage_iter iter; 1251 struct drm_device *drm = plane->dev; 1252 struct drm_rect dst_clip; 1253 struct drm_rect damage; 1254 int idx; 1255 1256 if (!drm_dev_enter(drm, &idx)) 1257 return; 1258 1259 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1260 goto out_drm_dev_exit; 1261 1262 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1263 drm_atomic_for_each_plane_damage(&iter, &damage) { 1264 dst_clip = plane_state->dst; 1265 1266 if (!drm_rect_intersect(&dst_clip, &damage)) 1267 continue; 1268 1269 ssd132x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1270 ssd130x_plane_state->buffer, 1271 ssd130x_crtc_state->data_array, 1272 &shadow_plane_state->fmtcnv_state); 1273 } 1274 1275 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1276 1277 out_drm_dev_exit: 1278 drm_dev_exit(idx); 1279 } 1280 1281 static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane, 1282 struct drm_atomic_state *state) 1283 { 1284 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1285 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 1286 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 1287 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1288 struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1289 struct drm_framebuffer *fb = plane_state->fb; 1290 struct drm_atomic_helper_damage_iter iter; 1291 struct drm_device *drm = plane->dev; 1292 struct drm_rect dst_clip; 1293 struct drm_rect damage; 1294 int idx; 1295 1296 if (!drm_dev_enter(drm, &idx)) 1297 return; 1298 1299 if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE)) 1300 goto out_drm_dev_exit; 1301 1302 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 1303 drm_atomic_for_each_plane_damage(&iter, &damage) { 1304 dst_clip = plane_state->dst; 1305 1306 if (!drm_rect_intersect(&dst_clip, &damage)) 1307 continue; 1308 1309 ssd133x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip, 1310 ssd130x_crtc_state->data_array, 1311 &shadow_plane_state->fmtcnv_state); 1312 } 1313 1314 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 1315 1316 out_drm_dev_exit: 1317 drm_dev_exit(idx); 1318 } 1319 1320 static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane, 1321 struct drm_atomic_state *state) 1322 { 1323 struct drm_device *drm = plane->dev; 1324 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1325 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1326 struct drm_crtc_state *crtc_state; 1327 struct ssd130x_crtc_state *ssd130x_crtc_state; 1328 int idx; 1329 1330 if (!plane_state->crtc) 1331 return; 1332 1333 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1334 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1335 1336 if (!drm_dev_enter(drm, &idx)) 1337 return; 1338 1339 ssd130x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1340 1341 drm_dev_exit(idx); 1342 } 1343 1344 static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane, 1345 struct drm_atomic_state *state) 1346 { 1347 struct drm_device *drm = plane->dev; 1348 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1349 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1350 struct drm_crtc_state *crtc_state; 1351 struct ssd130x_crtc_state *ssd130x_crtc_state; 1352 int idx; 1353 1354 if (!plane_state->crtc) 1355 return; 1356 1357 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1358 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1359 1360 if (!drm_dev_enter(drm, &idx)) 1361 return; 1362 1363 ssd132x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1364 1365 drm_dev_exit(idx); 1366 } 1367 1368 static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane, 1369 struct drm_atomic_state *state) 1370 { 1371 struct drm_device *drm = plane->dev; 1372 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1373 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 1374 struct drm_crtc_state *crtc_state; 1375 struct ssd130x_crtc_state *ssd130x_crtc_state; 1376 int idx; 1377 1378 if (!plane_state->crtc) 1379 return; 1380 1381 crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); 1382 ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state); 1383 1384 if (!drm_dev_enter(drm, &idx)) 1385 return; 1386 1387 ssd133x_clear_screen(ssd130x, ssd130x_crtc_state->data_array); 1388 1389 drm_dev_exit(idx); 1390 } 1391 1392 /* Called during init to allocate the plane's atomic state. */ 1393 static void ssd130x_primary_plane_reset(struct drm_plane *plane) 1394 { 1395 struct ssd130x_plane_state *ssd130x_state; 1396 1397 drm_WARN_ON_ONCE(plane->dev, plane->state); 1398 1399 ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL); 1400 if (!ssd130x_state) 1401 return; 1402 1403 __drm_gem_reset_shadow_plane(plane, &ssd130x_state->base); 1404 } 1405 1406 static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane) 1407 { 1408 struct drm_shadow_plane_state *new_shadow_plane_state; 1409 struct ssd130x_plane_state *old_ssd130x_state; 1410 struct ssd130x_plane_state *ssd130x_state; 1411 1412 if (drm_WARN_ON_ONCE(plane->dev, !plane->state)) 1413 return NULL; 1414 1415 old_ssd130x_state = to_ssd130x_plane_state(plane->state); 1416 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1417 if (!ssd130x_state) 1418 return NULL; 1419 1420 /* The buffer is not duplicated and is allocated in .atomic_check */ 1421 ssd130x_state->buffer = NULL; 1422 1423 new_shadow_plane_state = &ssd130x_state->base; 1424 1425 __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state); 1426 1427 return &new_shadow_plane_state->base; 1428 } 1429 1430 static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane, 1431 struct drm_plane_state *state) 1432 { 1433 struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state); 1434 1435 kfree(ssd130x_state->buffer); 1436 1437 __drm_gem_destroy_shadow_plane_state(&ssd130x_state->base); 1438 1439 kfree(ssd130x_state); 1440 } 1441 1442 static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = { 1443 [SSD130X_FAMILY] = { 1444 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1445 .atomic_check = ssd130x_primary_plane_atomic_check, 1446 .atomic_update = ssd130x_primary_plane_atomic_update, 1447 .atomic_disable = ssd130x_primary_plane_atomic_disable, 1448 }, 1449 [SSD132X_FAMILY] = { 1450 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1451 .atomic_check = ssd132x_primary_plane_atomic_check, 1452 .atomic_update = ssd132x_primary_plane_atomic_update, 1453 .atomic_disable = ssd132x_primary_plane_atomic_disable, 1454 }, 1455 [SSD133X_FAMILY] = { 1456 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 1457 .atomic_check = ssd133x_primary_plane_atomic_check, 1458 .atomic_update = ssd133x_primary_plane_atomic_update, 1459 .atomic_disable = ssd133x_primary_plane_atomic_disable, 1460 } 1461 }; 1462 1463 static const struct drm_plane_funcs ssd130x_primary_plane_funcs = { 1464 .update_plane = drm_atomic_helper_update_plane, 1465 .disable_plane = drm_atomic_helper_disable_plane, 1466 .reset = ssd130x_primary_plane_reset, 1467 .atomic_duplicate_state = ssd130x_primary_plane_duplicate_state, 1468 .atomic_destroy_state = ssd130x_primary_plane_destroy_state, 1469 .destroy = drm_plane_cleanup, 1470 }; 1471 1472 static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc, 1473 const struct drm_display_mode *mode) 1474 { 1475 struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev); 1476 1477 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &ssd130x->mode); 1478 } 1479 1480 static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc, 1481 struct drm_atomic_state *state) 1482 { 1483 struct drm_device *drm = crtc->dev; 1484 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1485 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1486 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1487 unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT); 1488 int ret; 1489 1490 ret = drm_crtc_helper_atomic_check(crtc, state); 1491 if (ret) 1492 return ret; 1493 1494 ssd130x_state->data_array = kmalloc_array(ssd130x->width, pages, GFP_KERNEL); 1495 if (!ssd130x_state->data_array) 1496 return -ENOMEM; 1497 1498 return 0; 1499 } 1500 1501 static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc, 1502 struct drm_atomic_state *state) 1503 { 1504 struct drm_device *drm = crtc->dev; 1505 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1506 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1507 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1508 unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH); 1509 int ret; 1510 1511 ret = drm_crtc_helper_atomic_check(crtc, state); 1512 if (ret) 1513 return ret; 1514 1515 ssd130x_state->data_array = kmalloc_array(columns, ssd130x->height, GFP_KERNEL); 1516 if (!ssd130x_state->data_array) 1517 return -ENOMEM; 1518 1519 return 0; 1520 } 1521 1522 static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc, 1523 struct drm_atomic_state *state) 1524 { 1525 struct drm_device *drm = crtc->dev; 1526 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1527 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 1528 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state); 1529 const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332); 1530 unsigned int pitch; 1531 int ret; 1532 1533 if (!fi) 1534 return -EINVAL; 1535 1536 ret = drm_crtc_helper_atomic_check(crtc, state); 1537 if (ret) 1538 return ret; 1539 1540 pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width); 1541 1542 ssd130x_state->data_array = kmalloc_array(pitch, ssd130x->height, GFP_KERNEL); 1543 if (!ssd130x_state->data_array) 1544 return -ENOMEM; 1545 1546 return 0; 1547 } 1548 1549 /* Called during init to allocate the CRTC's atomic state. */ 1550 static void ssd130x_crtc_reset(struct drm_crtc *crtc) 1551 { 1552 struct ssd130x_crtc_state *ssd130x_state; 1553 1554 drm_WARN_ON_ONCE(crtc->dev, crtc->state); 1555 1556 ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL); 1557 if (!ssd130x_state) 1558 return; 1559 1560 __drm_atomic_helper_crtc_reset(crtc, &ssd130x_state->base); 1561 } 1562 1563 static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc) 1564 { 1565 struct ssd130x_crtc_state *old_ssd130x_state; 1566 struct ssd130x_crtc_state *ssd130x_state; 1567 1568 if (drm_WARN_ON_ONCE(crtc->dev, !crtc->state)) 1569 return NULL; 1570 1571 old_ssd130x_state = to_ssd130x_crtc_state(crtc->state); 1572 ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL); 1573 if (!ssd130x_state) 1574 return NULL; 1575 1576 /* The buffer is not duplicated and is allocated in .atomic_check */ 1577 ssd130x_state->data_array = NULL; 1578 1579 __drm_atomic_helper_crtc_duplicate_state(crtc, &ssd130x_state->base); 1580 1581 return &ssd130x_state->base; 1582 } 1583 1584 static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc, 1585 struct drm_crtc_state *state) 1586 { 1587 struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state); 1588 1589 kfree(ssd130x_state->data_array); 1590 1591 __drm_atomic_helper_crtc_destroy_state(state); 1592 1593 kfree(ssd130x_state); 1594 } 1595 1596 /* 1597 * The CRTC is always enabled. Screen updates are performed by 1598 * the primary plane's atomic_update function. Disabling clears 1599 * the screen in the primary plane's atomic_disable function. 1600 */ 1601 static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = { 1602 [SSD130X_FAMILY] = { 1603 .mode_valid = ssd130x_crtc_mode_valid, 1604 .atomic_check = ssd130x_crtc_atomic_check, 1605 }, 1606 [SSD132X_FAMILY] = { 1607 .mode_valid = ssd130x_crtc_mode_valid, 1608 .atomic_check = ssd132x_crtc_atomic_check, 1609 }, 1610 [SSD133X_FAMILY] = { 1611 .mode_valid = ssd130x_crtc_mode_valid, 1612 .atomic_check = ssd133x_crtc_atomic_check, 1613 }, 1614 }; 1615 1616 static const struct drm_crtc_funcs ssd130x_crtc_funcs = { 1617 .reset = ssd130x_crtc_reset, 1618 .destroy = drm_crtc_cleanup, 1619 .set_config = drm_atomic_helper_set_config, 1620 .page_flip = drm_atomic_helper_page_flip, 1621 .atomic_duplicate_state = ssd130x_crtc_duplicate_state, 1622 .atomic_destroy_state = ssd130x_crtc_destroy_state, 1623 }; 1624 1625 static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder, 1626 struct drm_atomic_state *state) 1627 { 1628 struct drm_device *drm = encoder->dev; 1629 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1630 int ret; 1631 1632 ret = ssd130x_power_on(ssd130x); 1633 if (ret) 1634 return; 1635 1636 ret = ssd130x_init(ssd130x); 1637 if (ret) 1638 goto power_off; 1639 1640 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1641 1642 backlight_enable(ssd130x->bl_dev); 1643 1644 return; 1645 1646 power_off: 1647 ssd130x_power_off(ssd130x); 1648 return; 1649 } 1650 1651 static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder, 1652 struct drm_atomic_state *state) 1653 { 1654 struct drm_device *drm = encoder->dev; 1655 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1656 int ret; 1657 1658 ret = ssd130x_power_on(ssd130x); 1659 if (ret) 1660 return; 1661 1662 ret = ssd132x_init(ssd130x); 1663 if (ret) 1664 goto power_off; 1665 1666 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1667 1668 backlight_enable(ssd130x->bl_dev); 1669 1670 return; 1671 1672 power_off: 1673 ssd130x_power_off(ssd130x); 1674 } 1675 1676 static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder, 1677 struct drm_atomic_state *state) 1678 { 1679 struct drm_device *drm = encoder->dev; 1680 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1681 int ret; 1682 1683 ret = ssd130x_power_on(ssd130x); 1684 if (ret) 1685 return; 1686 1687 ret = ssd133x_init(ssd130x); 1688 if (ret) 1689 goto power_off; 1690 1691 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON); 1692 1693 backlight_enable(ssd130x->bl_dev); 1694 1695 return; 1696 1697 power_off: 1698 ssd130x_power_off(ssd130x); 1699 } 1700 1701 static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder, 1702 struct drm_atomic_state *state) 1703 { 1704 struct drm_device *drm = encoder->dev; 1705 struct ssd130x_device *ssd130x = drm_to_ssd130x(drm); 1706 1707 backlight_disable(ssd130x->bl_dev); 1708 1709 ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_OFF); 1710 1711 ssd130x_power_off(ssd130x); 1712 } 1713 1714 static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = { 1715 [SSD130X_FAMILY] = { 1716 .atomic_enable = ssd130x_encoder_atomic_enable, 1717 .atomic_disable = ssd130x_encoder_atomic_disable, 1718 }, 1719 [SSD132X_FAMILY] = { 1720 .atomic_enable = ssd132x_encoder_atomic_enable, 1721 .atomic_disable = ssd130x_encoder_atomic_disable, 1722 }, 1723 [SSD133X_FAMILY] = { 1724 .atomic_enable = ssd133x_encoder_atomic_enable, 1725 .atomic_disable = ssd130x_encoder_atomic_disable, 1726 } 1727 }; 1728 1729 static const struct drm_encoder_funcs ssd130x_encoder_funcs = { 1730 .destroy = drm_encoder_cleanup, 1731 }; 1732 1733 static int ssd130x_connector_get_modes(struct drm_connector *connector) 1734 { 1735 struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev); 1736 1737 return drm_connector_helper_get_modes_fixed(connector, &ssd130x->mode); 1738 } 1739 1740 static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = { 1741 .get_modes = ssd130x_connector_get_modes, 1742 }; 1743 1744 static const struct drm_connector_funcs ssd130x_connector_funcs = { 1745 .reset = drm_atomic_helper_connector_reset, 1746 .fill_modes = drm_helper_probe_single_connector_modes, 1747 .destroy = drm_connector_cleanup, 1748 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1749 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1750 }; 1751 1752 static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = { 1753 .fb_create = drm_gem_fb_create_with_dirty, 1754 .atomic_check = drm_atomic_helper_check, 1755 .atomic_commit = drm_atomic_helper_commit, 1756 }; 1757 1758 static const uint32_t ssd130x_formats[] = { 1759 DRM_FORMAT_XRGB8888, 1760 }; 1761 1762 DEFINE_DRM_GEM_FOPS(ssd130x_fops); 1763 1764 static const struct drm_driver ssd130x_drm_driver = { 1765 DRM_GEM_SHMEM_DRIVER_OPS, 1766 DRM_FBDEV_SHMEM_DRIVER_OPS, 1767 .name = DRIVER_NAME, 1768 .desc = DRIVER_DESC, 1769 .major = DRIVER_MAJOR, 1770 .minor = DRIVER_MINOR, 1771 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1772 .fops = &ssd130x_fops, 1773 }; 1774 1775 static int ssd130x_update_bl(struct backlight_device *bdev) 1776 { 1777 struct ssd130x_device *ssd130x = bl_get_data(bdev); 1778 int brightness = backlight_get_brightness(bdev); 1779 int ret; 1780 1781 ssd130x->contrast = brightness; 1782 1783 ret = ssd130x_write_cmd(ssd130x, 1, SSD13XX_CONTRAST); 1784 if (ret < 0) 1785 return ret; 1786 1787 ret = ssd130x_write_cmd(ssd130x, 1, ssd130x->contrast); 1788 if (ret < 0) 1789 return ret; 1790 1791 return 0; 1792 } 1793 1794 static const struct backlight_ops ssd130xfb_bl_ops = { 1795 .update_status = ssd130x_update_bl, 1796 }; 1797 1798 static void ssd130x_parse_properties(struct ssd130x_device *ssd130x) 1799 { 1800 struct device *dev = ssd130x->dev; 1801 1802 if (device_property_read_u32(dev, "solomon,width", &ssd130x->width)) 1803 ssd130x->width = ssd130x->device_info->default_width; 1804 1805 if (device_property_read_u32(dev, "solomon,height", &ssd130x->height)) 1806 ssd130x->height = ssd130x->device_info->default_height; 1807 1808 if (device_property_read_u32(dev, "solomon,page-offset", &ssd130x->page_offset)) 1809 ssd130x->page_offset = 1; 1810 1811 if (device_property_read_u32(dev, "solomon,col-offset", &ssd130x->col_offset)) 1812 ssd130x->col_offset = 0; 1813 1814 if (device_property_read_u32(dev, "solomon,com-offset", &ssd130x->com_offset)) 1815 ssd130x->com_offset = 0; 1816 1817 if (device_property_read_u32(dev, "solomon,prechargep1", &ssd130x->prechargep1)) 1818 ssd130x->prechargep1 = 2; 1819 1820 if (device_property_read_u32(dev, "solomon,prechargep2", &ssd130x->prechargep2)) 1821 ssd130x->prechargep2 = 2; 1822 1823 if (!device_property_read_u8_array(dev, "solomon,lookup-table", 1824 ssd130x->lookup_table, 1825 ARRAY_SIZE(ssd130x->lookup_table))) 1826 ssd130x->lookup_table_set = 1; 1827 1828 ssd130x->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap"); 1829 ssd130x->com_seq = device_property_read_bool(dev, "solomon,com-seq"); 1830 ssd130x->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap"); 1831 ssd130x->com_invdir = device_property_read_bool(dev, "solomon,com-invdir"); 1832 ssd130x->area_color_enable = 1833 device_property_read_bool(dev, "solomon,area-color-enable"); 1834 ssd130x->low_power = device_property_read_bool(dev, "solomon,low-power"); 1835 1836 ssd130x->contrast = 127; 1837 ssd130x->vcomh = ssd130x->device_info->default_vcomh; 1838 1839 /* Setup display timing */ 1840 if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div)) 1841 ssd130x->dclk_div = ssd130x->device_info->default_dclk_div; 1842 if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq)) 1843 ssd130x->dclk_frq = ssd130x->device_info->default_dclk_frq; 1844 } 1845 1846 static int ssd130x_init_modeset(struct ssd130x_device *ssd130x) 1847 { 1848 enum ssd130x_family_ids family_id = ssd130x->device_info->family_id; 1849 struct drm_display_mode *mode = &ssd130x->mode; 1850 struct device *dev = ssd130x->dev; 1851 struct drm_device *drm = &ssd130x->drm; 1852 unsigned long max_width, max_height; 1853 struct drm_plane *primary_plane; 1854 struct drm_crtc *crtc; 1855 struct drm_encoder *encoder; 1856 struct drm_connector *connector; 1857 int ret; 1858 1859 /* 1860 * Modesetting 1861 */ 1862 1863 ret = drmm_mode_config_init(drm); 1864 if (ret) { 1865 dev_err(dev, "DRM mode config init failed: %d\n", ret); 1866 return ret; 1867 } 1868 1869 mode->type = DRM_MODE_TYPE_DRIVER; 1870 mode->clock = 1; 1871 mode->hdisplay = ssd130x->width; 1872 mode->htotal = ssd130x->width; 1873 mode->hsync_start = ssd130x->width; 1874 mode->hsync_end = ssd130x->width; 1875 mode->vdisplay = ssd130x->height; 1876 mode->vtotal = ssd130x->height; 1877 mode->vsync_start = ssd130x->height; 1878 mode->vsync_end = ssd130x->height; 1879 mode->width_mm = 27; 1880 mode->height_mm = 27; 1881 1882 max_width = max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH); 1883 max_height = max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT); 1884 1885 drm->mode_config.min_width = mode->hdisplay; 1886 drm->mode_config.max_width = max_width; 1887 drm->mode_config.min_height = mode->vdisplay; 1888 drm->mode_config.max_height = max_height; 1889 drm->mode_config.preferred_depth = 24; 1890 drm->mode_config.funcs = &ssd130x_mode_config_funcs; 1891 1892 /* Primary plane */ 1893 1894 primary_plane = &ssd130x->primary_plane; 1895 ret = drm_universal_plane_init(drm, primary_plane, 0, &ssd130x_primary_plane_funcs, 1896 ssd130x_formats, ARRAY_SIZE(ssd130x_formats), 1897 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1898 if (ret) { 1899 dev_err(dev, "DRM primary plane init failed: %d\n", ret); 1900 return ret; 1901 } 1902 1903 drm_plane_helper_add(primary_plane, &ssd130x_primary_plane_helper_funcs[family_id]); 1904 1905 drm_plane_enable_fb_damage_clips(primary_plane); 1906 1907 /* CRTC */ 1908 1909 crtc = &ssd130x->crtc; 1910 ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1911 &ssd130x_crtc_funcs, NULL); 1912 if (ret) { 1913 dev_err(dev, "DRM crtc init failed: %d\n", ret); 1914 return ret; 1915 } 1916 1917 drm_crtc_helper_add(crtc, &ssd130x_crtc_helper_funcs[family_id]); 1918 1919 /* Encoder */ 1920 1921 encoder = &ssd130x->encoder; 1922 ret = drm_encoder_init(drm, encoder, &ssd130x_encoder_funcs, 1923 DRM_MODE_ENCODER_NONE, NULL); 1924 if (ret) { 1925 dev_err(dev, "DRM encoder init failed: %d\n", ret); 1926 return ret; 1927 } 1928 1929 drm_encoder_helper_add(encoder, &ssd130x_encoder_helper_funcs[family_id]); 1930 1931 encoder->possible_crtcs = drm_crtc_mask(crtc); 1932 1933 /* Connector */ 1934 1935 connector = &ssd130x->connector; 1936 ret = drm_connector_init(drm, connector, &ssd130x_connector_funcs, 1937 DRM_MODE_CONNECTOR_Unknown); 1938 if (ret) { 1939 dev_err(dev, "DRM connector init failed: %d\n", ret); 1940 return ret; 1941 } 1942 1943 drm_connector_helper_add(connector, &ssd130x_connector_helper_funcs); 1944 1945 ret = drm_connector_attach_encoder(connector, encoder); 1946 if (ret) { 1947 dev_err(dev, "DRM attach connector to encoder failed: %d\n", ret); 1948 return ret; 1949 } 1950 1951 drm_mode_config_reset(drm); 1952 1953 return 0; 1954 } 1955 1956 static int ssd130x_get_resources(struct ssd130x_device *ssd130x) 1957 { 1958 struct device *dev = ssd130x->dev; 1959 1960 ssd130x->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1961 if (IS_ERR(ssd130x->reset)) 1962 return dev_err_probe(dev, PTR_ERR(ssd130x->reset), 1963 "Failed to get reset gpio\n"); 1964 1965 ssd130x->vcc_reg = devm_regulator_get(dev, "vcc"); 1966 if (IS_ERR(ssd130x->vcc_reg)) 1967 return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg), 1968 "Failed to get VCC regulator\n"); 1969 1970 return 0; 1971 } 1972 1973 struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap) 1974 { 1975 struct ssd130x_device *ssd130x; 1976 struct backlight_device *bl; 1977 struct drm_device *drm; 1978 int ret; 1979 1980 ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver, 1981 struct ssd130x_device, drm); 1982 if (IS_ERR(ssd130x)) 1983 return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x), 1984 "Failed to allocate DRM device\n")); 1985 1986 drm = &ssd130x->drm; 1987 1988 ssd130x->dev = dev; 1989 ssd130x->regmap = regmap; 1990 ssd130x->device_info = device_get_match_data(dev); 1991 1992 if (ssd130x->device_info->page_mode_only) 1993 ssd130x->page_address_mode = 1; 1994 1995 ssd130x_parse_properties(ssd130x); 1996 1997 ret = ssd130x_get_resources(ssd130x); 1998 if (ret) 1999 return ERR_PTR(ret); 2000 2001 bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x, 2002 &ssd130xfb_bl_ops, NULL); 2003 if (IS_ERR(bl)) 2004 return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl), 2005 "Unable to register backlight device\n")); 2006 2007 bl->props.brightness = ssd130x->contrast; 2008 bl->props.max_brightness = MAX_CONTRAST; 2009 ssd130x->bl_dev = bl; 2010 2011 ret = ssd130x_init_modeset(ssd130x); 2012 if (ret) 2013 return ERR_PTR(ret); 2014 2015 ret = drm_dev_register(drm, 0); 2016 if (ret) 2017 return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n")); 2018 2019 drm_client_setup(drm, NULL); 2020 2021 return ssd130x; 2022 } 2023 EXPORT_SYMBOL_GPL(ssd130x_probe); 2024 2025 void ssd130x_remove(struct ssd130x_device *ssd130x) 2026 { 2027 drm_dev_unplug(&ssd130x->drm); 2028 drm_atomic_helper_shutdown(&ssd130x->drm); 2029 } 2030 EXPORT_SYMBOL_GPL(ssd130x_remove); 2031 2032 void ssd130x_shutdown(struct ssd130x_device *ssd130x) 2033 { 2034 drm_atomic_helper_shutdown(&ssd130x->drm); 2035 } 2036 EXPORT_SYMBOL_GPL(ssd130x_shutdown); 2037 2038 MODULE_DESCRIPTION(DRIVER_DESC); 2039 MODULE_AUTHOR("Javier Martinez Canillas <javierm@redhat.com>"); 2040 MODULE_LICENSE("GPL v2"); 2041