1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H 8 #define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H 9 10 /* CRU-->SOFTRST_CON00 */ 11 #define SRST_NCOREPORESET0_AC 0 12 #define SRST_NCOREPORESET1_AC 1 13 #define SRST_NCOREPORESET2_AC 2 14 #define SRST_NCORESET0_AC 3 15 #define SRST_NCORESET1_AC 4 16 #define SRST_NCORESET2_AC 5 17 #define SRST_NL2RESET_AC 6 18 #define SRST_A_CORE_BIU_AC 7 19 #define SRST_H_M0_AC 8 20 21 /* CRU-->SOFTRST_CON02 */ 22 #define SRST_NDBGRESET 9 23 #define SRST_P_CORE_BIU 10 24 #define SRST_PMU 11 25 26 /* CRU-->SOFTRST_CON03 */ 27 #define SRST_P_DBG 12 28 #define SRST_POT_DBG 13 29 #define SRST_P_CORE_GRF 14 30 #define SRST_CORE_EMA_DETECT 15 31 #define SRST_REF_PVTPLL_CORE 16 32 #define SRST_P_GPIO1 17 33 #define SRST_DB_GPIO1 18 34 35 /* CRU-->SOFTRST_CON04 */ 36 #define SRST_A_CORE_PERI_BIU 19 37 #define SRST_A_DSMC 20 38 #define SRST_P_DSMC 21 39 #define SRST_FLEXBUS 22 40 #define SRST_A_FLEXBUS 23 41 #define SRST_H_FLEXBUS 24 42 #define SRST_A_DSMC_SLV 25 43 #define SRST_H_DSMC_SLV 26 44 #define SRST_DSMC_SLV 27 45 46 /* CRU-->SOFTRST_CON05 */ 47 #define SRST_A_BUS_BIU 28 48 #define SRST_H_BUS_BIU 29 49 #define SRST_P_BUS_BIU 30 50 #define SRST_A_SYSRAM 31 51 #define SRST_H_SYSRAM 32 52 #define SRST_A_DMAC0 33 53 #define SRST_A_DMAC1 34 54 #define SRST_H_M0 35 55 #define SRST_M0_JTAG 36 56 #define SRST_H_CRYPTO 37 57 58 /* CRU-->SOFTRST_CON06 */ 59 #define SRST_H_RNG 38 60 #define SRST_P_BUS_GRF 39 61 #define SRST_P_TIMER0 40 62 #define SRST_TIMER0_CH0 41 63 #define SRST_TIMER0_CH1 42 64 #define SRST_TIMER0_CH2 43 65 #define SRST_TIMER0_CH3 44 66 #define SRST_TIMER0_CH4 45 67 #define SRST_TIMER0_CH5 46 68 #define SRST_P_WDT0 47 69 #define SRST_T_WDT0 48 70 #define SRST_P_WDT1 49 71 #define SRST_T_WDT1 50 72 #define SRST_P_MAILBOX 51 73 #define SRST_P_INTMUX 52 74 #define SRST_P_SPINLOCK 53 75 76 /* CRU-->SOFTRST_CON07 */ 77 #define SRST_P_DDRC 54 78 #define SRST_H_DDRPHY 55 79 #define SRST_P_DDRMON 56 80 #define SRST_DDRMON_OSC 57 81 #define SRST_P_DDR_LPC 58 82 #define SRST_H_USBOTG0 59 83 #define SRST_USBOTG0_ADP 60 84 #define SRST_H_USBOTG1 61 85 #define SRST_USBOTG1_ADP 62 86 #define SRST_P_USBPHY 63 87 #define SRST_USBPHY_POR 64 88 #define SRST_USBPHY_OTG0 65 89 #define SRST_USBPHY_OTG1 66 90 91 /* CRU-->SOFTRST_CON08 */ 92 #define SRST_A_DMA2DDR 67 93 #define SRST_P_DMA2DDR 68 94 95 /* CRU-->SOFTRST_CON09 */ 96 #define SRST_USBOTG0_UTMI 69 97 #define SRST_USBOTG1_UTMI 70 98 99 /* CRU-->SOFTRST_CON10 */ 100 #define SRST_A_DDRC_0 71 101 #define SRST_A_DDRC_1 72 102 #define SRST_A_DDR_BIU 73 103 #define SRST_DDRC 74 104 #define SRST_DDRMON 75 105 106 /* CRU-->SOFTRST_CON11 */ 107 #define SRST_H_LSPERI_BIU 76 108 #define SRST_P_UART0 77 109 #define SRST_P_UART1 78 110 #define SRST_P_UART2 79 111 #define SRST_P_UART3 80 112 #define SRST_P_UART4 81 113 #define SRST_UART0 82 114 #define SRST_UART1 83 115 #define SRST_UART2 84 116 #define SRST_UART3 85 117 #define SRST_UART4 86 118 #define SRST_P_I2C0 87 119 #define SRST_I2C0 88 120 121 /* CRU-->SOFTRST_CON12 */ 122 #define SRST_P_I2C1 89 123 #define SRST_I2C1 90 124 #define SRST_P_I2C2 91 125 #define SRST_I2C2 92 126 #define SRST_P_PWM1 93 127 #define SRST_PWM1 94 128 #define SRST_P_SPI0 95 129 #define SRST_SPI0 96 130 #define SRST_P_SPI1 97 131 #define SRST_SPI1 98 132 #define SRST_P_GPIO2 99 133 #define SRST_DB_GPIO2 100 134 135 /* CRU-->SOFTRST_CON13 */ 136 #define SRST_P_GPIO3 101 137 #define SRST_DB_GPIO3 102 138 #define SRST_P_GPIO4 103 139 #define SRST_DB_GPIO4 104 140 #define SRST_H_CAN0 105 141 #define SRST_CAN0 106 142 #define SRST_H_CAN1 107 143 #define SRST_CAN1 108 144 #define SRST_H_PDM 109 145 #define SRST_M_PDM 110 146 #define SRST_PDM 111 147 #define SRST_SPDIFTX 112 148 #define SRST_H_SPDIFTX 113 149 #define SRST_H_SPDIFRX 114 150 #define SRST_SPDIFRX 115 151 #define SRST_M_SAI0 116 152 153 /* CRU-->SOFTRST_CON14 */ 154 #define SRST_H_SAI0 117 155 #define SRST_M_SAI1 118 156 #define SRST_H_SAI1 119 157 #define SRST_H_ASRC0 120 158 #define SRST_ASRC0 121 159 #define SRST_H_ASRC1 122 160 #define SRST_ASRC1 123 161 162 /* CRU-->SOFTRST_CON17 */ 163 #define SRST_H_HSPERI_BIU 124 164 #define SRST_H_SDMMC 125 165 #define SRST_H_FSPI 126 166 #define SRST_S_FSPI 127 167 #define SRST_P_SPI2 128 168 #define SRST_A_MAC0 129 169 #define SRST_A_MAC1 130 170 171 /* CRU-->SOFTRST_CON18 */ 172 #define SRST_M_SAI2 131 173 #define SRST_H_SAI2 132 174 #define SRST_H_SAI3 133 175 #define SRST_M_SAI3 134 176 #define SRST_H_SAI4 135 177 #define SRST_M_SAI4 136 178 #define SRST_H_DSM 137 179 #define SRST_M_DSM 138 180 #define SRST_P_AUDIO_ADC 139 181 #define SRST_M_AUDIO_ADC 140 182 183 /* CRU-->SOFTRST_CON19 */ 184 #define SRST_P_SARADC 141 185 #define SRST_SARADC 142 186 #define SRST_SARADC_PHY 143 187 #define SRST_P_OTPC_NS 144 188 #define SRST_SBPI_OTPC_NS 145 189 #define SRST_USER_OTPC_NS 146 190 #define SRST_P_UART5 147 191 #define SRST_UART5 148 192 #define SRST_P_GPIO234_IOC 149 193 194 /* CRU-->SOFTRST_CON21 */ 195 #define SRST_A_VIO_BIU 150 196 #define SRST_H_VIO_BIU 151 197 #define SRST_H_RGA 152 198 #define SRST_A_RGA 153 199 #define SRST_CORE_RGA 154 200 #define SRST_A_VOP 155 201 #define SRST_H_VOP 156 202 #define SRST_VOP 157 203 #define SRST_P_DPHY 158 204 #define SRST_P_DSI_HOST 159 205 #define SRST_P_TSADC 160 206 #define SRST_TSADC 161 207 208 /* CRU-->SOFTRST_CON22 */ 209 #define SRST_P_GPIO1_IOC 162 210 211 #endif 212