xref: /linux/include/linux/tpm_command.h (revision afe0579334f622c803f2864f22c04c20c320bd80)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_TPM_COMMAND_H__
3 #define __LINUX_TPM_COMMAND_H__
4 
5 #include <crypto/sha2.h>
6 
7 /*
8  * == TPM 1 Family Chips ==
9  *
10  * TPM 1.2 Main Specification:
11  * https://trustedcomputinggroup.org/resource/tpm-main-specification/
12  */
13 
14 #define TPM_MAX_ORDINAL	243
15 
16 /* Command TAGS */
17 enum tpm_command_tags {
18 	TPM_TAG_RQU_COMMAND		= 193,
19 	TPM_TAG_RQU_AUTH1_COMMAND	= 194,
20 	TPM_TAG_RQU_AUTH2_COMMAND	= 195,
21 	TPM_TAG_RSP_COMMAND		= 196,
22 	TPM_TAG_RSP_AUTH1_COMMAND	= 197,
23 	TPM_TAG_RSP_AUTH2_COMMAND	= 198,
24 };
25 
26 /* Command Ordinals */
27 enum tpm_command_ordinals {
28 	TPM_ORD_CONTINUE_SELFTEST	= 83,
29 	TPM_ORD_GET_CAP			= 101,
30 	TPM_ORD_GET_RANDOM		= 70,
31 	TPM_ORD_PCR_EXTEND		= 20,
32 	TPM_ORD_PCR_READ		= 21,
33 	TPM_ORD_OSAP			= 11,
34 	TPM_ORD_OIAP			= 10,
35 	TPM_ORD_SAVESTATE		= 152,
36 	TPM_ORD_SEAL			= 23,
37 	TPM_ORD_STARTUP			= 153,
38 	TPM_ORD_UNSEAL			= 24,
39 };
40 
41 enum tpm_capabilities {
42 	TPM_CAP_FLAG		= 4,
43 	TPM_CAP_PROP		= 5,
44 	TPM_CAP_VERSION_1_1	= 0x06,
45 	TPM_CAP_VERSION_1_2	= 0x1A,
46 };
47 
48 enum tpm_sub_capabilities {
49 	TPM_CAP_PROP_PCR		= 0x101,
50 	TPM_CAP_PROP_MANUFACTURER	= 0x103,
51 	TPM_CAP_FLAG_PERM		= 0x108,
52 	TPM_CAP_FLAG_VOL		= 0x109,
53 	TPM_CAP_PROP_OWNER		= 0x111,
54 	TPM_CAP_PROP_TIS_TIMEOUT	= 0x115,
55 	TPM_CAP_PROP_TIS_DURATION	= 0x120,
56 };
57 
58 /* Return Codes */
59 enum tpm_return_codes {
60 	TPM_BASE_MASK			= 0,
61 	TPM_NON_FATAL_MASK		= 0x00000800,
62 	TPM_SUCCESS			= TPM_BASE_MASK + 0,
63 	TPM_ERR_DEACTIVATED		= TPM_BASE_MASK + 6,
64 	TPM_ERR_DISABLED		= TPM_BASE_MASK + 7,
65 	TPM_ERR_FAIL			= TPM_BASE_MASK + 9,
66 	TPM_ERR_FAILEDSELFTEST		= TPM_BASE_MASK + 28,
67 	TPM_ERR_INVALID_POSTINIT	= TPM_BASE_MASK + 38,
68 	TPM_ERR_INVALID_FAMILY		= TPM_BASE_MASK + 55,
69 	TPM_WARN_RETRY			= TPM_BASE_MASK + TPM_NON_FATAL_MASK + 0,
70 	TPM_WARN_DOING_SELFTEST		= TPM_BASE_MASK + TPM_NON_FATAL_MASK + 2,
71 };
72 
73 struct	stclear_flags_t {
74 	__be16 tag;
75 	u8 deactivated;
76 	u8 disableForceClear;
77 	u8 physicalPresence;
78 	u8 physicalPresenceLock;
79 	u8 bGlobalLock;
80 } __packed;
81 
82 struct tpm1_version {
83 	u8 major;
84 	u8 minor;
85 	u8 rev_major;
86 	u8 rev_minor;
87 } __packed;
88 
89 struct tpm1_version2 {
90 	__be16 tag;
91 	struct tpm1_version version;
92 } __packed;
93 
94 struct	timeout_t {
95 	__be32 a;
96 	__be32 b;
97 	__be32 c;
98 	__be32 d;
99 } __packed;
100 
101 struct duration_t {
102 	__be32 tpm_short;
103 	__be32 tpm_medium;
104 	__be32 tpm_long;
105 } __packed;
106 
107 struct permanent_flags_t {
108 	__be16 tag;
109 	u8 disable;
110 	u8 ownership;
111 	u8 deactivated;
112 	u8 readPubek;
113 	u8 disableOwnerClear;
114 	u8 allowMaintenance;
115 	u8 physicalPresenceLifetimeLock;
116 	u8 physicalPresenceHWEnable;
117 	u8 physicalPresenceCMDEnable;
118 	u8 CEKPUsed;
119 	u8 TPMpost;
120 	u8 TPMpostLock;
121 	u8 FIPS;
122 	u8 operator;
123 	u8 enableRevokeEK;
124 	u8 nvLocked;
125 	u8 readSRKPub;
126 	u8 tpmEstablished;
127 	u8 maintenanceDone;
128 	u8 disableFullDALogicInfo;
129 } __packed;
130 
131 typedef union {
132 	struct permanent_flags_t perm_flags;
133 	struct stclear_flags_t stclear_flags;
134 	__u8 owned;
135 	__be32 num_pcrs;
136 	struct tpm1_version version1;
137 	struct tpm1_version2 version2;
138 	__be32 manufacturer_id;
139 	struct timeout_t timeout;
140 	struct duration_t duration;
141 } cap_t;
142 
143 /*
144  * 128 bytes is an arbitrary cap. This could be as large as TPM_BUFSIZE - 18
145  * bytes, but 128 is still a relatively large number of random bytes and
146  * anything much bigger causes users of struct tpm_cmd_t to start getting
147  * compiler warnings about stack frame size.
148  */
149 #define TPM_MAX_RNG_DATA		128
150 
151 struct tpm1_get_random_out {
152 	__be32 rng_data_len;
153 	u8 rng_data[TPM_MAX_RNG_DATA];
154 } __packed;
155 
156 /* Other constants */
157 #define SRKHANDLE                       0x40000000
158 #define TPM_NONCE_SIZE                  20
159 #define TPM_ST_CLEAR			1
160 
161 /*
162  * == TPM 2 Family Chips ==
163  *
164  * TPM 2.0 Library
165  * https://trustedcomputinggroup.org/resource/tpm-library-specification/
166  */
167 
168 /* TPM2 specific constants. */
169 #define TPM2_SPACE_BUFFER_SIZE		16384 /* 16 kB */
170 
171 enum tpm2_session_types {
172 	TPM2_SE_HMAC	= 0x00,
173 	TPM2_SE_POLICY	= 0x01,
174 	TPM2_SE_TRIAL	= 0x02,
175 };
176 
177 enum tpm2_timeouts {
178 	TPM2_TIMEOUT_A		= 750,
179 	TPM2_TIMEOUT_B		= 4000,
180 	TPM2_TIMEOUT_C		= 200,
181 	TPM2_TIMEOUT_D		= 30,
182 	TPM2_DURATION_SHORT	= 20,
183 	TPM2_DURATION_MEDIUM	= 750,
184 	TPM2_DURATION_LONG	= 2000,
185 	TPM2_DURATION_LONG_LONG	= 300000,
186 	TPM2_DURATION_DEFAULT	= 120000,
187 };
188 
189 enum tpm2_structures {
190 	TPM2_ST_NO_SESSIONS	= 0x8001,
191 	TPM2_ST_SESSIONS	= 0x8002,
192 	TPM2_ST_CREATION	= 0x8021,
193 };
194 
195 /* Indicates from what layer of the software stack the error comes from */
196 #define TSS2_RC_LAYER_SHIFT	 16
197 #define TSS2_RESMGR_TPM_RC_LAYER (11 << TSS2_RC_LAYER_SHIFT)
198 
199 enum tpm2_return_codes {
200 	TPM2_RC_SUCCESS		= 0x0000,
201 	TPM2_RC_HASH		= 0x0083, /* RC_FMT1 */
202 	TPM2_RC_HANDLE		= 0x008B,
203 	TPM2_RC_INTEGRITY	= 0x009F,
204 	TPM2_RC_INITIALIZE	= 0x0100, /* RC_VER1 */
205 	TPM2_RC_FAILURE		= 0x0101,
206 	TPM2_RC_DISABLED	= 0x0120,
207 	TPM2_RC_UPGRADE		= 0x012D,
208 	TPM2_RC_COMMAND_CODE	= 0x0143,
209 	TPM2_RC_TESTING		= 0x090A, /* RC_WARN */
210 	TPM2_RC_REFERENCE_H0	= 0x0910,
211 	TPM2_RC_RETRY		= 0x0922,
212 	TPM2_RC_SESSION_MEMORY	= 0x0903,
213 };
214 
215 enum tpm2_command_codes {
216 	TPM2_CC_FIRST			= 0x011F,
217 	TPM2_CC_HIERARCHY_CONTROL	= 0x0121,
218 	TPM2_CC_HIERARCHY_CHANGE_AUTH	= 0x0129,
219 	TPM2_CC_CREATE_PRIMARY		= 0x0131,
220 	TPM2_CC_SEQUENCE_COMPLETE	= 0x013E,
221 	TPM2_CC_SELF_TEST		= 0x0143,
222 	TPM2_CC_STARTUP			= 0x0144,
223 	TPM2_CC_SHUTDOWN		= 0x0145,
224 	TPM2_CC_NV_READ			= 0x014E,
225 	TPM2_CC_CREATE			= 0x0153,
226 	TPM2_CC_LOAD			= 0x0157,
227 	TPM2_CC_SEQUENCE_UPDATE		= 0x015C,
228 	TPM2_CC_UNSEAL			= 0x015E,
229 	TPM2_CC_CONTEXT_LOAD		= 0x0161,
230 	TPM2_CC_CONTEXT_SAVE		= 0x0162,
231 	TPM2_CC_FLUSH_CONTEXT		= 0x0165,
232 	TPM2_CC_READ_PUBLIC		= 0x0173,
233 	TPM2_CC_START_AUTH_SESS		= 0x0176,
234 	TPM2_CC_VERIFY_SIGNATURE	= 0x0177,
235 	TPM2_CC_GET_CAPABILITY		= 0x017A,
236 	TPM2_CC_GET_RANDOM		= 0x017B,
237 	TPM2_CC_PCR_READ		= 0x017E,
238 	TPM2_CC_PCR_EXTEND		= 0x0182,
239 	TPM2_CC_EVENT_SEQUENCE_COMPLETE	= 0x0185,
240 	TPM2_CC_HASH_SEQUENCE_START	= 0x0186,
241 	TPM2_CC_CREATE_LOADED		= 0x0191,
242 	TPM2_CC_LAST			= 0x0193, /* Spec 1.36 */
243 };
244 
245 enum tpm2_capabilities {
246 	TPM2_CAP_HANDLES	= 1,
247 	TPM2_CAP_COMMANDS	= 2,
248 	TPM2_CAP_PCRS		= 5,
249 	TPM2_CAP_TPM_PROPERTIES = 6,
250 };
251 
252 enum tpm2_properties {
253 	TPM_PT_TOTAL_COMMANDS	= 0x0129,
254 };
255 
256 enum tpm2_startup_types {
257 	TPM2_SU_CLEAR		= 0x0000,
258 	TPM2_SU_STATE		= 0x0001,
259 };
260 
261 enum tpm2_cc_attrs {
262 	TPM2_CC_ATTR_CHANDLES	= 25,
263 	TPM2_CC_ATTR_RHANDLE	= 28,
264 	TPM2_CC_ATTR_VENDOR	= 29,
265 };
266 
267 enum tpm2_permanent_handles {
268 	TPM2_RH_NULL		= 0x40000007,
269 	TPM2_RS_PW		= 0x40000009,
270 };
271 
272 /* Most Significant Octet for key types  */
273 enum tpm2_mso_type {
274 	TPM2_MSO_NVRAM		= 0x01,
275 	TPM2_MSO_SESSION	= 0x02,
276 	TPM2_MSO_POLICY		= 0x03,
277 	TPM2_MSO_PERMANENT	= 0x40,
278 	TPM2_MSO_VOLATILE	= 0x80,
279 	TPM2_MSO_PERSISTENT	= 0x81,
280 };
281 
282 enum tpm2_curves {
283 	TPM2_ECC_NONE		= 0x0000,
284 	TPM2_ECC_NIST_P256	= 0x0003,
285 };
286 
287 enum tpm2_object_attributes {
288 	TPM2_OA_FIXED_TPM		= BIT(1),
289 	TPM2_OA_ST_CLEAR		= BIT(2),
290 	TPM2_OA_FIXED_PARENT		= BIT(4),
291 	TPM2_OA_SENSITIVE_DATA_ORIGIN	= BIT(5),
292 	TPM2_OA_USER_WITH_AUTH		= BIT(6),
293 	TPM2_OA_ADMIN_WITH_POLICY	= BIT(7),
294 	TPM2_OA_NO_DA			= BIT(10),
295 	TPM2_OA_ENCRYPTED_DUPLICATION	= BIT(11),
296 	TPM2_OA_RESTRICTED		= BIT(16),
297 	TPM2_OA_DECRYPT			= BIT(17),
298 	TPM2_OA_SIGN			= BIT(18),
299 };
300 
301 enum tpm2_session_attributes {
302 	TPM2_SA_CONTINUE_SESSION	= BIT(0),
303 	TPM2_SA_AUDIT_EXCLUSIVE		= BIT(1),
304 	TPM2_SA_AUDIT_RESET		= BIT(3),
305 	TPM2_SA_DECRYPT			= BIT(5),
306 	TPM2_SA_ENCRYPT			= BIT(6),
307 	TPM2_SA_AUDIT			= BIT(7),
308 };
309 
310 enum tpm2_pcr_select {
311 	TPM2_PLATFORM_PCR	= 24,
312 	TPM2_PCR_SELECT_MIN	= ((TPM2_PLATFORM_PCR + 7) / 8),
313 };
314 
315 enum tpm2_handle_types {
316 	TPM2_HT_HMAC_SESSION	= 0x02000000,
317 	TPM2_HT_POLICY_SESSION	= 0x03000000,
318 	TPM2_HT_TRANSIENT	= 0x80000000,
319 };
320 
321 enum tpm2_pt_props {
322 	TPM2_PT_NONE			= 0x00000000,
323 	TPM2_PT_GROUP			= 0x00000100,
324 	TPM2_PT_FIXED			= TPM2_PT_GROUP * 1,
325 	TPM2_PT_FAMILY_INDICATOR	= TPM2_PT_FIXED + 0,
326 	TPM2_PT_LEVEL		= TPM2_PT_FIXED + 1,
327 	TPM2_PT_REVISION	= TPM2_PT_FIXED + 2,
328 	TPM2_PT_DAY_OF_YEAR	= TPM2_PT_FIXED + 3,
329 	TPM2_PT_YEAR		= TPM2_PT_FIXED + 4,
330 	TPM2_PT_MANUFACTURER	= TPM2_PT_FIXED + 5,
331 	TPM2_PT_VENDOR_STRING_1	= TPM2_PT_FIXED + 6,
332 	TPM2_PT_VENDOR_STRING_2	= TPM2_PT_FIXED + 7,
333 	TPM2_PT_VENDOR_STRING_3	= TPM2_PT_FIXED + 8,
334 	TPM2_PT_VENDOR_STRING_4	= TPM2_PT_FIXED + 9,
335 	TPM2_PT_VENDOR_TPM_TYPE	= TPM2_PT_FIXED + 10,
336 	TPM2_PT_FIRMWARE_VERSION_1	= TPM2_PT_FIXED + 11,
337 	TPM2_PT_FIRMWARE_VERSION_2	= TPM2_PT_FIXED + 12,
338 	TPM2_PT_INPUT_BUFFER		= TPM2_PT_FIXED + 13,
339 	TPM2_PT_HR_TRANSIENT_MIN	= TPM2_PT_FIXED + 14,
340 	TPM2_PT_HR_PERSISTENT_MIN	= TPM2_PT_FIXED + 15,
341 	TPM2_PT_HR_LOADED_MIN		= TPM2_PT_FIXED + 16,
342 	TPM2_PT_ACTIVE_SESSIONS_MAX	= TPM2_PT_FIXED + 17,
343 	TPM2_PT_PCR_COUNT	= TPM2_PT_FIXED + 18,
344 	TPM2_PT_PCR_SELECT_MIN	= TPM2_PT_FIXED + 19,
345 	TPM2_PT_CONTEXT_GAP_MAX	= TPM2_PT_FIXED + 20,
346 	TPM2_PT_NV_COUNTERS_MAX	= TPM2_PT_FIXED + 22,
347 	TPM2_PT_NV_INDEX_MAX	= TPM2_PT_FIXED + 23,
348 	TPM2_PT_MEMORY		= TPM2_PT_FIXED + 24,
349 	TPM2_PT_CLOCK_UPDATE	= TPM2_PT_FIXED + 25,
350 	TPM2_PT_CONTEXT_HASH	= TPM2_PT_FIXED + 26,
351 	TPM2_PT_CONTEXT_SYM	= TPM2_PT_FIXED + 27,
352 	TPM2_PT_CONTEXT_SYM_SIZE	= TPM2_PT_FIXED + 28,
353 	TPM2_PT_ORDERLY_COUNT		= TPM2_PT_FIXED + 29,
354 	TPM2_PT_MAX_COMMAND_SIZE	= TPM2_PT_FIXED + 30,
355 	TPM2_PT_MAX_RESPONSE_SIZE	= TPM2_PT_FIXED + 31,
356 	TPM2_PT_MAX_DIGEST		= TPM2_PT_FIXED + 32,
357 	TPM2_PT_MAX_OBJECT_CONTEXT	= TPM2_PT_FIXED + 33,
358 	TPM2_PT_MAX_SESSION_CONTEXT	= TPM2_PT_FIXED + 34,
359 	TPM2_PT_PS_FAMILY_INDICATOR	= TPM2_PT_FIXED + 35,
360 	TPM2_PT_PS_LEVEL	= TPM2_PT_FIXED + 36,
361 	TPM2_PT_PS_REVISION	= TPM2_PT_FIXED + 37,
362 	TPM2_PT_PS_DAY_OF_YEAR	= TPM2_PT_FIXED + 38,
363 	TPM2_PT_PS_YEAR		= TPM2_PT_FIXED + 39,
364 	TPM2_PT_SPLIT_MAX	= TPM2_PT_FIXED + 40,
365 	TPM2_PT_TOTAL_COMMANDS	= TPM2_PT_FIXED + 41,
366 	TPM2_PT_LIBRARY_COMMANDS	= TPM2_PT_FIXED + 42,
367 	TPM2_PT_VENDOR_COMMANDS		= TPM2_PT_FIXED + 43,
368 	TPM2_PT_NV_BUFFER_MAX		= TPM2_PT_FIXED + 44,
369 	TPM2_PT_MODES			= TPM2_PT_FIXED + 45,
370 	TPM2_PT_MAX_CAP_BUFFER		= TPM2_PT_FIXED + 46,
371 	TPM2_PT_VAR		= TPM2_PT_GROUP * 2,
372 	TPM2_PT_PERMANENT	= TPM2_PT_VAR + 0,
373 	TPM2_PT_STARTUP_CLEAR	= TPM2_PT_VAR + 1,
374 	TPM2_PT_HR_NV_INDEX	= TPM2_PT_VAR + 2,
375 	TPM2_PT_HR_LOADED	= TPM2_PT_VAR + 3,
376 	TPM2_PT_HR_LOADED_AVAIL	= TPM2_PT_VAR + 4,
377 	TPM2_PT_HR_ACTIVE	= TPM2_PT_VAR + 5,
378 	TPM2_PT_HR_ACTIVE_AVAIL	= TPM2_PT_VAR + 6,
379 	TPM2_PT_HR_TRANSIENT_AVAIL	= TPM2_PT_VAR + 7,
380 	TPM2_PT_HR_PERSISTENT		= TPM2_PT_VAR + 8,
381 	TPM2_PT_HR_PERSISTENT_AVAIL	= TPM2_PT_VAR + 9,
382 	TPM2_PT_NV_COUNTERS		= TPM2_PT_VAR + 10,
383 	TPM2_PT_NV_COUNTERS_AVAIL	= TPM2_PT_VAR + 11,
384 	TPM2_PT_ALGORITHM_SET		= TPM2_PT_VAR + 12,
385 	TPM2_PT_LOADED_CURVES		= TPM2_PT_VAR + 13,
386 	TPM2_PT_LOCKOUT_COUNTER		= TPM2_PT_VAR + 14,
387 	TPM2_PT_MAX_AUTH_FAIL		= TPM2_PT_VAR + 15,
388 	TPM2_PT_LOCKOUT_INTERVAL	= TPM2_PT_VAR + 16,
389 	TPM2_PT_LOCKOUT_RECOVERY	= TPM2_PT_VAR + 17,
390 	TPM2_PT_NV_WRITE_RECOVERY	= TPM2_PT_VAR + 18,
391 	TPM2_PT_AUDIT_COUNTER_0	= TPM2_PT_VAR + 19,
392 	TPM2_PT_AUDIT_COUNTER_1	= TPM2_PT_VAR + 20,
393 };
394 
395 struct tpm2_pcr_read_out {
396 	__be32 update_cnt;
397 	__be32 pcr_selects_cnt;
398 	__be16 hash_alg;
399 	u8 pcr_select_size;
400 	u8 pcr_select[TPM2_PCR_SELECT_MIN];
401 	__be32 digests_cnt;
402 	__be16 digest_size;
403 	u8 digest[];
404 } __packed;
405 
406 struct tpm2_get_random_out {
407 	__be16 size;
408 	u8 buffer[TPM_MAX_RNG_DATA];
409 } __packed;
410 
411 struct tpm2_get_cap_out {
412 	u8 more_data;
413 	__be32 subcap_id;
414 	__be32 property_cnt;
415 	__be32 property_id;
416 	__be32 value;
417 } __packed;
418 
419 struct tpm2_pcr_selection {
420 	__be16 hash_alg;
421 	u8 size_of_select;
422 	u8 pcr_select[3];
423 } __packed;
424 
425 struct tpm2_context {
426 	__be64 sequence;
427 	__be32 saved_handle;
428 	__be32 hierarchy;
429 	__be16 blob_size;
430 } __packed;
431 
432 /*
433  * == TPM Common Defs ==
434  */
435 
436 #define TPM_DIGEST_SIZE		20	/* Max TPM v1.2 PCR size */
437 #define TPM_BUFSIZE		4096
438 
439 /*
440  * SHA-512 is, as of today, the largest digest in the TCG algorithm repository.
441  */
442 #define TPM2_MAX_DIGEST_SIZE	SHA512_DIGEST_SIZE
443 
444 /*
445  * A TPM name digest i.e., TPMT_HA, is a concatenation of TPM_ALG_ID of the
446  * name algorithm and hash of TPMT_PUBLIC.
447  */
448 #define TPM2_MAX_NAME_SIZE	(TPM2_MAX_DIGEST_SIZE + 2)
449 
450 /*
451  * Fixed define for the size of a name.  This is actually HASHALG size
452  * plus 2, so 32 for SHA256
453  */
454 #define TPM2_NULL_NAME_SIZE	34
455 
456 /*
457  * The maximum number of PCR banks.
458  */
459 #define TPM2_MAX_PCR_BANKS	8
460 
461 /* If you add a new hash to this, increment TPM_MAX_HASHES below */
462 enum tpm_algorithms {
463 	TPM_ALG_ERROR		= 0x0000,
464 	TPM_ALG_SHA1		= 0x0004,
465 	TPM_ALG_AES		= 0x0006,
466 	TPM_ALG_KEYEDHASH	= 0x0008,
467 	TPM_ALG_SHA256		= 0x000B,
468 	TPM_ALG_SHA384		= 0x000C,
469 	TPM_ALG_SHA512		= 0x000D,
470 	TPM_ALG_NULL		= 0x0010,
471 	TPM_ALG_SM3_256		= 0x0012,
472 	TPM_ALG_ECC		= 0x0023,
473 	TPM_ALG_CFB		= 0x0043,
474 };
475 
476 /*
477  * The locality (0 - 4) for a TPM, as defined in section 3.2 of the
478  * Client Platform Profile Specification.
479  */
480 enum tpm_localities {
481 	TPM_LOCALITY_0		= 0, /* Static RTM */
482 	TPM_LOCALITY_1		= 1, /* Dynamic OS */
483 	TPM_LOCALITY_2		= 2, /* DRTM Environment */
484 	TPM_LOCALITY_3		= 3, /* Aux Components */
485 	TPM_LOCALITY_4		= 4, /* CPU DRTM Establishment */
486 	TPM_MAX_LOCALITY	= TPM_LOCALITY_4
487 };
488 
489 /*
490  * Structure to represent active PCR algorithm banks usable by the
491  * TPM chip.
492  */
493 struct tpm_bank_info {
494 	u16 alg_id;
495 	u16 digest_size;
496 	u16 crypto_id;
497 };
498 
499 /*
500  * Maximum number of hashing algorithms a TPM can have.  This is
501  * basically a count of every hash in tpm_algorithms above
502  */
503 #define TPM_MAX_HASHES		5
504 
505 struct tpm_digest {
506 	u16 alg_id;
507 	u8 digest[TPM2_MAX_DIGEST_SIZE];
508 } __packed;
509 
510 #define TPM_HEADER_SIZE		10
511 
512 struct tpm_header {
513 	__be16 tag;
514 	__be32 length;
515 	union {
516 		__be32 ordinal;
517 		__be32 return_code;
518 	};
519 } __packed;
520 
521 #endif
522