1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __SP_GLOBAL_H_INCLUDED__ 17 #define __SP_GLOBAL_H_INCLUDED__ 18 19 #include <system_local.h> 20 21 #include <scalar_processor_2400_params.h> 22 23 #define SP_PMEM_WIDTH_LOG2 SP_PMEM_LOG_WIDTH_BITS 24 #define SP_PMEM_SIZE SP_PMEM_DEPTH 25 26 #define SP_DMEM_SIZE 0x4000 27 28 /* SP Registers */ 29 #define SP_PC_REG 0x09 30 #define SP_SC_REG 0x00 31 #define SP_START_ADDR_REG 0x01 32 #define SP_ICACHE_ADDR_REG 0x05 33 #define SP_IRQ_READY_REG 0x00 34 #define SP_IRQ_CLEAR_REG 0x00 35 #define SP_ICACHE_INV_REG 0x00 36 #define SP_CTRL_SINK_REG 0x0A 37 38 /* SP Register bits */ 39 #define SP_RST_BIT 0x00 40 #define SP_START_BIT 0x01 41 #define SP_BREAK_BIT 0x02 42 #define SP_RUN_BIT 0x03 43 #define SP_BROKEN_BIT 0x04 44 #define SP_IDLE_BIT 0x05 /* READY */ 45 #define SP_SLEEPING_BIT 0x06 46 #define SP_STALLING_BIT 0x07 47 #define SP_IRQ_CLEAR_BIT 0x08 48 #define SP_IRQ_READY_BIT 0x0A 49 #define SP_IRQ_SLEEPING_BIT 0x0B 50 51 #define SP_ICACHE_INV_BIT 0x0C 52 #define SP_IPREFETCH_EN_BIT 0x0D 53 54 #define SP_FIFO0_SINK_BIT 0x00 55 #define SP_FIFO1_SINK_BIT 0x01 56 #define SP_FIFO2_SINK_BIT 0x02 57 #define SP_FIFO3_SINK_BIT 0x03 58 #define SP_FIFO4_SINK_BIT 0x04 59 #define SP_FIFO5_SINK_BIT 0x05 60 #define SP_FIFO6_SINK_BIT 0x06 61 #define SP_FIFO7_SINK_BIT 0x07 62 #define SP_FIFO8_SINK_BIT 0x08 63 #define SP_FIFO9_SINK_BIT 0x09 64 #define SP_FIFOA_SINK_BIT 0x0A 65 #define SP_DMEM_SINK_BIT 0x0B 66 #define SP_CTRL_MT_SINK_BIT 0x0C 67 #define SP_ICACHE_MT_SINK_BIT 0x0D 68 69 #define SP_FIFO0_SINK_REG 0x0A 70 #define SP_FIFO1_SINK_REG 0x0A 71 #define SP_FIFO2_SINK_REG 0x0A 72 #define SP_FIFO3_SINK_REG 0x0A 73 #define SP_FIFO4_SINK_REG 0x0A 74 #define SP_FIFO5_SINK_REG 0x0A 75 #define SP_FIFO6_SINK_REG 0x0A 76 #define SP_FIFO7_SINK_REG 0x0A 77 #define SP_FIFO8_SINK_REG 0x0A 78 #define SP_FIFO9_SINK_REG 0x0A 79 #define SP_FIFOA_SINK_REG 0x0A 80 #define SP_DMEM_SINK_REG 0x0A 81 #define SP_CTRL_MT_SINK_REG 0x0A 82 #define SP_ICACHE_MT_SINK_REG 0x0A 83 84 #endif /* __SP_GLOBAL_H_INCLUDED__ */ 85