1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel Core SoC Power Management Controller Header File 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12 #ifndef PMC_CORE_H 13 #define PMC_CORE_H 14 15 #include <linux/acpi.h> 16 #include <linux/bits.h> 17 #include <linux/platform_device.h> 18 19 struct telem_endpoint; 20 21 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) 22 23 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 24 #define MAX_NUM_PMC 3 25 #define S0IX_BLK_SIZE 4 26 27 /* Sunrise Point Power Management Controller PCI Device ID */ 28 #define SPT_PMC_PCI_DEVICE_ID 0x9d21 29 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 30 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 31 #define SPT_PMC_PM_CFG_OFFSET 0x18 32 #define SPT_PMC_PM_STS_OFFSET 0x1c 33 #define SPT_PMC_MTPMC_OFFSET 0x20 34 #define SPT_PMC_MFPMC_OFFSET 0x38 35 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 36 #define SPT_PMC_VRIC1_OFFSET 0x31c 37 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 38 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 39 #define SPT_PMC_MPHY_COM_STS_0 0x1155 40 #define SPT_PMC_MMIO_REG_LEN 0x1000 41 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 42 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 43 #define MTPMC_MASK 0xffff0000 44 #define PPFEAR_MAX_NUM_ENTRIES 12 45 #define SPT_PPFEAR_NUM_ENTRIES 5 46 #define SPT_PMC_READ_DISABLE_BIT 0x16 47 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 48 #define NUM_RETRIES 100 49 #define SPT_NUM_IP_IGN_ALLOWED 17 50 51 #define SPT_PMC_LTR_CUR_PLT 0x350 52 #define SPT_PMC_LTR_CUR_ASLT 0x354 53 #define SPT_PMC_LTR_SPA 0x360 54 #define SPT_PMC_LTR_SPB 0x364 55 #define SPT_PMC_LTR_SATA 0x368 56 #define SPT_PMC_LTR_GBE 0x36C 57 #define SPT_PMC_LTR_XHCI 0x370 58 #define SPT_PMC_LTR_RESERVED 0x374 59 #define SPT_PMC_LTR_ME 0x378 60 #define SPT_PMC_LTR_EVA 0x37C 61 #define SPT_PMC_LTR_SPC 0x380 62 #define SPT_PMC_LTR_AZ 0x384 63 #define SPT_PMC_LTR_LPSS 0x38C 64 #define SPT_PMC_LTR_CAM 0x390 65 #define SPT_PMC_LTR_SPD 0x394 66 #define SPT_PMC_LTR_SPE 0x398 67 #define SPT_PMC_LTR_ESPI 0x39C 68 #define SPT_PMC_LTR_SCC 0x3A0 69 #define SPT_PMC_LTR_ISH 0x3A4 70 71 #define SPT_PMC_ACPI_PM_TMR_CTL_OFFSET 0x18FC 72 73 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ 74 enum ppfear_regs { 75 SPT_PMC_XRAM_PPFEAR0A = 0x590, 76 SPT_PMC_XRAM_PPFEAR0B, 77 SPT_PMC_XRAM_PPFEAR0C, 78 SPT_PMC_XRAM_PPFEAR0D, 79 SPT_PMC_XRAM_PPFEAR1A, 80 }; 81 82 #define SPT_PMC_BIT_PMC BIT(0) 83 #define SPT_PMC_BIT_OPI BIT(1) 84 #define SPT_PMC_BIT_SPI BIT(2) 85 #define SPT_PMC_BIT_XHCI BIT(3) 86 #define SPT_PMC_BIT_SPA BIT(4) 87 #define SPT_PMC_BIT_SPB BIT(5) 88 #define SPT_PMC_BIT_SPC BIT(6) 89 #define SPT_PMC_BIT_GBE BIT(7) 90 91 #define SPT_PMC_BIT_SATA BIT(0) 92 #define SPT_PMC_BIT_HDA_PGD0 BIT(1) 93 #define SPT_PMC_BIT_HDA_PGD1 BIT(2) 94 #define SPT_PMC_BIT_HDA_PGD2 BIT(3) 95 #define SPT_PMC_BIT_HDA_PGD3 BIT(4) 96 #define SPT_PMC_BIT_RSVD_0B BIT(5) 97 #define SPT_PMC_BIT_LPSS BIT(6) 98 #define SPT_PMC_BIT_LPC BIT(7) 99 100 #define SPT_PMC_BIT_SMB BIT(0) 101 #define SPT_PMC_BIT_ISH BIT(1) 102 #define SPT_PMC_BIT_P2SB BIT(2) 103 #define SPT_PMC_BIT_DFX BIT(3) 104 #define SPT_PMC_BIT_SCC BIT(4) 105 #define SPT_PMC_BIT_RSVD_0C BIT(5) 106 #define SPT_PMC_BIT_FUSE BIT(6) 107 #define SPT_PMC_BIT_CAMREA BIT(7) 108 109 #define SPT_PMC_BIT_RSVD_0D BIT(0) 110 #define SPT_PMC_BIT_USB3_OTG BIT(1) 111 #define SPT_PMC_BIT_EXI BIT(2) 112 #define SPT_PMC_BIT_CSE BIT(3) 113 #define SPT_PMC_BIT_CSME_KVM BIT(4) 114 #define SPT_PMC_BIT_CSME_PMT BIT(5) 115 #define SPT_PMC_BIT_CSME_CLINK BIT(6) 116 #define SPT_PMC_BIT_CSME_PTIO BIT(7) 117 118 #define SPT_PMC_BIT_CSME_USBR BIT(0) 119 #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 120 #define SPT_PMC_BIT_CSME_SMT BIT(2) 121 #define SPT_PMC_BIT_RSVD_1A BIT(3) 122 #define SPT_PMC_BIT_CSME_SMS2 BIT(4) 123 #define SPT_PMC_BIT_CSME_SMS1 BIT(5) 124 #define SPT_PMC_BIT_CSME_RTC BIT(6) 125 #define SPT_PMC_BIT_CSME_PSF BIT(7) 126 127 #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 128 #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 129 #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 130 #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 131 #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 132 #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 133 #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 134 #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 135 136 #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 137 #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 138 #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 139 #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 140 #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 141 #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 142 #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 143 #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 144 145 #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 146 #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 147 #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 148 #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 149 150 #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) 151 #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) 152 153 #define SPT_PMC_BIT_ACPI_PM_TMR_DISABLE BIT(1) 154 155 /* Cannonlake Power Management Controller register offsets */ 156 #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 157 #define CNP_PMC_PM_CFG_OFFSET 0x1818 158 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C 159 #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C 160 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ 161 #define CNP_PMC_HOST_PPFEAR0A 0x1D90 162 163 #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) 164 165 #define CNP_PMC_MMIO_REG_LEN 0x2000 166 #define CNP_PPFEAR_NUM_ENTRIES 8 167 #define CNP_PMC_READ_DISABLE_BIT 22 168 #define CNP_NUM_IP_IGN_ALLOWED 19 169 #define CNP_PMC_LTR_CUR_PLT 0x1B50 170 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 171 #define CNP_PMC_LTR_SPA 0x1B60 172 #define CNP_PMC_LTR_SPB 0x1B64 173 #define CNP_PMC_LTR_SATA 0x1B68 174 #define CNP_PMC_LTR_GBE 0x1B6C 175 #define CNP_PMC_LTR_XHCI 0x1B70 176 #define CNP_PMC_LTR_RESERVED 0x1B74 177 #define CNP_PMC_LTR_ME 0x1B78 178 #define CNP_PMC_LTR_EVA 0x1B7C 179 #define CNP_PMC_LTR_SPC 0x1B80 180 #define CNP_PMC_LTR_AZ 0x1B84 181 #define CNP_PMC_LTR_LPSS 0x1B8C 182 #define CNP_PMC_LTR_CAM 0x1B90 183 #define CNP_PMC_LTR_SPD 0x1B94 184 #define CNP_PMC_LTR_SPE 0x1B98 185 #define CNP_PMC_LTR_ESPI 0x1B9C 186 #define CNP_PMC_LTR_SCC 0x1BA0 187 #define CNP_PMC_LTR_ISH 0x1BA4 188 #define CNP_PMC_LTR_CNV 0x1BF0 189 #define CNP_PMC_LTR_EMMC 0x1BF4 190 #define CNP_PMC_LTR_UFSX2 0x1BF8 191 192 #define LTR_DECODED_VAL GENMASK(9, 0) 193 #define LTR_DECODED_SCALE GENMASK(12, 10) 194 #define LTR_REQ_SNOOP BIT(15) 195 #define LTR_REQ_NONSNOOP BIT(31) 196 197 #define ICL_PPFEAR_NUM_ENTRIES 9 198 #define ICL_NUM_IP_IGN_ALLOWED 20 199 #define ICL_PMC_LTR_WIGIG 0x1BFC 200 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 201 202 #define LPM_MAX_NUM_MODES 8 203 #define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 } 204 205 #define GET_X2_COUNTER(v) ((v) >> 1) 206 #define LPM_STS_LATCH_MODE BIT(31) 207 208 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A 209 #define TGL_PMC_LTR_THC0 0x1C04 210 #define TGL_PMC_LTR_THC1 0x1C08 211 #define TGL_NUM_IP_IGN_ALLOWED 23 212 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ 213 214 #define ADL_PMC_LTR_SPF 0x1C00 215 #define ADL_NUM_IP_IGN_ALLOWED 23 216 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 217 218 /* 219 * Tigerlake Power Management Controller register offsets 220 */ 221 #define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 222 #define TGL_LPM_EN_OFFSET 0x1C78 223 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 224 225 /* Tigerlake Low Power Mode debug registers */ 226 #define TGL_LPM_STATUS_OFFSET 0x1C3C 227 #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C 228 #define TGL_LPM_PRI_OFFSET 0x1C7C 229 #define TGL_LPM_NUM_MAPS 6 230 231 /* Tigerlake PSON residency register */ 232 #define TGL_PSON_RESIDENCY_OFFSET 0x18f8 233 #define TGL_PSON_RES_COUNTER_STEP 0x7A 234 235 /* Extended Test Mode Register 3 (CNL and later) */ 236 #define ETR3_OFFSET 0x1048 237 #define ETR3_CF9GR BIT(20) 238 #define ETR3_CF9LOCK BIT(31) 239 240 /* Extended Test Mode Register LPM bits (TGL and later */ 241 #define ETR3_CLEAR_LPM_EVENTS BIT(28) 242 243 /* Alder Lake Power Management Controller register offsets */ 244 #define ADL_LPM_EN_OFFSET 0x179C 245 #define ADL_LPM_RESIDENCY_OFFSET 0x17A4 246 #define ADL_LPM_NUM_MODES 2 247 #define ADL_LPM_NUM_MAPS 14 248 249 /* Alder Lake Low Power Mode debug registers */ 250 #define ADL_LPM_STATUS_OFFSET 0x170C 251 #define ADL_LPM_PRI_OFFSET 0x17A0 252 #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 253 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 254 255 /* Meteor Lake Power Management Controller register offsets */ 256 #define MTL_LPM_EN_OFFSET 0x1798 257 #define MTL_LPM_RESIDENCY_OFFSET 0x17A0 258 259 /* Meteor Lake Low Power Mode debug registers */ 260 #define MTL_LPM_PRI_OFFSET 0x179C 261 #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 262 #define MTL_LPM_STATUS_OFFSET 0x1700 263 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C 264 #define MTL_PMC_LTR_IOE_PMC 0x1C0C 265 #define MTL_PMC_LTR_ESE 0x1BAC 266 #define MTL_PMC_LTR_RESERVED 0x1BA4 267 #define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4 268 #define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 269 #define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 270 #define MTL_PMC_LTR_SPG 0x1B74 271 #define ARL_SOCS_PMC_LTR_RESERVED 0x1B88 272 #define ARL_SOCS_NUM_IP_IGN_ALLOWED 26 273 #define ARL_PMC_LTR_DMI3 0x1BE4 274 #define ARL_PCH_PMC_MMIO_REG_LEN 0x2720 275 276 /* Meteor Lake PGD PFET Enable Ack Status */ 277 #define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 278 #define MTL_IOE_PPFEAR_NUM_ENTRIES 10 279 #define ARL_SOCS_PPFEAR_NUM_ENTRIES 9 280 281 /* Die C6 from PUNIT telemetry */ 282 #define MTL_PMT_DMU_DIE_C6_OFFSET 15 283 #define MTL_PMT_DMU_GUID 0x1A067102 284 #define ARL_PMT_DMU_GUID 0x1A06A000 285 286 #define LNL_PMC_MMIO_REG_LEN 0x2708 287 #define LNL_PMC_LTR_OSSE 0x1B88 288 #define LNL_NUM_IP_IGN_ALLOWED 27 289 #define LNL_PPFEAR_NUM_ENTRIES 12 290 #define LNL_S0IX_BLOCKER_OFFSET 0x2004 291 292 extern const char *pmc_lpm_modes[]; 293 294 struct pmc_bit_map { 295 const char *name; 296 u32 bit_mask; 297 u8 blk; 298 }; 299 300 /** 301 * struct pmc_reg_map - Structure used to define parameter unique to a 302 PCH family 303 * @pfear_sts: Maps name of IP block to PPFEAR* bit 304 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 305 * @pll_sts: Maps name of PLL to corresponding bit status 306 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info 307 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets 308 * @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter 309 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 310 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 311 * @regmap_length: Length of memory to map from PWRMBASE address to access 312 * @ppfear0_offset: PWRMBASE offset to read PPFEAR* 313 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 314 * PPFEAR 315 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 316 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 317 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* 318 * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter 319 * 320 * Each PCH has unique set of register offsets and bit indexes. This structure 321 * captures them to have a common implementation. 322 */ 323 struct pmc_reg_map { 324 const struct pmc_bit_map **pfear_sts; 325 const struct pmc_bit_map *mphy_sts; 326 const struct pmc_bit_map *pll_sts; 327 const struct pmc_bit_map **slps0_dbg_maps; 328 const struct pmc_bit_map *ltr_show_sts; 329 const struct pmc_bit_map *msr_sts; 330 const struct pmc_bit_map **lpm_sts; 331 const struct pmc_bit_map **s0ix_blocker_maps; 332 const u32 slp_s0_offset; 333 const int slp_s0_res_counter_step; 334 const u32 ltr_ignore_offset; 335 const int regmap_length; 336 const u32 ppfear0_offset; 337 const int ppfear_buckets; 338 const u32 pm_cfg_offset; 339 const int pm_read_disable_bit; 340 const u32 slps0_dbg_offset; 341 const u32 ltr_ignore_max; 342 const u32 pm_vric1_offset; 343 const u32 s0ix_blocker_offset; 344 /* Low Power Mode registers */ 345 const int lpm_num_maps; 346 const int lpm_num_modes; 347 const int lpm_res_counter_step_x2; 348 const u32 lpm_sts_latch_en_offset; 349 const u32 lpm_en_offset; 350 const u32 lpm_priority_offset; 351 const u32 lpm_residency_offset; 352 const u32 lpm_status_offset; 353 const u32 lpm_live_status_offset; 354 const u32 etr3_offset; 355 const u8 *lpm_reg_index; 356 const u32 pson_residency_offset; 357 const u32 pson_residency_counter_step; 358 const u32 acpi_pm_tmr_ctl_offset; 359 const u32 acpi_pm_tmr_disable_bit; 360 }; 361 362 /** 363 * struct pmc_info - Structure to keep pmc info 364 * @devid: device id of the pmc device 365 * @map: pointer to a pmc_reg_map struct that contains platform 366 * specific attributes 367 */ 368 struct pmc_info { 369 u32 guid; 370 u16 devid; 371 const struct pmc_reg_map *map; 372 }; 373 374 /** 375 * struct pmc - pmc private info structure 376 * @base_addr: contains pmc base address 377 * @regbase: pointer to io-remapped memory location 378 * @map: pointer to pmc_reg_map struct that contains platform 379 * specific attributes 380 * @lpm_req_regs: List of substate requirements 381 * @ltr_ign: Holds LTR ignore data while suspended 382 * 383 * pmc contains info about one power management controller device. 384 */ 385 struct pmc { 386 u64 base_addr; 387 void __iomem *regbase; 388 const struct pmc_reg_map *map; 389 u32 *lpm_req_regs; 390 u32 ltr_ign; 391 }; 392 393 /** 394 * struct pmc_dev - pmc device structure 395 * @devs: pointer to an array of pmc pointers 396 * @pdev: pointer to platform_device struct 397 * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM 398 * @crystal_freq: crystal frequency from cpuid 399 * @dbgfs_dir: path to debugfs interface 400 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers 401 * used to read MPHY PG and PLL status are available 402 * @mutex_lock: mutex to complete one transcation 403 * @pkgc_res_cnt: Array of PKGC residency counters 404 * @num_of_pkgc: Number of PKGC 405 * @s0ix_counter: S0ix residency (step adjusted) 406 * @num_lpm_modes: Count of enabled modes 407 * @lpm_en_modes: Array of enabled modes from lowest to highest priority 408 * @suspend: Function to perform platform specific suspend 409 * @resume: Function to perform platform specific resume 410 * 411 * pmc_dev contains info about power management controller device. 412 */ 413 struct pmc_dev { 414 struct pmc *pmcs[MAX_NUM_PMC]; 415 struct dentry *dbgfs_dir; 416 struct platform_device *pdev; 417 struct pci_dev *ssram_pcidev; 418 unsigned int crystal_freq; 419 int pmc_xram_read_bit; 420 struct mutex lock; /* generic mutex lock for PMC Core */ 421 422 u64 s0ix_counter; 423 int num_lpm_modes; 424 int lpm_en_modes[LPM_MAX_NUM_MODES]; 425 void (*suspend)(struct pmc_dev *pmcdev); 426 int (*resume)(struct pmc_dev *pmcdev); 427 428 u64 *pkgc_res_cnt; 429 u8 num_of_pkgc; 430 431 bool has_die_c6; 432 u32 die_c6_offset; 433 struct telem_endpoint *punit_ep; 434 struct pmc_info *regmap_list; 435 436 bool enable_acpi_pm_timer_on_resume; 437 }; 438 439 enum pmc_index { 440 PMC_IDX_MAIN, 441 PMC_IDX_SOC = PMC_IDX_MAIN, 442 PMC_IDX_IOE, 443 PMC_IDX_PCH, 444 PMC_IDX_MAX 445 }; 446 447 extern const struct pmc_bit_map msr_map[]; 448 extern const struct pmc_bit_map spt_pll_map[]; 449 extern const struct pmc_bit_map spt_mphy_map[]; 450 extern const struct pmc_bit_map spt_pfear_map[]; 451 extern const struct pmc_bit_map *ext_spt_pfear_map[]; 452 extern const struct pmc_bit_map spt_ltr_show_map[]; 453 extern const struct pmc_reg_map spt_reg_map; 454 extern const struct pmc_bit_map cnp_pfear_map[]; 455 extern const struct pmc_bit_map *ext_cnp_pfear_map[]; 456 extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; 457 extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; 458 extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; 459 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; 460 extern const struct pmc_bit_map cnp_ltr_show_map[]; 461 extern const struct pmc_reg_map cnp_reg_map; 462 extern const struct pmc_bit_map icl_pfear_map[]; 463 extern const struct pmc_bit_map *ext_icl_pfear_map[]; 464 extern const struct pmc_reg_map icl_reg_map; 465 extern const struct pmc_bit_map tgl_pfear_map[]; 466 extern const struct pmc_bit_map *ext_tgl_pfear_map[]; 467 extern const struct pmc_bit_map tgl_clocksource_status_map[]; 468 extern const struct pmc_bit_map tgl_power_gating_status_map[]; 469 extern const struct pmc_bit_map tgl_d3_status_map[]; 470 extern const struct pmc_bit_map tgl_vnn_req_status_map[]; 471 extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; 472 extern const struct pmc_bit_map tgl_signal_status_map[]; 473 extern const struct pmc_bit_map *tgl_lpm_maps[]; 474 extern const struct pmc_reg_map tgl_reg_map; 475 extern const struct pmc_reg_map tgl_h_reg_map; 476 extern const struct pmc_bit_map adl_pfear_map[]; 477 extern const struct pmc_bit_map *ext_adl_pfear_map[]; 478 extern const struct pmc_bit_map adl_ltr_show_map[]; 479 extern const struct pmc_bit_map adl_clocksource_status_map[]; 480 extern const struct pmc_bit_map adl_power_gating_status_0_map[]; 481 extern const struct pmc_bit_map adl_power_gating_status_1_map[]; 482 extern const struct pmc_bit_map adl_power_gating_status_2_map[]; 483 extern const struct pmc_bit_map adl_d3_status_0_map[]; 484 extern const struct pmc_bit_map adl_d3_status_1_map[]; 485 extern const struct pmc_bit_map adl_d3_status_2_map[]; 486 extern const struct pmc_bit_map adl_d3_status_3_map[]; 487 extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; 488 extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; 489 extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; 490 extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; 491 extern const struct pmc_bit_map adl_vnn_misc_status_map[]; 492 extern const struct pmc_bit_map *adl_lpm_maps[]; 493 extern const struct pmc_reg_map adl_reg_map; 494 extern const struct pmc_bit_map mtl_socm_pfear_map[]; 495 extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; 496 extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; 497 extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; 498 extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; 499 extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; 500 extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; 501 extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; 502 extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; 503 extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; 504 extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; 505 extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; 506 extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; 507 extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; 508 extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; 509 extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; 510 extern const struct pmc_bit_map mtl_socm_signal_status_map[]; 511 extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; 512 extern const struct pmc_reg_map mtl_socm_reg_map; 513 extern const struct pmc_bit_map mtl_ioep_pfear_map[]; 514 extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; 515 extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; 516 extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; 517 extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; 518 extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; 519 extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; 520 extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; 521 extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; 522 extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; 523 extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; 524 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; 525 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; 526 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; 527 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; 528 extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; 529 extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; 530 extern const struct pmc_reg_map mtl_ioep_reg_map; 531 extern const struct pmc_bit_map mtl_ioem_pfear_map[]; 532 extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; 533 extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; 534 extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; 535 extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; 536 extern const struct pmc_reg_map mtl_ioem_reg_map; 537 extern const struct pmc_reg_map lnl_socm_reg_map; 538 539 /* LNL */ 540 extern const struct pmc_bit_map lnl_ltr_show_map[]; 541 extern const struct pmc_bit_map lnl_clocksource_status_map[]; 542 extern const struct pmc_bit_map lnl_power_gating_status_0_map[]; 543 extern const struct pmc_bit_map lnl_power_gating_status_1_map[]; 544 extern const struct pmc_bit_map lnl_power_gating_status_2_map[]; 545 extern const struct pmc_bit_map lnl_d3_status_0_map[]; 546 extern const struct pmc_bit_map lnl_d3_status_1_map[]; 547 extern const struct pmc_bit_map lnl_d3_status_2_map[]; 548 extern const struct pmc_bit_map lnl_d3_status_3_map[]; 549 extern const struct pmc_bit_map lnl_vnn_req_status_0_map[]; 550 extern const struct pmc_bit_map lnl_vnn_req_status_1_map[]; 551 extern const struct pmc_bit_map lnl_vnn_req_status_2_map[]; 552 extern const struct pmc_bit_map lnl_vnn_req_status_3_map[]; 553 extern const struct pmc_bit_map lnl_vnn_misc_status_map[]; 554 extern const struct pmc_bit_map *lnl_lpm_maps[]; 555 extern const struct pmc_bit_map *lnl_blk_maps[]; 556 extern const struct pmc_bit_map lnl_pfear_map[]; 557 extern const struct pmc_bit_map *ext_lnl_pfear_map[]; 558 extern const struct pmc_bit_map lnl_signal_status_map[]; 559 560 /* ARL */ 561 extern const struct pmc_bit_map arl_socs_ltr_show_map[]; 562 extern const struct pmc_bit_map arl_socs_clocksource_status_map[]; 563 extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[]; 564 extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[]; 565 extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[]; 566 extern const struct pmc_bit_map arl_socs_d3_status_2_map[]; 567 extern const struct pmc_bit_map arl_socs_d3_status_3_map[]; 568 extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[]; 569 extern const struct pmc_bit_map *arl_socs_lpm_maps[]; 570 extern const struct pmc_bit_map arl_socs_pfear_map[]; 571 extern const struct pmc_bit_map *ext_arl_socs_pfear_map[]; 572 extern const struct pmc_reg_map arl_socs_reg_map; 573 extern const struct pmc_bit_map arl_pchs_ltr_show_map[]; 574 extern const struct pmc_bit_map arl_pchs_clocksource_status_map[]; 575 extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[]; 576 extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[]; 577 extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[]; 578 extern const struct pmc_bit_map arl_pchs_d3_status_0_map[]; 579 extern const struct pmc_bit_map arl_pchs_d3_status_1_map[]; 580 extern const struct pmc_bit_map arl_pchs_d3_status_2_map[]; 581 extern const struct pmc_bit_map arl_pchs_d3_status_3_map[]; 582 extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[]; 583 extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[]; 584 extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[]; 585 extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[]; 586 extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[]; 587 extern const struct pmc_bit_map arl_pchs_signal_status_map[]; 588 extern const struct pmc_bit_map *arl_pchs_lpm_maps[]; 589 extern const struct pmc_reg_map arl_pchs_reg_map; 590 591 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); 592 extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); 593 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore); 594 595 int pmc_core_resume_common(struct pmc_dev *pmcdev); 596 int get_primary_reg_base(struct pmc *pmc); 597 extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); 598 extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); 599 extern void pmc_core_set_device_d3(unsigned int device); 600 601 extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func); 602 603 int spt_core_init(struct pmc_dev *pmcdev); 604 int cnp_core_init(struct pmc_dev *pmcdev); 605 int icl_core_init(struct pmc_dev *pmcdev); 606 int tgl_core_init(struct pmc_dev *pmcdev); 607 int tgl_l_core_init(struct pmc_dev *pmcdev); 608 int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp); 609 int adl_core_init(struct pmc_dev *pmcdev); 610 int mtl_core_init(struct pmc_dev *pmcdev); 611 int arl_core_init(struct pmc_dev *pmcdev); 612 int lnl_core_init(struct pmc_dev *pmcdev); 613 614 void cnl_suspend(struct pmc_dev *pmcdev); 615 int cnl_resume(struct pmc_dev *pmcdev); 616 617 #define pmc_for_each_mode(mode, pmcdev) \ 618 for (unsigned int __i = 0, __cond; \ 619 __cond = __i < (pmcdev)->num_lpm_modes, \ 620 __cond && ((mode) = (pmcdev)->lpm_en_modes[__i]), \ 621 __cond; \ 622 __i++) 623 624 #define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ 625 static int __name ## _open(struct inode *inode, struct file *file) \ 626 { \ 627 return single_open(file, __name ## _show, inode->i_private); \ 628 } \ 629 \ 630 static const struct file_operations __name ## _fops = { \ 631 .owner = THIS_MODULE, \ 632 .open = __name ## _open, \ 633 .read = seq_read, \ 634 .write = __name ## _write, \ 635 .release = single_release, \ 636 } 637 638 #endif /* PMC_CORE_H */ 639