1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI driver for NVIDIA's Tegra114 SPI Controller. 4 * 5 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmapool.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/of.h> 23 #include <linux/reset.h> 24 #include <linux/spi/spi.h> 25 26 #define SPI_COMMAND1 0x000 27 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) 28 #define SPI_PACKED (1 << 5) 29 #define SPI_TX_EN (1 << 11) 30 #define SPI_RX_EN (1 << 12) 31 #define SPI_BOTH_EN_BYTE (1 << 13) 32 #define SPI_BOTH_EN_BIT (1 << 14) 33 #define SPI_LSBYTE_FE (1 << 15) 34 #define SPI_LSBIT_FE (1 << 16) 35 #define SPI_BIDIROE (1 << 17) 36 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18) 37 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18) 38 #define SPI_IDLE_SDA_PULL_LOW (2 << 18) 39 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18) 40 #define SPI_IDLE_SDA_MASK (3 << 18) 41 #define SPI_CS_SW_VAL (1 << 20) 42 #define SPI_CS_SW_HW (1 << 21) 43 /* SPI_CS_POL_INACTIVE bits are default high */ 44 /* n from 0 to 3 */ 45 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n))) 46 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22) 47 48 #define SPI_CS_SEL_0 (0 << 26) 49 #define SPI_CS_SEL_1 (1 << 26) 50 #define SPI_CS_SEL_2 (2 << 26) 51 #define SPI_CS_SEL_3 (3 << 26) 52 #define SPI_CS_SEL_MASK (3 << 26) 53 #define SPI_CS_SEL(x) (((x) & 0x3) << 26) 54 #define SPI_CONTROL_MODE_0 (0 << 28) 55 #define SPI_CONTROL_MODE_1 (1 << 28) 56 #define SPI_CONTROL_MODE_2 (2 << 28) 57 #define SPI_CONTROL_MODE_3 (3 << 28) 58 #define SPI_CONTROL_MODE_MASK (3 << 28) 59 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28) 60 #define SPI_M_S (1 << 30) 61 #define SPI_PIO (1 << 31) 62 63 #define SPI_COMMAND2 0x004 64 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6) 65 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0) 66 67 #define SPI_CS_TIMING1 0x008 68 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold)) 69 #define SPI_CS_SETUP_HOLD(reg, cs, val) \ 70 ((((val) & 0xFFu) << ((cs) * 8)) | \ 71 ((reg) & ~(0xFFu << ((cs) * 8)))) 72 73 #define SPI_CS_TIMING2 0x00C 74 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0) 75 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5) 76 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8) 77 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13) 78 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16) 79 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21) 80 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24) 81 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29) 82 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \ 83 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \ 84 ((reg) & ~(1 << ((cs) * 8 + 5)))) 85 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \ 86 (reg = (((val) & 0x1F) << ((cs) * 8)) | \ 87 ((reg) & ~(0x1F << ((cs) * 8)))) 88 #define MAX_SETUP_HOLD_CYCLES 16 89 #define MAX_INACTIVE_CYCLES 32 90 91 #define SPI_TRANS_STATUS 0x010 92 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF) 93 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF) 94 #define SPI_RDY (1 << 30) 95 96 #define SPI_FIFO_STATUS 0x014 97 #define SPI_RX_FIFO_EMPTY (1 << 0) 98 #define SPI_RX_FIFO_FULL (1 << 1) 99 #define SPI_TX_FIFO_EMPTY (1 << 2) 100 #define SPI_TX_FIFO_FULL (1 << 3) 101 #define SPI_RX_FIFO_UNF (1 << 4) 102 #define SPI_RX_FIFO_OVF (1 << 5) 103 #define SPI_TX_FIFO_UNF (1 << 6) 104 #define SPI_TX_FIFO_OVF (1 << 7) 105 #define SPI_ERR (1 << 8) 106 #define SPI_TX_FIFO_FLUSH (1 << 14) 107 #define SPI_RX_FIFO_FLUSH (1 << 15) 108 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F) 109 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F) 110 #define SPI_FRAME_END (1 << 30) 111 #define SPI_CS_INACTIVE (1 << 31) 112 113 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \ 114 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF) 115 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY) 116 117 #define SPI_TX_DATA 0x018 118 #define SPI_RX_DATA 0x01C 119 120 #define SPI_DMA_CTL 0x020 121 #define SPI_TX_TRIG_1 (0 << 15) 122 #define SPI_TX_TRIG_4 (1 << 15) 123 #define SPI_TX_TRIG_8 (2 << 15) 124 #define SPI_TX_TRIG_16 (3 << 15) 125 #define SPI_TX_TRIG_MASK (3 << 15) 126 #define SPI_RX_TRIG_1 (0 << 19) 127 #define SPI_RX_TRIG_4 (1 << 19) 128 #define SPI_RX_TRIG_8 (2 << 19) 129 #define SPI_RX_TRIG_16 (3 << 19) 130 #define SPI_RX_TRIG_MASK (3 << 19) 131 #define SPI_IE_TX (1 << 28) 132 #define SPI_IE_RX (1 << 29) 133 #define SPI_CONT (1 << 30) 134 #define SPI_DMA (1 << 31) 135 #define SPI_DMA_EN SPI_DMA 136 137 #define SPI_DMA_BLK 0x024 138 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0) 139 140 #define SPI_TX_FIFO 0x108 141 #define SPI_RX_FIFO 0x188 142 #define SPI_INTR_MASK 0x18c 143 #define SPI_INTR_ALL_MASK (0x1fUL << 25) 144 #define MAX_CHIP_SELECT 4 145 #define SPI_FIFO_DEPTH 64 146 #define DATA_DIR_TX (1 << 0) 147 #define DATA_DIR_RX (1 << 1) 148 149 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 150 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) 151 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40) 152 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0) 153 #define MAX_HOLD_CYCLES 16 154 #define SPI_DEFAULT_SPEED 25000000 155 156 struct tegra_spi_soc_data { 157 bool has_intr_mask_reg; 158 }; 159 160 struct tegra_spi_client_data { 161 int tx_clk_tap_delay; 162 int rx_clk_tap_delay; 163 }; 164 165 struct tegra_spi_data { 166 struct device *dev; 167 struct spi_controller *host; 168 spinlock_t lock; 169 170 struct clk *clk; 171 struct reset_control *rst; 172 void __iomem *base; 173 phys_addr_t phys; 174 unsigned irq; 175 u32 cur_speed; 176 177 struct spi_device *cur_spi; 178 struct spi_device *cs_control; 179 unsigned cur_pos; 180 unsigned words_per_32bit; 181 unsigned bytes_per_word; 182 unsigned curr_dma_words; 183 unsigned cur_direction; 184 185 unsigned cur_rx_pos; 186 unsigned cur_tx_pos; 187 188 unsigned dma_buf_size; 189 unsigned max_buf_size; 190 bool is_curr_dma_xfer; 191 bool use_hw_based_cs; 192 193 struct completion rx_dma_complete; 194 struct completion tx_dma_complete; 195 196 u32 tx_status; 197 u32 rx_status; 198 u32 status_reg; 199 bool is_packed; 200 201 u32 command1_reg; 202 u32 dma_control_reg; 203 u32 def_command1_reg; 204 u32 def_command2_reg; 205 u32 spi_cs_timing1; 206 u32 spi_cs_timing2; 207 u8 last_used_cs; 208 209 struct completion xfer_completion; 210 struct spi_transfer *curr_xfer; 211 struct dma_chan *rx_dma_chan; 212 u32 *rx_dma_buf; 213 dma_addr_t rx_dma_phys; 214 struct dma_async_tx_descriptor *rx_dma_desc; 215 216 struct dma_chan *tx_dma_chan; 217 u32 *tx_dma_buf; 218 dma_addr_t tx_dma_phys; 219 struct dma_async_tx_descriptor *tx_dma_desc; 220 const struct tegra_spi_soc_data *soc_data; 221 }; 222 223 static int tegra_spi_runtime_suspend(struct device *dev); 224 static int tegra_spi_runtime_resume(struct device *dev); 225 226 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi, 227 unsigned long reg) 228 { 229 return readl(tspi->base + reg); 230 } 231 232 static inline void tegra_spi_writel(struct tegra_spi_data *tspi, 233 u32 val, unsigned long reg) 234 { 235 writel(val, tspi->base + reg); 236 237 /* Read back register to make sure that register writes completed */ 238 if (reg != SPI_TX_FIFO) 239 readl(tspi->base + SPI_COMMAND1); 240 } 241 242 static void tegra_spi_clear_status(struct tegra_spi_data *tspi) 243 { 244 u32 val; 245 246 /* Write 1 to clear status register */ 247 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS); 248 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS); 249 250 /* Clear fifo status error if any */ 251 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 252 if (val & SPI_ERR) 253 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR, 254 SPI_FIFO_STATUS); 255 } 256 257 static unsigned tegra_spi_calculate_curr_xfer_param( 258 struct spi_device *spi, struct tegra_spi_data *tspi, 259 struct spi_transfer *t) 260 { 261 unsigned remain_len = t->len - tspi->cur_pos; 262 unsigned max_word; 263 unsigned bits_per_word = t->bits_per_word; 264 unsigned max_len; 265 unsigned total_fifo_words; 266 267 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); 268 269 if ((bits_per_word == 8 || bits_per_word == 16 || 270 bits_per_word == 32) && t->len > 3) { 271 tspi->is_packed = true; 272 tspi->words_per_32bit = 32/bits_per_word; 273 } else { 274 tspi->is_packed = false; 275 tspi->words_per_32bit = 1; 276 } 277 278 if (tspi->is_packed) { 279 max_len = min(remain_len, tspi->max_buf_size); 280 tspi->curr_dma_words = max_len/tspi->bytes_per_word; 281 total_fifo_words = (max_len + 3) / 4; 282 } else { 283 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; 284 max_word = min(max_word, tspi->max_buf_size/4); 285 tspi->curr_dma_words = max_word; 286 total_fifo_words = max_word; 287 } 288 return total_fifo_words; 289 } 290 291 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf( 292 struct tegra_spi_data *tspi, struct spi_transfer *t) 293 { 294 unsigned nbytes; 295 unsigned tx_empty_count; 296 u32 fifo_status; 297 unsigned max_n_32bit; 298 unsigned i, count; 299 unsigned int written_words; 300 unsigned fifo_words_left; 301 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 302 303 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 304 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status); 305 306 if (tspi->is_packed) { 307 fifo_words_left = tx_empty_count * tspi->words_per_32bit; 308 written_words = min(fifo_words_left, tspi->curr_dma_words); 309 nbytes = written_words * tspi->bytes_per_word; 310 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 311 for (count = 0; count < max_n_32bit; count++) { 312 u32 x = 0; 313 314 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 315 x |= (u32)(*tx_buf++) << (i * 8); 316 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 317 } 318 319 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; 320 } else { 321 unsigned int write_bytes; 322 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); 323 written_words = max_n_32bit; 324 nbytes = written_words * tspi->bytes_per_word; 325 if (nbytes > t->len - tspi->cur_pos) 326 nbytes = t->len - tspi->cur_pos; 327 write_bytes = nbytes; 328 for (count = 0; count < max_n_32bit; count++) { 329 u32 x = 0; 330 331 for (i = 0; nbytes && (i < tspi->bytes_per_word); 332 i++, nbytes--) 333 x |= (u32)(*tx_buf++) << (i * 8); 334 tegra_spi_writel(tspi, x, SPI_TX_FIFO); 335 } 336 337 tspi->cur_tx_pos += write_bytes; 338 } 339 340 return written_words; 341 } 342 343 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf( 344 struct tegra_spi_data *tspi, struct spi_transfer *t) 345 { 346 unsigned rx_full_count; 347 u32 fifo_status; 348 unsigned i, count; 349 unsigned int read_words = 0; 350 unsigned len; 351 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 352 353 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 354 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status); 355 if (tspi->is_packed) { 356 len = tspi->curr_dma_words * tspi->bytes_per_word; 357 for (count = 0; count < rx_full_count; count++) { 358 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO); 359 360 for (i = 0; len && (i < 4); i++, len--) 361 *rx_buf++ = (x >> i*8) & 0xFF; 362 } 363 read_words += tspi->curr_dma_words; 364 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 365 } else { 366 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 367 u8 bytes_per_word = tspi->bytes_per_word; 368 unsigned int read_bytes; 369 370 len = rx_full_count * bytes_per_word; 371 if (len > t->len - tspi->cur_pos) 372 len = t->len - tspi->cur_pos; 373 read_bytes = len; 374 for (count = 0; count < rx_full_count; count++) { 375 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; 376 377 for (i = 0; len && (i < bytes_per_word); i++, len--) 378 *rx_buf++ = (x >> (i*8)) & 0xFF; 379 } 380 read_words += rx_full_count; 381 tspi->cur_rx_pos += read_bytes; 382 } 383 384 return read_words; 385 } 386 387 static void tegra_spi_copy_client_txbuf_to_spi_txbuf( 388 struct tegra_spi_data *tspi, struct spi_transfer *t) 389 { 390 /* Make the dma buffer to read by cpu */ 391 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 392 tspi->dma_buf_size, DMA_TO_DEVICE); 393 394 if (tspi->is_packed) { 395 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 396 397 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 398 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 399 } else { 400 unsigned int i; 401 unsigned int count; 402 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 403 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 404 unsigned int write_bytes; 405 406 if (consume > t->len - tspi->cur_pos) 407 consume = t->len - tspi->cur_pos; 408 write_bytes = consume; 409 for (count = 0; count < tspi->curr_dma_words; count++) { 410 u32 x = 0; 411 412 for (i = 0; consume && (i < tspi->bytes_per_word); 413 i++, consume--) 414 x |= (u32)(*tx_buf++) << (i * 8); 415 tspi->tx_dma_buf[count] = x; 416 } 417 418 tspi->cur_tx_pos += write_bytes; 419 } 420 421 /* Make the dma buffer to read by dma */ 422 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, 423 tspi->dma_buf_size, DMA_TO_DEVICE); 424 } 425 426 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf( 427 struct tegra_spi_data *tspi, struct spi_transfer *t) 428 { 429 /* Make the dma buffer to read by cpu */ 430 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 431 tspi->dma_buf_size, DMA_FROM_DEVICE); 432 433 if (tspi->is_packed) { 434 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 435 436 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 437 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 438 } else { 439 unsigned int i; 440 unsigned int count; 441 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 442 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 443 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 444 unsigned int read_bytes; 445 446 if (consume > t->len - tspi->cur_pos) 447 consume = t->len - tspi->cur_pos; 448 read_bytes = consume; 449 for (count = 0; count < tspi->curr_dma_words; count++) { 450 u32 x = tspi->rx_dma_buf[count] & rx_mask; 451 452 for (i = 0; consume && (i < tspi->bytes_per_word); 453 i++, consume--) 454 *rx_buf++ = (x >> (i*8)) & 0xFF; 455 } 456 457 tspi->cur_rx_pos += read_bytes; 458 } 459 460 /* Make the dma buffer to read by dma */ 461 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 462 tspi->dma_buf_size, DMA_FROM_DEVICE); 463 } 464 465 static void tegra_spi_dma_complete(void *args) 466 { 467 struct completion *dma_complete = args; 468 469 complete(dma_complete); 470 } 471 472 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len) 473 { 474 reinit_completion(&tspi->tx_dma_complete); 475 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, 476 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, 477 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 478 if (!tspi->tx_dma_desc) { 479 dev_err(tspi->dev, "Not able to get desc for Tx\n"); 480 return -EIO; 481 } 482 483 tspi->tx_dma_desc->callback = tegra_spi_dma_complete; 484 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; 485 486 dmaengine_submit(tspi->tx_dma_desc); 487 dma_async_issue_pending(tspi->tx_dma_chan); 488 return 0; 489 } 490 491 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len) 492 { 493 reinit_completion(&tspi->rx_dma_complete); 494 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, 495 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, 496 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 497 if (!tspi->rx_dma_desc) { 498 dev_err(tspi->dev, "Not able to get desc for Rx\n"); 499 return -EIO; 500 } 501 502 tspi->rx_dma_desc->callback = tegra_spi_dma_complete; 503 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; 504 505 dmaengine_submit(tspi->rx_dma_desc); 506 dma_async_issue_pending(tspi->rx_dma_chan); 507 return 0; 508 } 509 510 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi) 511 { 512 unsigned long timeout = jiffies + HZ; 513 u32 status; 514 515 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 516 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) { 517 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH; 518 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS); 519 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) { 520 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 521 if (time_after(jiffies, timeout)) { 522 dev_err(tspi->dev, 523 "timeout waiting for fifo flush\n"); 524 return -EIO; 525 } 526 527 udelay(1); 528 } 529 } 530 531 return 0; 532 } 533 534 static int tegra_spi_start_dma_based_transfer( 535 struct tegra_spi_data *tspi, struct spi_transfer *t) 536 { 537 u32 val; 538 unsigned int len; 539 int ret = 0; 540 u8 dma_burst; 541 struct dma_slave_config dma_sconfig = {0}; 542 543 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); 544 tegra_spi_writel(tspi, val, SPI_DMA_BLK); 545 546 if (tspi->is_packed) 547 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, 548 4) * 4; 549 else 550 len = tspi->curr_dma_words * 4; 551 552 /* Set attention level based on length of transfer */ 553 if (len & 0xF) { 554 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1; 555 dma_burst = 1; 556 } else if (((len) >> 4) & 0x1) { 557 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4; 558 dma_burst = 4; 559 } else { 560 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8; 561 dma_burst = 8; 562 } 563 564 if (!tspi->soc_data->has_intr_mask_reg) { 565 if (tspi->cur_direction & DATA_DIR_TX) 566 val |= SPI_IE_TX; 567 568 if (tspi->cur_direction & DATA_DIR_RX) 569 val |= SPI_IE_RX; 570 } 571 572 tegra_spi_writel(tspi, val, SPI_DMA_CTL); 573 tspi->dma_control_reg = val; 574 575 dma_sconfig.device_fc = true; 576 if (tspi->cur_direction & DATA_DIR_TX) { 577 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; 578 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 579 dma_sconfig.dst_maxburst = dma_burst; 580 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig); 581 if (ret < 0) { 582 dev_err(tspi->dev, 583 "DMA slave config failed: %d\n", ret); 584 return ret; 585 } 586 587 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t); 588 ret = tegra_spi_start_tx_dma(tspi, len); 589 if (ret < 0) { 590 dev_err(tspi->dev, 591 "Starting tx dma failed, err %d\n", ret); 592 return ret; 593 } 594 } 595 596 if (tspi->cur_direction & DATA_DIR_RX) { 597 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; 598 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 599 dma_sconfig.src_maxburst = dma_burst; 600 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig); 601 if (ret < 0) { 602 dev_err(tspi->dev, 603 "DMA slave config failed: %d\n", ret); 604 return ret; 605 } 606 607 /* Make the dma buffer to read by dma */ 608 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 609 tspi->dma_buf_size, DMA_FROM_DEVICE); 610 611 ret = tegra_spi_start_rx_dma(tspi, len); 612 if (ret < 0) { 613 dev_err(tspi->dev, 614 "Starting rx dma failed, err %d\n", ret); 615 if (tspi->cur_direction & DATA_DIR_TX) 616 dmaengine_terminate_all(tspi->tx_dma_chan); 617 return ret; 618 } 619 } 620 tspi->is_curr_dma_xfer = true; 621 tspi->dma_control_reg = val; 622 623 val |= SPI_DMA_EN; 624 tegra_spi_writel(tspi, val, SPI_DMA_CTL); 625 return ret; 626 } 627 628 static int tegra_spi_start_cpu_based_transfer( 629 struct tegra_spi_data *tspi, struct spi_transfer *t) 630 { 631 u32 val; 632 unsigned cur_words; 633 634 if (tspi->cur_direction & DATA_DIR_TX) 635 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t); 636 else 637 cur_words = tspi->curr_dma_words; 638 639 val = SPI_DMA_BLK_SET(cur_words - 1); 640 tegra_spi_writel(tspi, val, SPI_DMA_BLK); 641 642 val = 0; 643 if (tspi->cur_direction & DATA_DIR_TX) 644 val |= SPI_IE_TX; 645 646 if (tspi->cur_direction & DATA_DIR_RX) 647 val |= SPI_IE_RX; 648 649 tegra_spi_writel(tspi, val, SPI_DMA_CTL); 650 tspi->dma_control_reg = val; 651 652 tspi->is_curr_dma_xfer = false; 653 654 val = tspi->command1_reg; 655 val |= SPI_PIO; 656 tegra_spi_writel(tspi, val, SPI_COMMAND1); 657 return 0; 658 } 659 660 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, 661 bool dma_to_memory) 662 { 663 struct dma_chan *dma_chan; 664 u32 *dma_buf; 665 dma_addr_t dma_phys; 666 667 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); 668 if (IS_ERR(dma_chan)) 669 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), 670 "Dma channel is not available\n"); 671 672 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 673 &dma_phys, GFP_KERNEL); 674 if (!dma_buf) { 675 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); 676 dma_release_channel(dma_chan); 677 return -ENOMEM; 678 } 679 680 if (dma_to_memory) { 681 tspi->rx_dma_chan = dma_chan; 682 tspi->rx_dma_buf = dma_buf; 683 tspi->rx_dma_phys = dma_phys; 684 } else { 685 tspi->tx_dma_chan = dma_chan; 686 tspi->tx_dma_buf = dma_buf; 687 tspi->tx_dma_phys = dma_phys; 688 } 689 return 0; 690 } 691 692 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, 693 bool dma_to_memory) 694 { 695 u32 *dma_buf; 696 dma_addr_t dma_phys; 697 struct dma_chan *dma_chan; 698 699 if (dma_to_memory) { 700 dma_buf = tspi->rx_dma_buf; 701 dma_chan = tspi->rx_dma_chan; 702 dma_phys = tspi->rx_dma_phys; 703 tspi->rx_dma_chan = NULL; 704 tspi->rx_dma_buf = NULL; 705 } else { 706 dma_buf = tspi->tx_dma_buf; 707 dma_chan = tspi->tx_dma_chan; 708 dma_phys = tspi->tx_dma_phys; 709 tspi->tx_dma_buf = NULL; 710 tspi->tx_dma_chan = NULL; 711 } 712 if (!dma_chan) 713 return; 714 715 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 716 dma_release_channel(dma_chan); 717 } 718 719 static int tegra_spi_set_hw_cs_timing(struct spi_device *spi) 720 { 721 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); 722 struct spi_delay *setup = &spi->cs_setup; 723 struct spi_delay *hold = &spi->cs_hold; 724 struct spi_delay *inactive = &spi->cs_inactive; 725 u8 setup_dly, hold_dly; 726 u32 setup_hold; 727 u32 spi_cs_timing; 728 u32 inactive_cycles; 729 u8 cs_state; 730 731 if ((setup->value && setup->unit != SPI_DELAY_UNIT_SCK) || 732 (hold->value && hold->unit != SPI_DELAY_UNIT_SCK) || 733 (inactive->value && inactive->unit != SPI_DELAY_UNIT_SCK)) { 734 dev_err(&spi->dev, 735 "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n", 736 SPI_DELAY_UNIT_SCK); 737 return -EINVAL; 738 } 739 740 setup_dly = min_t(u8, setup->value, MAX_SETUP_HOLD_CYCLES); 741 hold_dly = min_t(u8, hold->value, MAX_SETUP_HOLD_CYCLES); 742 if (setup_dly && hold_dly) { 743 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); 744 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, 745 spi_get_chipselect(spi, 0), 746 setup_hold); 747 if (tspi->spi_cs_timing1 != spi_cs_timing) { 748 tspi->spi_cs_timing1 = spi_cs_timing; 749 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1); 750 } 751 } 752 753 inactive_cycles = min_t(u8, inactive->value, MAX_INACTIVE_CYCLES); 754 if (inactive_cycles) 755 inactive_cycles--; 756 cs_state = inactive_cycles ? 0 : 1; 757 spi_cs_timing = tspi->spi_cs_timing2; 758 SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0), 759 cs_state); 760 SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0), 761 inactive_cycles); 762 if (tspi->spi_cs_timing2 != spi_cs_timing) { 763 tspi->spi_cs_timing2 = spi_cs_timing; 764 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2); 765 } 766 767 return 0; 768 } 769 770 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, 771 struct spi_transfer *t, 772 bool is_first_of_msg, 773 bool is_single_xfer) 774 { 775 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); 776 struct tegra_spi_client_data *cdata = spi->controller_data; 777 u32 speed = t->speed_hz; 778 u8 bits_per_word = t->bits_per_word; 779 u32 command1, command2; 780 int req_mode; 781 u32 tx_tap = 0, rx_tap = 0; 782 783 if (speed != tspi->cur_speed) { 784 clk_set_rate(tspi->clk, speed); 785 tspi->cur_speed = speed; 786 } 787 788 tspi->cur_spi = spi; 789 tspi->cur_pos = 0; 790 tspi->cur_rx_pos = 0; 791 tspi->cur_tx_pos = 0; 792 tspi->curr_xfer = t; 793 794 if (is_first_of_msg) { 795 tegra_spi_clear_status(tspi); 796 797 command1 = tspi->def_command1_reg; 798 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); 799 800 command1 &= ~SPI_CONTROL_MODE_MASK; 801 req_mode = spi->mode & 0x3; 802 if (req_mode == SPI_MODE_0) 803 command1 |= SPI_CONTROL_MODE_0; 804 else if (req_mode == SPI_MODE_1) 805 command1 |= SPI_CONTROL_MODE_1; 806 else if (req_mode == SPI_MODE_2) 807 command1 |= SPI_CONTROL_MODE_2; 808 else if (req_mode == SPI_MODE_3) 809 command1 |= SPI_CONTROL_MODE_3; 810 811 if (spi->mode & SPI_LSB_FIRST) 812 command1 |= SPI_LSBIT_FE; 813 else 814 command1 &= ~SPI_LSBIT_FE; 815 816 if (spi->mode & SPI_3WIRE) 817 command1 |= SPI_BIDIROE; 818 else 819 command1 &= ~SPI_BIDIROE; 820 821 if (tspi->cs_control) { 822 if (tspi->cs_control != spi) 823 tegra_spi_writel(tspi, command1, SPI_COMMAND1); 824 tspi->cs_control = NULL; 825 } else 826 tegra_spi_writel(tspi, command1, SPI_COMMAND1); 827 828 /* GPIO based chip select control */ 829 if (spi_get_csgpiod(spi, 0)) 830 gpiod_set_value(spi_get_csgpiod(spi, 0), 1); 831 832 if (is_single_xfer && !(t->cs_change)) { 833 tspi->use_hw_based_cs = true; 834 command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); 835 } else { 836 tspi->use_hw_based_cs = false; 837 command1 |= SPI_CS_SW_HW; 838 if (spi->mode & SPI_CS_HIGH) 839 command1 |= SPI_CS_SW_VAL; 840 else 841 command1 &= ~SPI_CS_SW_VAL; 842 } 843 844 if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) { 845 if (cdata && cdata->tx_clk_tap_delay) 846 tx_tap = cdata->tx_clk_tap_delay; 847 if (cdata && cdata->rx_clk_tap_delay) 848 rx_tap = cdata->rx_clk_tap_delay; 849 command2 = SPI_TX_TAP_DELAY(tx_tap) | 850 SPI_RX_TAP_DELAY(rx_tap); 851 if (command2 != tspi->def_command2_reg) 852 tegra_spi_writel(tspi, command2, SPI_COMMAND2); 853 tspi->last_used_cs = spi_get_chipselect(spi, 0); 854 } 855 856 } else { 857 command1 = tspi->command1_reg; 858 command1 &= ~SPI_BIT_LENGTH(~0); 859 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); 860 } 861 862 /* 863 * Re-assert the CS GPIO for every transfer: transfer_end() drops it 864 * on cs_change, and the assert above only covers is_first_of_msg. 865 */ 866 if (spi_get_csgpiod(spi, 0)) 867 gpiod_set_value(spi_get_csgpiod(spi, 0), 1); 868 869 return command1; 870 } 871 872 static int tegra_spi_start_transfer_one(struct spi_device *spi, 873 struct spi_transfer *t, u32 command1) 874 { 875 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); 876 unsigned total_fifo_words; 877 int ret; 878 879 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t); 880 881 if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL) 882 command1 |= SPI_BOTH_EN_BIT; 883 else 884 command1 &= ~SPI_BOTH_EN_BIT; 885 886 if (tspi->is_packed) 887 command1 |= SPI_PACKED; 888 else 889 command1 &= ~SPI_PACKED; 890 891 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN); 892 tspi->cur_direction = 0; 893 if (t->rx_buf) { 894 command1 |= SPI_RX_EN; 895 tspi->cur_direction |= DATA_DIR_RX; 896 } 897 if (t->tx_buf) { 898 command1 |= SPI_TX_EN; 899 tspi->cur_direction |= DATA_DIR_TX; 900 } 901 command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0)); 902 tegra_spi_writel(tspi, command1, SPI_COMMAND1); 903 tspi->command1_reg = command1; 904 905 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", 906 tspi->def_command1_reg, (unsigned)command1); 907 908 ret = tegra_spi_flush_fifos(tspi); 909 if (ret < 0) 910 return ret; 911 if (total_fifo_words > SPI_FIFO_DEPTH) 912 ret = tegra_spi_start_dma_based_transfer(tspi, t); 913 else 914 ret = tegra_spi_start_cpu_based_transfer(tspi, t); 915 return ret; 916 } 917 918 static struct tegra_spi_client_data 919 *tegra_spi_parse_cdata_dt(struct spi_device *spi) 920 { 921 struct tegra_spi_client_data *cdata; 922 struct device_node *target_np; 923 924 target_np = spi->dev.of_node; 925 if (!target_np) { 926 dev_dbg(&spi->dev, "device node not found\n"); 927 return NULL; 928 } 929 930 cdata = kzalloc_obj(*cdata); 931 if (!cdata) 932 return NULL; 933 934 of_property_read_u32(target_np, "nvidia,tx-clk-tap-delay", 935 &cdata->tx_clk_tap_delay); 936 of_property_read_u32(target_np, "nvidia,rx-clk-tap-delay", 937 &cdata->rx_clk_tap_delay); 938 return cdata; 939 } 940 941 static void tegra_spi_cleanup(struct spi_device *spi) 942 { 943 struct tegra_spi_client_data *cdata = spi->controller_data; 944 945 spi->controller_data = NULL; 946 if (spi->dev.of_node) 947 kfree(cdata); 948 } 949 950 static int tegra_spi_setup(struct spi_device *spi) 951 { 952 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); 953 struct tegra_spi_client_data *cdata = spi->controller_data; 954 u32 val; 955 unsigned long flags; 956 int ret; 957 958 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 959 spi->bits_per_word, 960 spi->mode & SPI_CPOL ? "" : "~", 961 spi->mode & SPI_CPHA ? "" : "~", 962 spi->max_speed_hz); 963 964 if (!cdata) { 965 cdata = tegra_spi_parse_cdata_dt(spi); 966 spi->controller_data = cdata; 967 } 968 969 ret = pm_runtime_resume_and_get(tspi->dev); 970 if (ret < 0) { 971 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 972 if (cdata) 973 tegra_spi_cleanup(spi); 974 return ret; 975 } 976 977 if (tspi->soc_data->has_intr_mask_reg) { 978 val = tegra_spi_readl(tspi, SPI_INTR_MASK); 979 val &= ~SPI_INTR_ALL_MASK; 980 tegra_spi_writel(tspi, val, SPI_INTR_MASK); 981 } 982 983 spin_lock_irqsave(&tspi->lock, flags); 984 /* GPIO based chip select control */ 985 if (spi_get_csgpiod(spi, 0)) 986 gpiod_set_value(spi_get_csgpiod(spi, 0), 0); 987 988 /* Update default register to include CS polarity and SPI mode */ 989 val = tspi->def_command1_reg; 990 if (spi->mode & SPI_CS_HIGH) 991 val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); 992 else 993 val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); 994 val &= ~SPI_CONTROL_MODE_MASK; 995 val |= SPI_MODE_SEL(spi->mode & 0x3); 996 tspi->def_command1_reg = val; 997 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); 998 spin_unlock_irqrestore(&tspi->lock, flags); 999 1000 pm_runtime_put(tspi->dev); 1001 return 0; 1002 } 1003 1004 static void tegra_spi_transfer_end(struct spi_device *spi) 1005 { 1006 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller); 1007 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; 1008 1009 /* GPIO based chip select control */ 1010 if (spi_get_csgpiod(spi, 0)) 1011 gpiod_set_value(spi_get_csgpiod(spi, 0), 0); 1012 1013 if (!tspi->use_hw_based_cs) { 1014 if (cs_val) 1015 tspi->command1_reg |= SPI_CS_SW_VAL; 1016 else 1017 tspi->command1_reg &= ~SPI_CS_SW_VAL; 1018 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); 1019 } 1020 1021 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); 1022 } 1023 1024 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi) 1025 { 1026 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n"); 1027 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", 1028 tegra_spi_readl(tspi, SPI_COMMAND1), 1029 tegra_spi_readl(tspi, SPI_COMMAND2)); 1030 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", 1031 tegra_spi_readl(tspi, SPI_DMA_CTL), 1032 tegra_spi_readl(tspi, SPI_DMA_BLK)); 1033 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", 1034 tegra_spi_readl(tspi, SPI_TRANS_STATUS), 1035 tegra_spi_readl(tspi, SPI_FIFO_STATUS)); 1036 } 1037 1038 static int tegra_spi_transfer_one_message(struct spi_controller *host, 1039 struct spi_message *msg) 1040 { 1041 bool is_first_msg = true; 1042 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1043 struct spi_transfer *xfer; 1044 struct spi_device *spi = msg->spi; 1045 int ret; 1046 bool skip = false; 1047 int single_xfer; 1048 1049 msg->status = 0; 1050 msg->actual_length = 0; 1051 1052 single_xfer = list_is_singular(&msg->transfers); 1053 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1054 u32 cmd1; 1055 1056 reinit_completion(&tspi->xfer_completion); 1057 1058 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg, 1059 single_xfer); 1060 1061 if (!xfer->len) { 1062 ret = 0; 1063 skip = true; 1064 goto complete_xfer; 1065 } 1066 1067 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1); 1068 if (ret < 0) { 1069 dev_err(tspi->dev, 1070 "spi can not start transfer, err %d\n", ret); 1071 goto complete_xfer; 1072 } 1073 1074 is_first_msg = false; 1075 ret = wait_for_completion_timeout(&tspi->xfer_completion, 1076 SPI_DMA_TIMEOUT); 1077 if (WARN_ON(ret == 0)) { 1078 dev_err(tspi->dev, "spi transfer timeout\n"); 1079 if (tspi->is_curr_dma_xfer && 1080 (tspi->cur_direction & DATA_DIR_TX)) 1081 dmaengine_terminate_all(tspi->tx_dma_chan); 1082 if (tspi->is_curr_dma_xfer && 1083 (tspi->cur_direction & DATA_DIR_RX)) 1084 dmaengine_terminate_all(tspi->rx_dma_chan); 1085 ret = -EIO; 1086 tegra_spi_dump_regs(tspi); 1087 tegra_spi_flush_fifos(tspi); 1088 reset_control_assert(tspi->rst); 1089 udelay(2); 1090 reset_control_deassert(tspi->rst); 1091 tspi->last_used_cs = host->num_chipselect + 1; 1092 goto complete_xfer; 1093 } 1094 1095 if (tspi->tx_status || tspi->rx_status) { 1096 dev_err(tspi->dev, "Error in Transfer\n"); 1097 ret = -EIO; 1098 tegra_spi_dump_regs(tspi); 1099 goto complete_xfer; 1100 } 1101 msg->actual_length += xfer->len; 1102 1103 complete_xfer: 1104 if (ret < 0 || skip) { 1105 tegra_spi_transfer_end(spi); 1106 spi_transfer_delay_exec(xfer); 1107 goto exit; 1108 } else if (list_is_last(&xfer->transfer_list, 1109 &msg->transfers)) { 1110 if (xfer->cs_change) 1111 tspi->cs_control = spi; 1112 else { 1113 tegra_spi_transfer_end(spi); 1114 spi_transfer_delay_exec(xfer); 1115 } 1116 } else if (xfer->cs_change) { 1117 tegra_spi_transfer_end(spi); 1118 spi_transfer_delay_exec(xfer); 1119 } 1120 1121 } 1122 ret = 0; 1123 exit: 1124 msg->status = ret; 1125 spi_finalize_current_message(host); 1126 return ret; 1127 } 1128 1129 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) 1130 { 1131 struct spi_transfer *t = tspi->curr_xfer; 1132 unsigned long flags; 1133 1134 spin_lock_irqsave(&tspi->lock, flags); 1135 if (tspi->tx_status || tspi->rx_status) { 1136 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n", 1137 tspi->status_reg); 1138 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", 1139 tspi->command1_reg, tspi->dma_control_reg); 1140 tegra_spi_dump_regs(tspi); 1141 tegra_spi_flush_fifos(tspi); 1142 complete(&tspi->xfer_completion); 1143 spin_unlock_irqrestore(&tspi->lock, flags); 1144 reset_control_assert(tspi->rst); 1145 udelay(2); 1146 reset_control_deassert(tspi->rst); 1147 return IRQ_HANDLED; 1148 } 1149 1150 if (tspi->cur_direction & DATA_DIR_RX) 1151 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t); 1152 1153 if (tspi->cur_direction & DATA_DIR_TX) 1154 tspi->cur_pos = tspi->cur_tx_pos; 1155 else 1156 tspi->cur_pos = tspi->cur_rx_pos; 1157 1158 if (tspi->cur_pos == t->len) { 1159 complete(&tspi->xfer_completion); 1160 goto exit; 1161 } 1162 1163 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); 1164 tegra_spi_start_cpu_based_transfer(tspi, t); 1165 exit: 1166 spin_unlock_irqrestore(&tspi->lock, flags); 1167 return IRQ_HANDLED; 1168 } 1169 1170 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) 1171 { 1172 struct spi_transfer *t = tspi->curr_xfer; 1173 long wait_status; 1174 int err = 0; 1175 unsigned total_fifo_words; 1176 unsigned long flags; 1177 1178 /* Abort dmas if any error */ 1179 if (tspi->cur_direction & DATA_DIR_TX) { 1180 if (tspi->tx_status) { 1181 dmaengine_terminate_all(tspi->tx_dma_chan); 1182 err += 1; 1183 } else { 1184 wait_status = wait_for_completion_interruptible_timeout( 1185 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT); 1186 if (wait_status <= 0) { 1187 dmaengine_terminate_all(tspi->tx_dma_chan); 1188 dev_err(tspi->dev, "TxDma Xfer failed\n"); 1189 err += 1; 1190 } 1191 } 1192 } 1193 1194 if (tspi->cur_direction & DATA_DIR_RX) { 1195 if (tspi->rx_status) { 1196 dmaengine_terminate_all(tspi->rx_dma_chan); 1197 err += 2; 1198 } else { 1199 wait_status = wait_for_completion_interruptible_timeout( 1200 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT); 1201 if (wait_status <= 0) { 1202 dmaengine_terminate_all(tspi->rx_dma_chan); 1203 dev_err(tspi->dev, "RxDma Xfer failed\n"); 1204 err += 2; 1205 } 1206 } 1207 } 1208 1209 spin_lock_irqsave(&tspi->lock, flags); 1210 if (err) { 1211 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n", 1212 tspi->status_reg); 1213 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", 1214 tspi->command1_reg, tspi->dma_control_reg); 1215 tegra_spi_dump_regs(tspi); 1216 tegra_spi_flush_fifos(tspi); 1217 complete(&tspi->xfer_completion); 1218 spin_unlock_irqrestore(&tspi->lock, flags); 1219 reset_control_assert(tspi->rst); 1220 udelay(2); 1221 reset_control_deassert(tspi->rst); 1222 return IRQ_HANDLED; 1223 } 1224 1225 if (tspi->cur_direction & DATA_DIR_RX) 1226 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t); 1227 1228 if (tspi->cur_direction & DATA_DIR_TX) 1229 tspi->cur_pos = tspi->cur_tx_pos; 1230 else 1231 tspi->cur_pos = tspi->cur_rx_pos; 1232 1233 if (tspi->cur_pos == t->len) { 1234 complete(&tspi->xfer_completion); 1235 goto exit; 1236 } 1237 1238 /* Continue transfer in current message */ 1239 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, 1240 tspi, t); 1241 if (total_fifo_words > SPI_FIFO_DEPTH) 1242 err = tegra_spi_start_dma_based_transfer(tspi, t); 1243 else 1244 err = tegra_spi_start_cpu_based_transfer(tspi, t); 1245 1246 exit: 1247 spin_unlock_irqrestore(&tspi->lock, flags); 1248 return IRQ_HANDLED; 1249 } 1250 1251 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data) 1252 { 1253 struct tegra_spi_data *tspi = context_data; 1254 1255 if (!tspi->is_curr_dma_xfer) 1256 return handle_cpu_based_xfer(tspi); 1257 return handle_dma_based_xfer(tspi); 1258 } 1259 1260 static irqreturn_t tegra_spi_isr(int irq, void *context_data) 1261 { 1262 struct tegra_spi_data *tspi = context_data; 1263 1264 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS); 1265 if (tspi->cur_direction & DATA_DIR_TX) 1266 tspi->tx_status = tspi->status_reg & 1267 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF); 1268 1269 if (tspi->cur_direction & DATA_DIR_RX) 1270 tspi->rx_status = tspi->status_reg & 1271 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF); 1272 tegra_spi_clear_status(tspi); 1273 1274 return IRQ_WAKE_THREAD; 1275 } 1276 1277 static struct tegra_spi_soc_data tegra114_spi_soc_data = { 1278 .has_intr_mask_reg = false, 1279 }; 1280 1281 static struct tegra_spi_soc_data tegra124_spi_soc_data = { 1282 .has_intr_mask_reg = false, 1283 }; 1284 1285 static struct tegra_spi_soc_data tegra210_spi_soc_data = { 1286 .has_intr_mask_reg = true, 1287 }; 1288 1289 static const struct of_device_id tegra_spi_of_match[] = { 1290 { 1291 .compatible = "nvidia,tegra114-spi", 1292 .data = &tegra114_spi_soc_data, 1293 }, { 1294 .compatible = "nvidia,tegra124-spi", 1295 .data = &tegra124_spi_soc_data, 1296 }, { 1297 .compatible = "nvidia,tegra210-spi", 1298 .data = &tegra210_spi_soc_data, 1299 }, 1300 {} 1301 }; 1302 MODULE_DEVICE_TABLE(of, tegra_spi_of_match); 1303 1304 static int tegra_spi_probe(struct platform_device *pdev) 1305 { 1306 struct spi_controller *host; 1307 struct tegra_spi_data *tspi; 1308 struct resource *r; 1309 int ret, spi_irq; 1310 int bus_num; 1311 u32 conflicting_cs; 1312 u32 enabled_child_cs_polarity = 0, disabled_child_cs_low = 0, disabled_child_cs_high = 0; 1313 u32 enabled_cs_mask = 0; 1314 1315 host = devm_spi_alloc_host(&pdev->dev, sizeof(*tspi)); 1316 if (!host) { 1317 dev_err(&pdev->dev, "host allocation failed\n"); 1318 return -ENOMEM; 1319 } 1320 platform_set_drvdata(pdev, host); 1321 tspi = spi_controller_get_devdata(host); 1322 1323 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency", 1324 &host->max_speed_hz)) 1325 host->max_speed_hz = 25000000; /* 25MHz */ 1326 1327 /* the spi->mode bits understood by this driver: */ 1328 host->use_gpio_descriptors = true; 1329 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | 1330 SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; 1331 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1332 host->setup = tegra_spi_setup; 1333 host->cleanup = tegra_spi_cleanup; 1334 host->transfer_one_message = tegra_spi_transfer_one_message; 1335 host->set_cs_timing = tegra_spi_set_hw_cs_timing; 1336 host->num_chipselect = MAX_CHIP_SELECT; 1337 host->auto_runtime_pm = true; 1338 bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); 1339 if (bus_num >= 0) 1340 host->bus_num = bus_num; 1341 1342 tspi->host = host; 1343 tspi->dev = &pdev->dev; 1344 spin_lock_init(&tspi->lock); 1345 1346 tspi->soc_data = of_device_get_match_data(&pdev->dev); 1347 if (!tspi->soc_data) { 1348 dev_err(&pdev->dev, "unsupported tegra\n"); 1349 return -ENODEV; 1350 } 1351 1352 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 1353 if (IS_ERR(tspi->base)) 1354 return PTR_ERR(tspi->base); 1355 1356 tspi->phys = r->start; 1357 1358 spi_irq = platform_get_irq(pdev, 0); 1359 if (spi_irq < 0) 1360 return spi_irq; 1361 1362 tspi->irq = spi_irq; 1363 1364 tspi->clk = devm_clk_get(&pdev->dev, "spi"); 1365 if (IS_ERR(tspi->clk)) { 1366 dev_err(&pdev->dev, "can not get clock\n"); 1367 return PTR_ERR(tspi->clk); 1368 } 1369 1370 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1371 if (IS_ERR(tspi->rst)) { 1372 dev_err(&pdev->dev, "can not get reset\n"); 1373 return PTR_ERR(tspi->rst); 1374 } 1375 1376 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; 1377 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1378 1379 ret = tegra_spi_init_dma_param(tspi, true); 1380 if (ret < 0) 1381 return ret; 1382 ret = tegra_spi_init_dma_param(tspi, false); 1383 if (ret < 0) 1384 goto exit_rx_dma_free; 1385 tspi->max_buf_size = tspi->dma_buf_size; 1386 init_completion(&tspi->tx_dma_complete); 1387 init_completion(&tspi->rx_dma_complete); 1388 1389 init_completion(&tspi->xfer_completion); 1390 1391 pm_runtime_enable(&pdev->dev); 1392 if (!pm_runtime_enabled(&pdev->dev)) { 1393 ret = tegra_spi_runtime_resume(&pdev->dev); 1394 if (ret) 1395 goto exit_pm_disable; 1396 } 1397 1398 ret = pm_runtime_resume_and_get(&pdev->dev); 1399 if (ret < 0) { 1400 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 1401 goto exit_pm_disable; 1402 } 1403 1404 reset_control_assert(tspi->rst); 1405 udelay(2); 1406 reset_control_deassert(tspi->rst); 1407 tspi->def_command1_reg = SPI_M_S; 1408 1409 /* 1410 * SPI_COMMAND1 is written before any child is registered, so a chip 1411 * select with CS_POL_INACTIVE clear stays asserted until 1412 * tegra_spi_setup() runs for that device. Program the level the 1413 * device tree asks for up front instead. 1414 * 1415 * Disabled children are included deliberately. The core never 1416 * registers them, so this is the only chance to park their chip 1417 * select at the level their hardware needs. An enabled child on the 1418 * same CS takes priority. 1419 */ 1420 for_each_child_of_node_scoped(pdev->dev.of_node, np) { 1421 u32 cs; 1422 u32 polarity_bitmask; 1423 u32 cs_polarity = 0; 1424 1425 if (of_property_read_u32(np, "reg", &cs)) 1426 continue; 1427 1428 if (cs >= MAX_CHIP_SELECT) 1429 continue; 1430 1431 polarity_bitmask = SPI_CS_POL_INACTIVE(cs); 1432 if (!of_property_read_bool(np, "spi-cs-high")) 1433 cs_polarity = polarity_bitmask; 1434 1435 if (of_device_is_available(np)) { 1436 enabled_cs_mask |= polarity_bitmask; 1437 enabled_child_cs_polarity |= cs_polarity; 1438 } else { 1439 if (cs_polarity) 1440 disabled_child_cs_low |= polarity_bitmask; 1441 else 1442 disabled_child_cs_high |= polarity_bitmask; 1443 } 1444 } 1445 conflicting_cs = disabled_child_cs_low & disabled_child_cs_high & ~enabled_cs_mask; 1446 for (u32 cs = 0; cs < MAX_CHIP_SELECT; cs++) { 1447 if (SPI_CS_POL_INACTIVE(cs) & conflicting_cs) 1448 dev_warn(&pdev->dev, 1449 "Conflicting CS polarity on disabled nodes at cs %u\n", cs); 1450 } 1451 1452 tspi->def_command1_reg |= enabled_child_cs_polarity | 1453 (disabled_child_cs_low & ~enabled_cs_mask); 1454 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); 1455 tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); 1456 tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); 1457 tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2); 1458 tspi->last_used_cs = host->num_chipselect + 1; 1459 pm_runtime_put(&pdev->dev); 1460 ret = request_threaded_irq(tspi->irq, tegra_spi_isr, 1461 tegra_spi_isr_thread, IRQF_ONESHOT, 1462 dev_name(&pdev->dev), tspi); 1463 if (ret < 0) { 1464 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 1465 tspi->irq); 1466 goto exit_pm_disable; 1467 } 1468 1469 ret = spi_register_controller(host); 1470 if (ret < 0) { 1471 dev_err(&pdev->dev, "can not register to host err %d\n", ret); 1472 goto exit_free_irq; 1473 } 1474 return ret; 1475 1476 exit_free_irq: 1477 free_irq(spi_irq, tspi); 1478 exit_pm_disable: 1479 pm_runtime_disable(&pdev->dev); 1480 if (!pm_runtime_status_suspended(&pdev->dev)) 1481 tegra_spi_runtime_suspend(&pdev->dev); 1482 tegra_spi_deinit_dma_param(tspi, false); 1483 exit_rx_dma_free: 1484 tegra_spi_deinit_dma_param(tspi, true); 1485 1486 return ret; 1487 } 1488 1489 static void tegra_spi_remove(struct platform_device *pdev) 1490 { 1491 struct spi_controller *host = platform_get_drvdata(pdev); 1492 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1493 1494 spi_unregister_controller(host); 1495 1496 free_irq(tspi->irq, tspi); 1497 1498 if (tspi->tx_dma_chan) 1499 tegra_spi_deinit_dma_param(tspi, false); 1500 1501 if (tspi->rx_dma_chan) 1502 tegra_spi_deinit_dma_param(tspi, true); 1503 1504 pm_runtime_disable(&pdev->dev); 1505 if (!pm_runtime_status_suspended(&pdev->dev)) 1506 tegra_spi_runtime_suspend(&pdev->dev); 1507 } 1508 1509 static int tegra_spi_suspend(struct device *dev) 1510 { 1511 struct spi_controller *host = dev_get_drvdata(dev); 1512 1513 return spi_controller_suspend(host); 1514 } 1515 1516 static int tegra_spi_resume(struct device *dev) 1517 { 1518 struct spi_controller *host = dev_get_drvdata(dev); 1519 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1520 int ret; 1521 1522 ret = pm_runtime_resume_and_get(dev); 1523 if (ret < 0) { 1524 dev_err(dev, "pm runtime failed, e = %d\n", ret); 1525 return ret; 1526 } 1527 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); 1528 tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); 1529 tspi->last_used_cs = host->num_chipselect + 1; 1530 pm_runtime_put(dev); 1531 1532 return spi_controller_resume(host); 1533 } 1534 1535 static int tegra_spi_runtime_suspend(struct device *dev) 1536 { 1537 struct spi_controller *host = dev_get_drvdata(dev); 1538 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1539 1540 /* Flush all write which are in PPSB queue by reading back */ 1541 tegra_spi_readl(tspi, SPI_COMMAND1); 1542 1543 clk_disable_unprepare(tspi->clk); 1544 return 0; 1545 } 1546 1547 static int tegra_spi_runtime_resume(struct device *dev) 1548 { 1549 struct spi_controller *host = dev_get_drvdata(dev); 1550 struct tegra_spi_data *tspi = spi_controller_get_devdata(host); 1551 int ret; 1552 1553 ret = clk_prepare_enable(tspi->clk); 1554 if (ret < 0) { 1555 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); 1556 return ret; 1557 } 1558 return 0; 1559 } 1560 1561 static const struct dev_pm_ops tegra_spi_pm_ops = { 1562 RUNTIME_PM_OPS(tegra_spi_runtime_suspend, 1563 tegra_spi_runtime_resume, NULL) 1564 SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume) 1565 }; 1566 static struct platform_driver tegra_spi_driver = { 1567 .driver = { 1568 .name = "spi-tegra114", 1569 .pm = pm_ptr(&tegra_spi_pm_ops), 1570 .of_match_table = tegra_spi_of_match, 1571 }, 1572 .probe = tegra_spi_probe, 1573 .remove = tegra_spi_remove, 1574 }; 1575 module_platform_driver(tegra_spi_driver); 1576 1577 MODULE_ALIAS("platform:spi-tegra114"); 1578 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver"); 1579 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1580 MODULE_LICENSE("GPL v2"); 1581