1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2001 - 2008 Tensilica Inc. 7 * Copyright (C) 2015 Cadence Design Systems Inc. 8 */ 9 10 #ifndef _XTENSA_PROCESSOR_H 11 #define _XTENSA_PROCESSOR_H 12 13 #include <asm/core.h> 14 15 #include <linux/compiler.h> 16 #include <linux/stringify.h> 17 18 #include <asm/bootparam.h> 19 #include <asm/ptrace.h> 20 #include <asm/types.h> 21 #include <asm/regs.h> 22 23 #define ARCH_SLAB_MINALIGN XTENSA_STACK_ALIGNMENT 24 25 /* 26 * User space process size: 1 GB. 27 * Windowed call ABI requires caller and callee to be located within the same 28 * 1 GB region. The C compiler places trampoline code on the stack for sources 29 * that take the address of a nested C function (a feature used by glibc), so 30 * the 1 GB requirement applies to the stack as well. 31 */ 32 33 #ifdef CONFIG_MMU 34 #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) 35 #else 36 #define TASK_SIZE __XTENSA_UL_CONST(0xffffffff) 37 #endif 38 39 #define STACK_TOP TASK_SIZE 40 #define STACK_TOP_MAX STACK_TOP 41 42 /* 43 * General exception cause assigned to fake NMI. Fake NMI needs to be handled 44 * differently from other interrupts, but it uses common kernel entry/exit 45 * code. 46 */ 47 48 #define EXCCAUSE_MAPPED_NMI 62 49 50 /* 51 * General exception cause assigned to debug exceptions. Debug exceptions go 52 * to their own vector, rather than the general exception vectors (user, 53 * kernel, double); and their specific causes are reported via DEBUGCAUSE 54 * rather than EXCCAUSE. However it is sometimes convenient to redirect debug 55 * exceptions to the general exception mechanism. To do this, an otherwise 56 * unused EXCCAUSE value was assigned to debug exceptions for this purpose. 57 */ 58 59 #define EXCCAUSE_MAPPED_DEBUG 63 60 61 /* 62 * We use DEPC also as a flag to distinguish between double and regular 63 * exceptions. For performance reasons, DEPC might contain the value of 64 * EXCCAUSE for regular exceptions, so we use this definition to mark a 65 * valid double exception address. 66 * (Note: We use it in bgeui, so it should be 64, 128, or 256) 67 */ 68 69 #define VALID_DOUBLE_EXCEPTION_ADDRESS 64 70 71 #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno) 72 #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL 73 74 #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) 75 #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) 76 77 #define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l) 78 #define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK) 79 80 #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) 81 82 /* LOCKLEVEL defines the interrupt level that masks all 83 * general-purpose interrupts. 84 */ 85 #if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT) 86 #define LOCKLEVEL (PROFILING_INTLEVEL - 1) 87 #else 88 #define LOCKLEVEL XCHAL_EXCM_LEVEL 89 #endif 90 91 #define TOPLEVEL XCHAL_EXCM_LEVEL 92 #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) 93 94 /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE 95 * registers 96 */ 97 #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */ 98 #define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */ 99 100 #if defined(__XTENSA_WINDOWED_ABI__) 101 #define KERNEL_PS_WOE_MASK PS_WOE_MASK 102 #elif defined(__XTENSA_CALL0_ABI__) 103 #define KERNEL_PS_WOE_MASK 0 104 #else 105 #error Unsupported xtensa ABI 106 #endif 107 108 #ifndef __ASSEMBLY__ 109 110 #if defined(__XTENSA_WINDOWED_ABI__) 111 112 /* Build a valid return address for the specified call winsize. 113 * winsize must be 1 (call4), 2 (call8), or 3 (call12) 114 */ 115 #define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30) 116 117 /* Convert return address to a valid pc 118 * Note: 'text' is the address within the same 1GB range as the ra 119 */ 120 #define MAKE_PC_FROM_RA(ra, text) (((ra) & 0x3fffffff) | ((unsigned long)(text) & 0xc0000000)) 121 122 #elif defined(__XTENSA_CALL0_ABI__) 123 124 /* Build a valid return address for the specified call winsize. 125 * winsize must be 1 (call4), 2 (call8), or 3 (call12) 126 */ 127 #define MAKE_RA_FOR_CALL(ra, ws) (ra) 128 129 /* Convert return address to a valid pc 130 * Note: 'text' is not used as 'ra' is always the full address 131 */ 132 #define MAKE_PC_FROM_RA(ra, text) (ra) 133 134 #else 135 #error Unsupported Xtensa ABI 136 #endif 137 138 /* Spill slot location for the register reg in the spill area under the stack 139 * pointer sp. reg must be in the range [0..4). 140 */ 141 #define SPILL_SLOT(sp, reg) (*(((unsigned long *)(sp)) - 4 + (reg))) 142 143 /* Spill slot location for the register reg in the spill area under the stack 144 * pointer sp for the call8. reg must be in the range [4..8). 145 */ 146 #define SPILL_SLOT_CALL8(sp, reg) (*(((unsigned long *)(sp)) - 12 + (reg))) 147 148 /* Spill slot location for the register reg in the spill area under the stack 149 * pointer sp for the call12. reg must be in the range [4..12). 150 */ 151 #define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg))) 152 153 struct thread_struct { 154 155 /* kernel's return address and stack pointer for context switching */ 156 unsigned long ra; /* kernel's a0: return address and window call size */ 157 unsigned long sp; /* kernel's a1: stack pointer */ 158 159 #ifdef CONFIG_HAVE_HW_BREAKPOINT 160 struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK]; 161 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK]; 162 #endif 163 } __aligned(16); 164 165 /* This decides where the kernel will search for a free chunk of vm 166 * space during mmap's. 167 */ 168 #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) 169 170 #define INIT_THREAD \ 171 { \ 172 ra: 0, \ 173 sp: sizeof(init_stack) + (long) &init_stack, \ 174 } 175 176 177 /* 178 * Do necessary setup to start up a newly executed thread. 179 * Note: When windowed ABI is used for userspace we set-up ps 180 * as if we did a call4 to the new pc. 181 * set_thread_state in signal.c depends on it. 182 */ 183 #if IS_ENABLED(CONFIG_USER_ABI_CALL0) 184 #define USER_PS_VALUE ((USER_RING << PS_RING_SHIFT) | \ 185 (1 << PS_UM_BIT) | \ 186 (1 << PS_EXCM_BIT)) 187 #else 188 #define USER_PS_VALUE (PS_WOE_MASK | \ 189 (1 << PS_CALLINC_SHIFT) | \ 190 (USER_RING << PS_RING_SHIFT) | \ 191 (1 << PS_UM_BIT) | \ 192 (1 << PS_EXCM_BIT)) 193 #endif 194 195 /* Clearing a0 terminates the backtrace. */ 196 #define start_thread(regs, new_pc, new_sp) \ 197 do { \ 198 unsigned long syscall = (regs)->syscall; \ 199 unsigned long current_aregs[16]; \ 200 memcpy(current_aregs, (regs)->areg, sizeof(current_aregs)); \ 201 memset((regs), 0, sizeof(*(regs))); \ 202 (regs)->pc = (new_pc); \ 203 (regs)->ps = USER_PS_VALUE; \ 204 memcpy((regs)->areg, current_aregs, sizeof(current_aregs)); \ 205 (regs)->areg[1] = (new_sp); \ 206 (regs)->areg[0] = 0; \ 207 (regs)->wmask = 1; \ 208 (regs)->depc = 0; \ 209 (regs)->windowbase = 0; \ 210 (regs)->windowstart = 1; \ 211 (regs)->syscall = syscall; \ 212 } while (0) 213 214 /* Forward declaration */ 215 struct task_struct; 216 struct mm_struct; 217 218 extern unsigned long __get_wchan(struct task_struct *p); 219 220 void init_arch(bp_tag_t *bp_start); 221 void do_notify_resume(struct pt_regs *regs); 222 223 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 224 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1]) 225 226 #define cpu_relax() barrier() 227 228 /* Special register access. */ 229 230 #define xtensa_set_sr(x, sr) \ 231 ({ \ 232 __asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \ 233 "a"((unsigned int)(x))); \ 234 }) 235 236 #define xtensa_get_sr(sr) \ 237 ({ \ 238 unsigned int v; \ 239 __asm__ __volatile__ ("rsr %0, "__stringify(sr) : "=a"(v)); \ 240 v; \ 241 }) 242 243 #define xtensa_xsr(x, sr) \ 244 ({ \ 245 unsigned int __v__ = (unsigned int)(x); \ 246 __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \ 247 __v__; \ 248 }) 249 250 #if XCHAL_HAVE_EXTERN_REGS 251 252 static inline void set_er(unsigned long value, unsigned long addr) 253 { 254 asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory"); 255 } 256 257 static inline unsigned long get_er(unsigned long addr) 258 { 259 register unsigned long value; 260 asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory"); 261 return value; 262 } 263 264 #endif /* XCHAL_HAVE_EXTERN_REGS */ 265 266 #endif /* __ASSEMBLY__ */ 267 #endif /* _XTENSA_PROCESSOR_H */ 268