1 /* 2 * Driver for Amlogic Meson SPI communication controller (SPICC) 3 * 4 * Copyright (C) BayLibre, SAS 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/spi/spi.h> 20 #include <linux/types.h> 21 #include <linux/interrupt.h> 22 #include <linux/reset.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/dma-mapping.h> 25 26 /* 27 * There are two modes for data transmission: PIO and DMA. 28 * When bits_per_word is 8, 16, 24, or 32, data is transferred using PIO mode. 29 * When bits_per_word is 64, DMA mode is used by default. 30 * 31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made 32 * up of one or more DMA bursts. The DMA burst implementation mechanism is, 33 * For TX, when the number of words in TXFIFO is less than the preset 34 * reading threshold, SPICC starts a reading DMA burst, which reads the preset 35 * number of words from TX buffer, then writes them into TXFIFO. 36 * For RX, when the number of words in RXFIFO is greater than the preset 37 * writing threshold, SPICC starts a writing request burst, which reads the 38 * preset number of words from RXFIFO, then write them into RX buffer. 39 * DMA works if the transfer meets the following conditions, 40 * - 64 bits per word 41 * - The transfer length in word must be multiples of the dma_burst_len, and 42 * the dma_burst_len should be one of 8,7...2, otherwise, it will be split 43 * into several SPI bursts by this driver 44 */ 45 46 #define SPICC_MAX_BURST 128 47 48 /* Register Map */ 49 #define SPICC_RXDATA 0x00 50 51 #define SPICC_TXDATA 0x04 52 53 #define SPICC_CONREG 0x08 54 #define SPICC_ENABLE BIT(0) 55 #define SPICC_MODE_MASTER BIT(1) 56 #define SPICC_XCH BIT(2) 57 #define SPICC_SMC BIT(3) 58 #define SPICC_POL BIT(4) 59 #define SPICC_PHA BIT(5) 60 #define SPICC_SSCTL BIT(6) 61 #define SPICC_SSPOL BIT(7) 62 #define SPICC_DRCTL_MASK GENMASK(9, 8) 63 #define SPICC_DRCTL_IGNORE 0 64 #define SPICC_DRCTL_FALLING 1 65 #define SPICC_DRCTL_LOWLEVEL 2 66 #define SPICC_CS_MASK GENMASK(13, 12) 67 #define SPICC_DATARATE_MASK GENMASK(18, 16) 68 #define SPICC_DATARATE_DIV4 0 69 #define SPICC_DATARATE_DIV8 1 70 #define SPICC_DATARATE_DIV16 2 71 #define SPICC_DATARATE_DIV32 3 72 #define SPICC_BITLENGTH_MASK GENMASK(24, 19) 73 #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25) 74 75 #define SPICC_INTREG 0x0c 76 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */ 77 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 78 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */ 79 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */ 80 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 81 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ 82 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ 83 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ 84 85 #define SPICC_DMAREG 0x10 86 #define SPICC_DMA_ENABLE BIT(0) 87 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1) 88 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6) 89 #define SPICC_READ_BURST_MASK GENMASK(14, 11) 90 #define SPICC_WRITE_BURST_MASK GENMASK(18, 15) 91 #define SPICC_DMA_URGENT BIT(19) 92 #define SPICC_DMA_THREADID_MASK GENMASK(25, 20) 93 #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26) 94 95 #define SPICC_STATREG 0x14 96 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */ 97 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ 98 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */ 99 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */ 100 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ 101 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ 102 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ 103 #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ 104 105 #define SPICC_PERIODREG 0x18 106 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */ 107 108 #define SPICC_TESTREG 0x1c 109 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */ 110 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */ 111 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */ 112 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ 113 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */ 114 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ 115 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ 116 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ 117 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ 118 #define SPICC_MO_NO_DELAY 0 119 #define SPICC_MO_DELAY_1_CYCLE 1 120 #define SPICC_MO_DELAY_2_CYCLE 2 121 #define SPICC_MO_DELAY_3_CYCLE 3 122 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ 123 #define SPICC_MI_NO_DELAY 0 124 #define SPICC_MI_DELAY_1_CYCLE 1 125 #define SPICC_MI_DELAY_2_CYCLE 2 126 #define SPICC_MI_DELAY_3_CYCLE 3 127 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ 128 #define SPICC_CAP_AHEAD_2_CYCLE 0 129 #define SPICC_CAP_AHEAD_1_CYCLE 1 130 #define SPICC_CAP_NO_DELAY 2 131 #define SPICC_CAP_DELAY_1_CYCLE 3 132 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ 133 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ 134 135 #define SPICC_DRADDR 0x20 /* Read Address of DMA */ 136 137 #define SPICC_DWADDR 0x24 /* Write Address of DMA */ 138 139 #define SPICC_LD_CNTL0 0x28 140 #define VSYNC_IRQ_SRC_SELECT BIT(0) 141 #define DMA_EN_SET_BY_VSYNC BIT(2) 142 #define XCH_EN_SET_BY_VSYNC BIT(3) 143 #define DMA_READ_COUNTER_EN BIT(4) 144 #define DMA_WRITE_COUNTER_EN BIT(5) 145 #define DMA_RADDR_LOAD_BY_VSYNC BIT(6) 146 #define DMA_WADDR_LOAD_BY_VSYNC BIT(7) 147 #define DMA_ADDR_LOAD_FROM_LD_ADDR BIT(8) 148 149 #define SPICC_LD_CNTL1 0x2c 150 #define DMA_READ_COUNTER GENMASK(15, 0) 151 #define DMA_WRITE_COUNTER GENMASK(31, 16) 152 #define DMA_BURST_LEN_DEFAULT 8 153 #define DMA_BURST_COUNT_MAX 0xffff 154 #define SPI_BURST_LEN_MAX (DMA_BURST_LEN_DEFAULT * DMA_BURST_COUNT_MAX) 155 156 #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ 157 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) 158 #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) 159 #define SPICC_ENH_DATARATE_EN BIT(24) 160 #define SPICC_ENH_MOSI_OEN BIT(25) 161 #define SPICC_ENH_CLK_OEN BIT(26) 162 #define SPICC_ENH_CS_OEN BIT(27) 163 #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) 164 #define SPICC_ENH_MAIN_CLK_AO BIT(29) 165 166 #define writel_bits_relaxed(mask, val, addr) \ 167 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 168 169 struct meson_spicc_data { 170 unsigned int max_speed_hz; 171 unsigned int min_speed_hz; 172 unsigned int fifo_size; 173 bool has_oen; 174 bool has_enhance_clk_div; 175 bool has_pclk; 176 }; 177 178 struct meson_spicc_device { 179 struct spi_controller *host; 180 struct platform_device *pdev; 181 void __iomem *base; 182 struct clk *core; 183 struct clk *pclk; 184 struct clk_divider pow2_div; 185 struct clk *clk; 186 struct spi_message *message; 187 struct spi_transfer *xfer; 188 struct completion done; 189 const struct meson_spicc_data *data; 190 u8 *tx_buf; 191 u8 *rx_buf; 192 unsigned int bytes_per_word; 193 unsigned long tx_remain; 194 unsigned long rx_remain; 195 unsigned long xfer_remain; 196 struct pinctrl *pinctrl; 197 struct pinctrl_state *pins_idle_high; 198 struct pinctrl_state *pins_idle_low; 199 dma_addr_t tx_dma; 200 dma_addr_t rx_dma; 201 bool using_dma; 202 }; 203 204 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) 205 206 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) 207 { 208 u32 conf; 209 210 if (!spicc->data->has_oen) { 211 /* Try to get pinctrl states for idle high/low */ 212 spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl, 213 "idle-high"); 214 if (IS_ERR(spicc->pins_idle_high)) { 215 dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n"); 216 spicc->pins_idle_high = NULL; 217 } 218 spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl, 219 "idle-low"); 220 if (IS_ERR(spicc->pins_idle_low)) { 221 dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n"); 222 spicc->pins_idle_low = NULL; 223 } 224 return; 225 } 226 227 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | 228 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; 229 230 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); 231 } 232 233 static int meson_spicc_dma_map(struct meson_spicc_device *spicc, 234 struct spi_transfer *t) 235 { 236 struct device *dev = spicc->host->dev.parent; 237 238 if (!(t->tx_buf && t->rx_buf)) 239 return -EINVAL; 240 241 t->tx_dma = dma_map_single(dev, (void *)t->tx_buf, t->len, DMA_TO_DEVICE); 242 if (dma_mapping_error(dev, t->tx_dma)) 243 return -ENOMEM; 244 245 t->rx_dma = dma_map_single(dev, t->rx_buf, t->len, DMA_FROM_DEVICE); 246 if (dma_mapping_error(dev, t->rx_dma)) 247 return -ENOMEM; 248 249 spicc->tx_dma = t->tx_dma; 250 spicc->rx_dma = t->rx_dma; 251 252 return 0; 253 } 254 255 static void meson_spicc_dma_unmap(struct meson_spicc_device *spicc, 256 struct spi_transfer *t) 257 { 258 struct device *dev = spicc->host->dev.parent; 259 260 if (t->tx_dma) 261 dma_unmap_single(dev, t->tx_dma, t->len, DMA_TO_DEVICE); 262 if (t->rx_dma) 263 dma_unmap_single(dev, t->rx_dma, t->len, DMA_FROM_DEVICE); 264 } 265 266 /* 267 * According to the remain words length, calculate a suitable spi burst length 268 * and a dma burst length for current spi burst 269 */ 270 static u32 meson_spicc_calc_dma_len(struct meson_spicc_device *spicc, 271 u32 len, u32 *dma_burst_len) 272 { 273 u32 i; 274 275 if (len <= spicc->data->fifo_size) { 276 *dma_burst_len = len; 277 return len; 278 } 279 280 *dma_burst_len = DMA_BURST_LEN_DEFAULT; 281 282 if (len == (SPI_BURST_LEN_MAX + 1)) 283 return SPI_BURST_LEN_MAX - DMA_BURST_LEN_DEFAULT; 284 285 if (len >= SPI_BURST_LEN_MAX) 286 return SPI_BURST_LEN_MAX; 287 288 for (i = DMA_BURST_LEN_DEFAULT; i > 1; i--) 289 if ((len % i) == 0) { 290 *dma_burst_len = i; 291 return len; 292 } 293 294 i = len % DMA_BURST_LEN_DEFAULT; 295 len -= i; 296 297 if (i == 1) 298 len -= DMA_BURST_LEN_DEFAULT; 299 300 return len; 301 } 302 303 static void meson_spicc_setup_dma(struct meson_spicc_device *spicc) 304 { 305 unsigned int len; 306 unsigned int dma_burst_len, dma_burst_count; 307 unsigned int count_en = 0; 308 unsigned int txfifo_thres = 0; 309 unsigned int read_req = 0; 310 unsigned int rxfifo_thres = 31; 311 unsigned int write_req = 0; 312 unsigned int ld_ctr1 = 0; 313 314 writel_relaxed(spicc->tx_dma, spicc->base + SPICC_DRADDR); 315 writel_relaxed(spicc->rx_dma, spicc->base + SPICC_DWADDR); 316 317 /* Set the max burst length to support a transmission with length of 318 * no more than 1024 bytes(128 words), which must use the CS management 319 * because of some strict timing requirements 320 */ 321 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, SPICC_BURSTLENGTH_MASK, 322 spicc->base + SPICC_CONREG); 323 324 len = meson_spicc_calc_dma_len(spicc, spicc->xfer_remain, 325 &dma_burst_len); 326 spicc->xfer_remain -= len; 327 dma_burst_count = DIV_ROUND_UP(len, dma_burst_len); 328 dma_burst_len--; 329 330 if (spicc->tx_dma) { 331 spicc->tx_dma += len; 332 count_en |= DMA_READ_COUNTER_EN; 333 txfifo_thres = spicc->data->fifo_size - dma_burst_len; 334 read_req = dma_burst_len; 335 ld_ctr1 |= FIELD_PREP(DMA_READ_COUNTER, dma_burst_count); 336 } 337 338 if (spicc->rx_dma) { 339 spicc->rx_dma += len; 340 count_en |= DMA_WRITE_COUNTER_EN; 341 rxfifo_thres = dma_burst_len; 342 write_req = dma_burst_len; 343 ld_ctr1 |= FIELD_PREP(DMA_WRITE_COUNTER, dma_burst_count); 344 } 345 346 writel_relaxed(count_en, spicc->base + SPICC_LD_CNTL0); 347 writel_relaxed(ld_ctr1, spicc->base + SPICC_LD_CNTL1); 348 writel_relaxed(SPICC_DMA_ENABLE 349 | SPICC_DMA_URGENT 350 | FIELD_PREP(SPICC_TXFIFO_THRESHOLD_MASK, txfifo_thres) 351 | FIELD_PREP(SPICC_READ_BURST_MASK, read_req) 352 | FIELD_PREP(SPICC_RXFIFO_THRESHOLD_MASK, rxfifo_thres) 353 | FIELD_PREP(SPICC_WRITE_BURST_MASK, write_req), 354 spicc->base + SPICC_DMAREG); 355 } 356 357 static irqreturn_t meson_spicc_dma_irq(struct meson_spicc_device *spicc) 358 { 359 if (readl_relaxed(spicc->base + SPICC_DMAREG) & SPICC_DMA_ENABLE) 360 return IRQ_HANDLED; 361 362 if (spicc->xfer_remain) { 363 meson_spicc_setup_dma(spicc); 364 } else { 365 writel_bits_relaxed(SPICC_SMC, 0, spicc->base + SPICC_CONREG); 366 writel_relaxed(0, spicc->base + SPICC_INTREG); 367 writel_relaxed(0, spicc->base + SPICC_DMAREG); 368 meson_spicc_dma_unmap(spicc, spicc->xfer); 369 complete(&spicc->done); 370 } 371 372 return IRQ_HANDLED; 373 } 374 375 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) 376 { 377 return !!FIELD_GET(SPICC_TF, 378 readl_relaxed(spicc->base + SPICC_STATREG)); 379 } 380 381 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) 382 { 383 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, 384 readl_relaxed(spicc->base + SPICC_STATREG)); 385 } 386 387 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc) 388 { 389 unsigned int bytes = spicc->bytes_per_word; 390 unsigned int byte_shift = 0; 391 u32 data = 0; 392 u8 byte; 393 394 while (bytes--) { 395 byte = *spicc->tx_buf++; 396 data |= (byte & 0xff) << byte_shift; 397 byte_shift += 8; 398 } 399 400 spicc->tx_remain--; 401 return data; 402 } 403 404 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc, 405 u32 data) 406 { 407 unsigned int bytes = spicc->bytes_per_word; 408 unsigned int byte_shift = 0; 409 u8 byte; 410 411 while (bytes--) { 412 byte = (data >> byte_shift) & 0xff; 413 *spicc->rx_buf++ = byte; 414 byte_shift += 8; 415 } 416 417 spicc->rx_remain--; 418 } 419 420 static inline void meson_spicc_rx(struct meson_spicc_device *spicc) 421 { 422 /* Empty RX FIFO */ 423 while (spicc->rx_remain && 424 meson_spicc_rxready(spicc)) 425 meson_spicc_push_data(spicc, 426 readl_relaxed(spicc->base + SPICC_RXDATA)); 427 } 428 429 static inline void meson_spicc_tx(struct meson_spicc_device *spicc) 430 { 431 /* Fill Up TX FIFO */ 432 while (spicc->tx_remain && 433 !meson_spicc_txfull(spicc)) 434 writel_relaxed(meson_spicc_pull_data(spicc), 435 spicc->base + SPICC_TXDATA); 436 } 437 438 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) 439 { 440 441 unsigned int burst_len = min_t(unsigned int, 442 spicc->xfer_remain / 443 spicc->bytes_per_word, 444 spicc->data->fifo_size); 445 /* Setup Xfer variables */ 446 spicc->tx_remain = burst_len; 447 spicc->rx_remain = burst_len; 448 spicc->xfer_remain -= burst_len * spicc->bytes_per_word; 449 450 /* Setup burst length */ 451 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, 452 FIELD_PREP(SPICC_BURSTLENGTH_MASK, 453 burst_len - 1), 454 spicc->base + SPICC_CONREG); 455 456 /* Fill TX FIFO */ 457 meson_spicc_tx(spicc); 458 } 459 460 static irqreturn_t meson_spicc_irq(int irq, void *data) 461 { 462 struct meson_spicc_device *spicc = (void *) data; 463 464 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); 465 466 if (spicc->using_dma) 467 return meson_spicc_dma_irq(spicc); 468 469 /* Empty RX FIFO */ 470 meson_spicc_rx(spicc); 471 472 if (!spicc->xfer_remain) { 473 /* Disable all IRQs */ 474 writel(0, spicc->base + SPICC_INTREG); 475 476 complete(&spicc->done); 477 478 return IRQ_HANDLED; 479 } 480 481 /* Setup burst */ 482 meson_spicc_setup_burst(spicc); 483 484 /* Start burst */ 485 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 486 487 return IRQ_HANDLED; 488 } 489 490 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) 491 { 492 u32 div, hz; 493 u32 mi_delay, cap_delay; 494 u32 conf; 495 496 if (spicc->data->has_enhance_clk_div) { 497 div = FIELD_GET(SPICC_ENH_DATARATE_MASK, 498 readl_relaxed(spicc->base + SPICC_ENH_CTL0)); 499 div++; 500 div <<= 1; 501 } else { 502 div = FIELD_GET(SPICC_DATARATE_MASK, 503 readl_relaxed(spicc->base + SPICC_CONREG)); 504 div += 2; 505 div = 1 << div; 506 } 507 508 mi_delay = SPICC_MI_NO_DELAY; 509 cap_delay = SPICC_CAP_AHEAD_2_CYCLE; 510 hz = clk_get_rate(spicc->clk); 511 512 if (hz >= 100000000) 513 cap_delay = SPICC_CAP_DELAY_1_CYCLE; 514 else if (hz >= 80000000) 515 cap_delay = SPICC_CAP_NO_DELAY; 516 else if (hz >= 40000000) 517 cap_delay = SPICC_CAP_AHEAD_1_CYCLE; 518 else if (div >= 16) 519 mi_delay = SPICC_MI_DELAY_3_CYCLE; 520 else if (div >= 8) 521 mi_delay = SPICC_MI_DELAY_2_CYCLE; 522 else if (div >= 6) 523 mi_delay = SPICC_MI_DELAY_1_CYCLE; 524 525 conf = readl_relaxed(spicc->base + SPICC_TESTREG); 526 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK 527 | SPICC_MI_CAP_DELAY_MASK); 528 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); 529 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); 530 writel_relaxed(conf, spicc->base + SPICC_TESTREG); 531 } 532 533 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, 534 struct spi_transfer *xfer) 535 { 536 u32 conf, conf_orig; 537 538 /* Read original configuration */ 539 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); 540 541 /* Setup word width */ 542 FIELD_MODIFY(SPICC_BITLENGTH_MASK, &conf, 543 (spicc->bytes_per_word << 3) - 1); 544 545 /* Ignore if unchanged */ 546 if (conf != conf_orig) 547 writel_relaxed(conf, spicc->base + SPICC_CONREG); 548 549 clk_set_rate(spicc->clk, xfer->speed_hz); 550 551 meson_spicc_auto_io_delay(spicc); 552 553 writel_relaxed(0, spicc->base + SPICC_DMAREG); 554 } 555 556 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) 557 { 558 if (spicc->data->has_oen) 559 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 560 SPICC_ENH_MAIN_CLK_AO, 561 spicc->base + SPICC_ENH_CTL0); 562 563 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, 564 spicc->base + SPICC_TESTREG); 565 566 while (meson_spicc_rxready(spicc)) 567 readl_relaxed(spicc->base + SPICC_RXDATA); 568 569 if (spicc->data->has_oen) 570 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, 571 spicc->base + SPICC_ENH_CTL0); 572 } 573 574 static int meson_spicc_transfer_one(struct spi_controller *host, 575 struct spi_device *spi, 576 struct spi_transfer *xfer) 577 { 578 struct meson_spicc_device *spicc = spi_controller_get_devdata(host); 579 uint64_t timeout; 580 581 /* Store current transfer */ 582 spicc->xfer = xfer; 583 584 /* Setup transfer parameters */ 585 spicc->tx_buf = (u8 *)xfer->tx_buf; 586 spicc->rx_buf = (u8 *)xfer->rx_buf; 587 spicc->xfer_remain = xfer->len; 588 589 /* Pre-calculate word size */ 590 spicc->bytes_per_word = 591 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); 592 593 if (xfer->len % spicc->bytes_per_word) 594 return -EINVAL; 595 596 /* Setup transfer parameters */ 597 meson_spicc_setup_xfer(spicc, xfer); 598 599 meson_spicc_reset_fifo(spicc); 600 601 /* Setup wait for completion */ 602 reinit_completion(&spicc->done); 603 604 /* For each byte we wait for 8 cycles of the SPI clock */ 605 timeout = 8LL * MSEC_PER_SEC * xfer->len; 606 do_div(timeout, xfer->speed_hz); 607 608 /* Add 10us delay between each fifo bursts */ 609 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC; 610 611 /* Increase it twice and add 200 ms tolerance */ 612 timeout += timeout + 200; 613 614 if (xfer->bits_per_word == 64) { 615 int ret; 616 617 /* dma_burst_len 1 can't trigger a dma burst */ 618 if (xfer->len < 16) 619 return -EINVAL; 620 621 ret = meson_spicc_dma_map(spicc, xfer); 622 if (ret) { 623 meson_spicc_dma_unmap(spicc, xfer); 624 dev_err(host->dev.parent, "dma map failed\n"); 625 return ret; 626 } 627 628 spicc->using_dma = true; 629 spicc->xfer_remain = DIV_ROUND_UP(xfer->len, spicc->bytes_per_word); 630 meson_spicc_setup_dma(spicc); 631 writel_relaxed(SPICC_TE_EN, spicc->base + SPICC_INTREG); 632 writel_bits_relaxed(SPICC_SMC, SPICC_SMC, spicc->base + SPICC_CONREG); 633 } else { 634 spicc->using_dma = false; 635 /* Setup burst */ 636 meson_spicc_setup_burst(spicc); 637 638 /* Start burst */ 639 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 640 641 /* Enable interrupts */ 642 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); 643 } 644 645 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout))) 646 return -ETIMEDOUT; 647 648 return 0; 649 } 650 651 static int meson_spicc_prepare_message(struct spi_controller *host, 652 struct spi_message *message) 653 { 654 struct meson_spicc_device *spicc = spi_controller_get_devdata(host); 655 struct spi_device *spi = message->spi; 656 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; 657 658 /* Store current message */ 659 spicc->message = message; 660 661 /* Enable Master */ 662 conf |= SPICC_ENABLE; 663 conf |= SPICC_MODE_MASTER; 664 665 /* SMC = 0 */ 666 667 /* Setup transfer mode */ 668 if (spi->mode & SPI_CPOL) 669 conf |= SPICC_POL; 670 else 671 conf &= ~SPICC_POL; 672 673 if (!spicc->data->has_oen) { 674 if (spi->mode & SPI_CPOL) { 675 if (spicc->pins_idle_high) 676 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high); 677 } else { 678 if (spicc->pins_idle_low) 679 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low); 680 } 681 } 682 683 if (spi->mode & SPI_CPHA) 684 conf |= SPICC_PHA; 685 else 686 conf &= ~SPICC_PHA; 687 688 /* SSCTL = 0 */ 689 690 if (spi->mode & SPI_CS_HIGH) 691 conf |= SPICC_SSPOL; 692 else 693 conf &= ~SPICC_SSPOL; 694 695 if (spi->mode & SPI_READY) 696 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL); 697 else 698 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE); 699 700 /* Select CS */ 701 conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0)); 702 703 /* Default 8bit word */ 704 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); 705 706 writel_relaxed(conf, spicc->base + SPICC_CONREG); 707 708 /* Setup no wait cycles by default */ 709 writel_relaxed(0, spicc->base + SPICC_PERIODREG); 710 711 writel_bits_relaxed(SPICC_LBC_W1, 712 spi->mode & SPI_LOOP ? SPICC_LBC_W1 : 0, 713 spicc->base + SPICC_TESTREG); 714 715 return 0; 716 } 717 718 static int meson_spicc_unprepare_transfer(struct spi_controller *host) 719 { 720 struct meson_spicc_device *spicc = spi_controller_get_devdata(host); 721 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; 722 723 /* Disable all IRQs */ 724 writel(0, spicc->base + SPICC_INTREG); 725 726 device_reset_optional(&spicc->pdev->dev); 727 728 /* Set default configuration, keeping datarate field */ 729 writel_relaxed(conf, spicc->base + SPICC_CONREG); 730 731 if (!spicc->data->has_oen) 732 pinctrl_select_default_state(&spicc->pdev->dev); 733 734 return 0; 735 } 736 737 static int meson_spicc_setup(struct spi_device *spi) 738 { 739 if (!spi->controller_state) 740 spi->controller_state = spi_controller_get_devdata(spi->controller); 741 742 /* DMA works at 64 bits, the rest works on PIO */ 743 if (spi->bits_per_word != 8 && 744 spi->bits_per_word != 16 && 745 spi->bits_per_word != 24 && 746 spi->bits_per_word != 32 && 747 spi->bits_per_word != 64) 748 return -EINVAL; 749 750 return 0; 751 } 752 753 static void meson_spicc_cleanup(struct spi_device *spi) 754 { 755 spi->controller_state = NULL; 756 } 757 758 /* 759 * The Clock Mux 760 * x-----------------x x------------x x------\ 761 * |---| pow2 fixed div |---| pow2 div |----| | 762 * | x-----------------x x------------x | | 763 * src ---| | mux |-- out 764 * | x-----------------x x------------x | | 765 * |---| enh fixed div |---| enh div |0---| | 766 * x-----------------x x------------x x------/ 767 * 768 * Clk path for GX series: 769 * src -> pow2 fixed div -> pow2 div -> out 770 * 771 * Clk path for AXG series: 772 * src -> pow2 fixed div -> pow2 div -> mux -> out 773 * src -> enh fixed div -> enh div -> mux -> out 774 * 775 * Clk path for G12A series: 776 * pclk -> pow2 fixed div -> pow2 div -> mux -> out 777 * pclk -> enh fixed div -> enh div -> mux -> out 778 * 779 * The pow2 divider is tied to the controller HW state, and the 780 * divider is only valid when the controller is initialized. 781 * 782 * A set of clock ops is added to make sure we don't read/set this 783 * clock rate while the controller is in an unknown state. 784 */ 785 786 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw, 787 unsigned long parent_rate) 788 { 789 struct clk_divider *divider = to_clk_divider(hw); 790 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 791 792 if (!spicc->host->cur_msg) 793 return 0; 794 795 return clk_divider_ops.recalc_rate(hw, parent_rate); 796 } 797 798 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw, 799 struct clk_rate_request *req) 800 { 801 struct clk_divider *divider = to_clk_divider(hw); 802 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 803 804 if (!spicc->host->cur_msg) 805 return -EINVAL; 806 807 return clk_divider_ops.determine_rate(hw, req); 808 } 809 810 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate, 811 unsigned long parent_rate) 812 { 813 struct clk_divider *divider = to_clk_divider(hw); 814 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider); 815 816 if (!spicc->host->cur_msg) 817 return -EINVAL; 818 819 return clk_divider_ops.set_rate(hw, rate, parent_rate); 820 } 821 822 static const struct clk_ops meson_spicc_pow2_clk_ops = { 823 .recalc_rate = meson_spicc_pow2_recalc_rate, 824 .determine_rate = meson_spicc_pow2_determine_rate, 825 .set_rate = meson_spicc_pow2_set_rate, 826 }; 827 828 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc) 829 { 830 struct device *dev = &spicc->pdev->dev; 831 struct clk_fixed_factor *pow2_fixed_div; 832 struct clk_init_data init; 833 struct clk *clk; 834 struct clk_parent_data parent_data[2]; 835 char name[64]; 836 837 memset(&init, 0, sizeof(init)); 838 memset(&parent_data, 0, sizeof(parent_data)); 839 840 init.parent_data = parent_data; 841 842 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ 843 844 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); 845 if (!pow2_fixed_div) 846 return -ENOMEM; 847 848 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); 849 init.name = name; 850 init.ops = &clk_fixed_factor_ops; 851 if (spicc->data->has_pclk) { 852 init.flags = CLK_SET_RATE_PARENT; 853 parent_data[0].hw = __clk_get_hw(spicc->pclk); 854 } else { 855 init.flags = 0; 856 parent_data[0].hw = __clk_get_hw(spicc->core); 857 } 858 init.num_parents = 1; 859 860 pow2_fixed_div->mult = 1; 861 pow2_fixed_div->div = 4; 862 pow2_fixed_div->hw.init = &init; 863 864 clk = devm_clk_register(dev, &pow2_fixed_div->hw); 865 if (WARN_ON(IS_ERR(clk))) 866 return PTR_ERR(clk); 867 868 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); 869 init.name = name; 870 init.ops = &meson_spicc_pow2_clk_ops; 871 /* 872 * Set NOCACHE here to make sure we read the actual HW value 873 * since we reset the HW after each transfer. 874 */ 875 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; 876 parent_data[0].hw = &pow2_fixed_div->hw; 877 init.num_parents = 1; 878 879 spicc->pow2_div.shift = 16; 880 spicc->pow2_div.width = 3; 881 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO; 882 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; 883 spicc->pow2_div.hw.init = &init; 884 885 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw); 886 if (WARN_ON(IS_ERR(spicc->clk))) 887 return PTR_ERR(spicc->clk); 888 889 return 0; 890 } 891 892 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc) 893 { 894 struct device *dev = &spicc->pdev->dev; 895 struct clk_fixed_factor *enh_fixed_div; 896 struct clk_divider *enh_div; 897 struct clk_mux *mux; 898 struct clk_init_data init; 899 struct clk *clk; 900 struct clk_parent_data parent_data[2]; 901 char name[64]; 902 903 memset(&init, 0, sizeof(init)); 904 memset(&parent_data, 0, sizeof(parent_data)); 905 906 init.parent_data = parent_data; 907 908 /* algorithm for enh div: rate = freq / 2 / (N + 1) */ 909 910 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); 911 if (!enh_fixed_div) 912 return -ENOMEM; 913 914 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); 915 init.name = name; 916 init.ops = &clk_fixed_factor_ops; 917 if (spicc->data->has_pclk) { 918 init.flags = CLK_SET_RATE_PARENT; 919 parent_data[0].hw = __clk_get_hw(spicc->pclk); 920 } else { 921 init.flags = 0; 922 parent_data[0].hw = __clk_get_hw(spicc->core); 923 } 924 init.num_parents = 1; 925 926 enh_fixed_div->mult = 1; 927 enh_fixed_div->div = 2; 928 enh_fixed_div->hw.init = &init; 929 930 clk = devm_clk_register(dev, &enh_fixed_div->hw); 931 if (WARN_ON(IS_ERR(clk))) 932 return PTR_ERR(clk); 933 934 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); 935 if (!enh_div) 936 return -ENOMEM; 937 938 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); 939 init.name = name; 940 init.ops = &clk_divider_ops; 941 init.flags = CLK_SET_RATE_PARENT; 942 parent_data[0].hw = &enh_fixed_div->hw; 943 init.num_parents = 1; 944 945 enh_div->shift = 16; 946 enh_div->width = 8; 947 enh_div->reg = spicc->base + SPICC_ENH_CTL0; 948 enh_div->hw.init = &init; 949 950 clk = devm_clk_register(dev, &enh_div->hw); 951 if (WARN_ON(IS_ERR(clk))) 952 return PTR_ERR(clk); 953 954 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 955 if (!mux) 956 return -ENOMEM; 957 958 snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); 959 init.name = name; 960 init.ops = &clk_mux_ops; 961 parent_data[0].hw = &spicc->pow2_div.hw; 962 parent_data[1].hw = &enh_div->hw; 963 init.num_parents = 2; 964 init.flags = CLK_SET_RATE_PARENT; 965 966 mux->mask = 0x1; 967 mux->shift = 24; 968 mux->reg = spicc->base + SPICC_ENH_CTL0; 969 mux->hw.init = &init; 970 971 spicc->clk = devm_clk_register(dev, &mux->hw); 972 if (WARN_ON(IS_ERR(spicc->clk))) 973 return PTR_ERR(spicc->clk); 974 975 return 0; 976 } 977 978 static int meson_spicc_probe(struct platform_device *pdev) 979 { 980 struct spi_controller *host; 981 struct meson_spicc_device *spicc; 982 int ret, irq; 983 984 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spicc)); 985 if (!host) { 986 dev_err(&pdev->dev, "host allocation failed\n"); 987 return -ENOMEM; 988 } 989 spicc = spi_controller_get_devdata(host); 990 spicc->host = host; 991 992 spicc->data = of_device_get_match_data(&pdev->dev); 993 if (!spicc->data) { 994 dev_err(&pdev->dev, "failed to get match data\n"); 995 return -EINVAL; 996 } 997 998 spicc->pdev = pdev; 999 platform_set_drvdata(pdev, spicc); 1000 1001 init_completion(&spicc->done); 1002 1003 spicc->base = devm_platform_ioremap_resource(pdev, 0); 1004 if (IS_ERR(spicc->base)) { 1005 dev_err(&pdev->dev, "io resource mapping failed\n"); 1006 return PTR_ERR(spicc->base); 1007 } 1008 1009 /* Set master mode and enable controller */ 1010 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, 1011 spicc->base + SPICC_CONREG); 1012 1013 /* Disable all IRQs */ 1014 writel_relaxed(0, spicc->base + SPICC_INTREG); 1015 1016 irq = platform_get_irq(pdev, 0); 1017 if (irq < 0) 1018 return irq; 1019 1020 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, 1021 0, NULL, spicc); 1022 if (ret) { 1023 dev_err(&pdev->dev, "irq request failed\n"); 1024 return ret; 1025 } 1026 1027 spicc->core = devm_clk_get_enabled(&pdev->dev, "core"); 1028 if (IS_ERR(spicc->core)) { 1029 dev_err(&pdev->dev, "core clock request failed\n"); 1030 return PTR_ERR(spicc->core); 1031 } 1032 1033 if (spicc->data->has_pclk) { 1034 spicc->pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); 1035 if (IS_ERR(spicc->pclk)) { 1036 dev_err(&pdev->dev, "pclk clock request failed\n"); 1037 return PTR_ERR(spicc->pclk); 1038 } 1039 } 1040 1041 spicc->pinctrl = devm_pinctrl_get(&pdev->dev); 1042 if (IS_ERR(spicc->pinctrl)) 1043 return PTR_ERR(spicc->pinctrl); 1044 1045 device_reset_optional(&pdev->dev); 1046 1047 host->num_chipselect = 4; 1048 host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LOOP; 1049 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX); 1050 host->min_speed_hz = spicc->data->min_speed_hz; 1051 host->max_speed_hz = spicc->data->max_speed_hz; 1052 host->setup = meson_spicc_setup; 1053 host->cleanup = meson_spicc_cleanup; 1054 host->prepare_message = meson_spicc_prepare_message; 1055 host->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; 1056 host->transfer_one = meson_spicc_transfer_one; 1057 host->use_gpio_descriptors = true; 1058 1059 meson_spicc_oen_enable(spicc); 1060 1061 ret = meson_spicc_pow2_clk_init(spicc); 1062 if (ret) { 1063 dev_err(&pdev->dev, "pow2 clock registration failed\n"); 1064 return ret; 1065 } 1066 1067 if (spicc->data->has_enhance_clk_div) { 1068 ret = meson_spicc_enh_clk_init(spicc); 1069 if (ret) { 1070 dev_err(&pdev->dev, "clock registration failed\n"); 1071 return ret; 1072 } 1073 } 1074 1075 ret = spi_register_controller(host); 1076 if (ret) { 1077 dev_err(&pdev->dev, "spi registration failed\n"); 1078 return ret; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static void meson_spicc_remove(struct platform_device *pdev) 1085 { 1086 struct meson_spicc_device *spicc = platform_get_drvdata(pdev); 1087 1088 spi_unregister_controller(spicc->host); 1089 1090 /* Disable SPI */ 1091 writel(0, spicc->base + SPICC_CONREG); 1092 } 1093 1094 static const struct meson_spicc_data meson_spicc_gx_data = { 1095 .max_speed_hz = 30000000, 1096 .min_speed_hz = 325000, 1097 .fifo_size = 16, 1098 }; 1099 1100 static const struct meson_spicc_data meson_spicc_axg_data = { 1101 .max_speed_hz = 80000000, 1102 .min_speed_hz = 325000, 1103 .fifo_size = 16, 1104 .has_oen = true, 1105 .has_enhance_clk_div = true, 1106 }; 1107 1108 static const struct meson_spicc_data meson_spicc_g12a_data = { 1109 .max_speed_hz = 166666666, 1110 .min_speed_hz = 50000, 1111 .fifo_size = 15, 1112 .has_oen = true, 1113 .has_enhance_clk_div = true, 1114 .has_pclk = true, 1115 }; 1116 1117 static const struct of_device_id meson_spicc_of_match[] = { 1118 { 1119 .compatible = "amlogic,meson-gx-spicc", 1120 .data = &meson_spicc_gx_data, 1121 }, 1122 { 1123 .compatible = "amlogic,meson-axg-spicc", 1124 .data = &meson_spicc_axg_data, 1125 }, 1126 { 1127 .compatible = "amlogic,meson-g12a-spicc", 1128 .data = &meson_spicc_g12a_data, 1129 }, 1130 { /* sentinel */ } 1131 }; 1132 MODULE_DEVICE_TABLE(of, meson_spicc_of_match); 1133 1134 static struct platform_driver meson_spicc_driver = { 1135 .probe = meson_spicc_probe, 1136 .remove = meson_spicc_remove, 1137 .driver = { 1138 .name = "meson-spicc", 1139 .of_match_table = of_match_ptr(meson_spicc_of_match), 1140 }, 1141 }; 1142 1143 module_platform_driver(meson_spicc_driver); 1144 1145 MODULE_DESCRIPTION("Meson SPI Communication Controller driver"); 1146 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 1147 MODULE_LICENSE("GPL"); 1148