1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com>
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/i2c.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16
17 /* spacemit i2c registers */
18 #define SPACEMIT_ICR 0x0 /* Control register */
19 #define SPACEMIT_ISR 0x4 /* Status register */
20 #define SPACEMIT_IDBR 0xc /* Data buffer register */
21 #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */
22 #define SPACEMIT_ILCR 0x10 /* Load Count Register */
23 #define SPACEMIT_IWCR 0x14 /* Wait Count Register */
24 #define SPACEMIT_IBMR 0x1c /* Bus monitor register */
25
26 /* SPACEMIT_ICR register fields */
27 #define SPACEMIT_CR_START BIT(0) /* start bit */
28 #define SPACEMIT_CR_STOP BIT(1) /* stop bit */
29 #define SPACEMIT_CR_ACKNAK BIT(2) /* send ACK(0) or NAK(1) */
30 #define SPACEMIT_CR_TB BIT(3) /* transfer byte bit */
31 /* Bits 4-7 are reserved */
32 #define SPACEMIT_CR_MODE_FAST BIT(8) /* bus mode (master operation) */
33 /* Bit 9 is reserved */
34 #define SPACEMIT_CR_UR BIT(10) /* unit reset */
35 #define SPACEMIT_CR_RSTREQ BIT(11) /* i2c bus reset request */
36 /* Bit 12 is reserved */
37 #define SPACEMIT_CR_SCLE BIT(13) /* master clock enable */
38 #define SPACEMIT_CR_IUE BIT(14) /* unit enable */
39 /* Bits 15-17 are reserved */
40 #define SPACEMIT_CR_ALDIE BIT(18) /* enable arbitration interrupt */
41 #define SPACEMIT_CR_DTEIE BIT(19) /* enable TX interrupts */
42 #define SPACEMIT_CR_DRFIE BIT(20) /* enable RX interrupts */
43 #define SPACEMIT_CR_GCD BIT(21) /* general call disable */
44 #define SPACEMIT_CR_BEIE BIT(22) /* enable bus error ints */
45 /* Bits 23-24 are reserved */
46 #define SPACEMIT_CR_MSDIE BIT(25) /* master STOP detected int enable */
47 #define SPACEMIT_CR_MSDE BIT(26) /* master STOP detected enable */
48 #define SPACEMIT_CR_TXDONEIE BIT(27) /* transaction done int enable */
49 #define SPACEMIT_CR_TXEIE BIT(28) /* transmit FIFO empty int enable */
50 #define SPACEMIT_CR_RXHFIE BIT(29) /* receive FIFO half-full int enable */
51 #define SPACEMIT_CR_RXFIE BIT(30) /* receive FIFO full int enable */
52 #define SPACEMIT_CR_RXOVIE BIT(31) /* receive FIFO overrun int enable */
53
54 #define SPACEMIT_I2C_INT_CTRL_MASK (SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \
55 SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \
56 SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \
57 SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \
58 SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE)
59
60 /* SPACEMIT_ISR register fields */
61 /* Bits 0-13 are reserved */
62 #define SPACEMIT_SR_ACKNAK BIT(14) /* ACK/NACK status */
63 #define SPACEMIT_SR_UB BIT(15) /* unit busy */
64 #define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */
65 #define SPACEMIT_SR_EBB BIT(17) /* early bus busy */
66 #define SPACEMIT_SR_ALD BIT(18) /* arbitration loss detected */
67 #define SPACEMIT_SR_ITE BIT(19) /* TX buffer empty */
68 #define SPACEMIT_SR_IRF BIT(20) /* RX buffer full */
69 #define SPACEMIT_SR_GCAD BIT(21) /* general call address detected */
70 #define SPACEMIT_SR_BED BIT(22) /* bus error no ACK/NAK */
71 #define SPACEMIT_SR_SAD BIT(23) /* slave address detected */
72 #define SPACEMIT_SR_SSD BIT(24) /* slave stop detected */
73 /* Bit 25 is reserved */
74 #define SPACEMIT_SR_MSD BIT(26) /* master stop detected */
75 #define SPACEMIT_SR_TXDONE BIT(27) /* transaction done */
76 #define SPACEMIT_SR_TXE BIT(28) /* TX FIFO empty */
77 #define SPACEMIT_SR_RXHF BIT(29) /* RX FIFO half-full */
78 #define SPACEMIT_SR_RXF BIT(30) /* RX FIFO full */
79 #define SPACEMIT_SR_RXOV BIT(31) /* RX FIFO overrun */
80
81 #define SPACEMIT_I2C_INT_STATUS_MASK (SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \
82 SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \
83 SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \
84 SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \
85 SPACEMIT_SR_ALD)
86
87 #define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */
88 /* the cycles of SCL during bus reset */
89 #define SPACEMIT_RCR_FIELD_RST_CYC GENMASK(3, 0)
90
91 /* SPACEMIT_IBMR register fields */
92 #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */
93 #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */
94
95 #define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0)
96 #define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9)
97
98 /* SPACEMIT_IWCR register fields */
99 #define SPACEMIT_WCR_COUNT GENMASK(4, 0)
100 #define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5)
101 #define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10)
102
103 /* Required by I2C IP for correct SCL timing */
104 #define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \
105 FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \
106 FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5))
107
108 /* i2c bus recover timeout: us */
109 #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000
110
111 #define SPACEMIT_SR_ERR (SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD)
112
113 #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9
114
115 #define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */
116 #define SPACEMIT_POLL_TIMEOUT 1000 /* us */
117 #define SPACEMIT_POLL_INTERVAL 30 /* us */
118
119 enum spacemit_i2c_state {
120 SPACEMIT_STATE_IDLE,
121 SPACEMIT_STATE_START,
122 SPACEMIT_STATE_READ,
123 SPACEMIT_STATE_WRITE,
124 };
125
126 enum spacemit_i2c_mode {
127 SPACEMIT_MODE_STANDARD,
128 SPACEMIT_MODE_FAST
129 };
130
131 /* i2c-spacemit driver's main struct */
132 struct spacemit_i2c_dev {
133 struct device *dev;
134 struct i2c_adapter adapt;
135
136 struct clk_hw scl_clk_hw;
137 struct clk *scl_clk;
138 enum spacemit_i2c_mode mode;
139
140 /* hardware resources */
141 void __iomem *base;
142 int irq;
143 u32 clock_freq;
144
145 struct i2c_msg *msgs;
146 u32 msg_num;
147
148 /* index of the current message being processed */
149 u32 msg_idx;
150 u8 *msg_buf;
151 /* the number of unprocessed bytes remaining in the current message */
152 u32 unprocessed;
153
154 enum spacemit_i2c_state state;
155 bool read;
156 bool use_pio;
157 struct completion complete;
158 u32 status;
159 };
160
spacemit_i2c_scl_clk_disable_unprepare(void * data)161 static void spacemit_i2c_scl_clk_disable_unprepare(void *data)
162 {
163 clk_disable_unprepare(data);
164 }
165
166 /*
167 * Calculate the ILCR divider value (lv) from the target SCL rate.
168 *
169 * Hardware timing formulas:
170 * - standard mode: SCL = FCLK / (2 * SLV + 8)
171 * - fast mode: SCL = FCLK / (2 * FLV + 10)
172 */
spacemit_i2c_calc_lv(struct spacemit_i2c_dev * i2c,unsigned long parent_rate,unsigned long target_rate)173 static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c,
174 unsigned long parent_rate,
175 unsigned long target_rate)
176 {
177 u32 offset, denom;
178
179 offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10;
180 denom = DIV_ROUND_CLOSEST(parent_rate, target_rate);
181
182 return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2);
183 }
184
spacemit_i2c_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)185 static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate,
186 unsigned long parent_rate)
187 {
188 struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
189 u32 lv, lcr, mask;
190
191 lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate);
192
193 mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ?
194 SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK;
195
196 lcr = readl(i2c->base + SPACEMIT_ILCR);
197 lcr &= ~mask;
198 lcr |= field_prep(mask, lv);
199 writel(lcr, i2c->base + SPACEMIT_ILCR);
200
201 return 0;
202 }
203
spacemit_i2c_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)204 static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw,
205 struct clk_rate_request *req)
206 {
207 struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
208 u32 lv, offset;
209
210 lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate);
211 offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10;
212 req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset);
213
214 return 0;
215 }
216
spacemit_i2c_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)217 static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw,
218 unsigned long parent_rate)
219 {
220 struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
221 u32 lcr, lv = 0;
222
223 lcr = readl(i2c->base + SPACEMIT_ILCR);
224
225 if (i2c->mode == SPACEMIT_MODE_STANDARD) {
226 lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr);
227 return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8);
228 }
229
230 lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr);
231 return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10);
232 }
233
234 static const struct clk_ops spacemit_i2c_clk_ops = {
235 .set_rate = spacemit_i2c_clk_set_rate,
236 .determine_rate = spacemit_i2c_clk_determine_rate,
237 .recalc_rate = spacemit_i2c_clk_recalc_rate,
238 };
239
spacemit_i2c_enable(struct spacemit_i2c_dev * i2c)240 static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c)
241 {
242 u32 val;
243
244 val = readl(i2c->base + SPACEMIT_ICR);
245 val |= SPACEMIT_CR_IUE;
246 writel(val, i2c->base + SPACEMIT_ICR);
247 }
248
spacemit_i2c_disable(struct spacemit_i2c_dev * i2c)249 static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c)
250 {
251 u32 val;
252
253 val = readl(i2c->base + SPACEMIT_ICR);
254 val &= ~SPACEMIT_CR_IUE;
255 writel(val, i2c->base + SPACEMIT_ICR);
256 }
257
spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev * i2c)258 static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c)
259 {
260 struct clk_init_data init = {};
261 char name[64];
262 int ret;
263
264 ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev));
265 if (ret >= ARRAY_SIZE(name))
266 dev_warn(i2c->dev, "scl clock name truncated");
267
268 init.name = name;
269 init.ops = &spacemit_i2c_clk_ops;
270 init.parent_data = (struct clk_parent_data[]) {
271 { .fw_name = "func" },
272 };
273 init.num_parents = 1;
274
275 i2c->scl_clk_hw.init = &init;
276
277 return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw);
278 }
279
spacemit_i2c_reset(struct spacemit_i2c_dev * i2c)280 static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c)
281 {
282 writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR);
283 udelay(5);
284 writel(0, i2c->base + SPACEMIT_ICR);
285 }
286
spacemit_i2c_handle_err(struct spacemit_i2c_dev * i2c)287 static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c)
288 {
289 dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status);
290
291 /* Arbitration Loss Detected */
292 if (i2c->status & SPACEMIT_SR_ALD) {
293 spacemit_i2c_reset(i2c);
294 return -EAGAIN;
295 }
296
297 /* Bus Error No ACK/NAK */
298 if (i2c->status & SPACEMIT_SR_BED)
299 spacemit_i2c_reset(i2c);
300
301 return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO;
302 }
303
spacemit_i2c_delay(struct spacemit_i2c_dev * i2c,unsigned int us)304 static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us)
305 {
306 if (i2c->use_pio)
307 udelay(us);
308 else
309 fsleep(us);
310 }
311
spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev * i2c)312 static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c)
313 {
314 u32 status;
315 u8 clk_cnt;
316
317 /* if bus is locked, reset unit. 0: locked */
318 status = readl(i2c->base + SPACEMIT_IBMR);
319 if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL))
320 return;
321
322 spacemit_i2c_reset(i2c);
323
324 spacemit_i2c_delay(i2c, 10);
325
326 for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) {
327 status = readl(i2c->base + SPACEMIT_IBMR);
328 if (status & SPACEMIT_BMR_SDA)
329 return;
330
331 /* There's nothing left to save here, we are about to exit */
332 writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1),
333 i2c->base + SPACEMIT_IRCR);
334 writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR);
335 usleep_range(20, 30);
336 }
337
338 /* check sda again here */
339 status = readl(i2c->base + SPACEMIT_IBMR);
340 if (!(status & SPACEMIT_BMR_SDA))
341 dev_warn_ratelimited(i2c->dev, "unit reset failed\n");
342 }
343
spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev * i2c)344 static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c)
345 {
346 int ret;
347 u32 val;
348
349 val = readl(i2c->base + SPACEMIT_ISR);
350 if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)))
351 return 0;
352
353 if (i2c->use_pio)
354 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR,
355 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)),
356 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT);
357 else
358 ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR,
359 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)),
360 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT);
361
362 if (ret)
363 spacemit_i2c_reset(i2c);
364
365 return ret;
366 }
367
spacemit_i2c_check_bus_release(struct spacemit_i2c_dev * i2c)368 static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c)
369 {
370 /* in case bus is not released after transfer completes */
371 if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) {
372 spacemit_i2c_conditionally_reset_bus(i2c);
373 spacemit_i2c_delay(i2c, 90);
374 }
375 }
376
377 static inline void
spacemit_i2c_clear_int_status(struct spacemit_i2c_dev * i2c,u32 mask)378 spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask)
379 {
380 writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR);
381 }
382
spacemit_i2c_init(struct spacemit_i2c_dev * i2c)383 static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
384 {
385 u32 val = 0;
386
387 if (!i2c->use_pio) {
388 /*
389 * Enable interrupt bits for all xfer mode:
390 * bus error, arbitration loss detected.
391 */
392 val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE;
393
394 /*
395 * Unmask interrupt bits for interrupt xfer mode:
396 * When IDBR receives a byte, an interrupt is triggered.
397 *
398 * For the tx empty interrupt, it will be enabled in the
399 * i2c_start().
400 * We don't want a TX empty interrupt until we start
401 * a transfer in i2c_start().
402 */
403 val |= SPACEMIT_CR_DRFIE;
404
405 /*
406 * Enable master stop interrupt bit.
407 * For transaction complete signal, we use master stop
408 * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE.
409 */
410 val |= SPACEMIT_CR_MSDIE;
411 }
412
413 if (i2c->mode == SPACEMIT_MODE_FAST)
414 val |= SPACEMIT_CR_MODE_FAST;
415
416 /* disable response to general call */
417 val |= SPACEMIT_CR_GCD;
418
419 /* enable SCL clock output */
420 val |= SPACEMIT_CR_SCLE;
421
422 /* enable master stop detected */
423 val |= SPACEMIT_CR_MSDE;
424
425 writel(val, i2c->base + SPACEMIT_ICR);
426
427 /*
428 * The glitch fix in the K1 I2C controller introduces a delay
429 * on restart signals, so we disable the fix here.
430 */
431 val = readl(i2c->base + SPACEMIT_IRCR);
432 val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX;
433 writel(val, i2c->base + SPACEMIT_IRCR);
434
435 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
436
437 /*
438 * Initialize IWCR to the value specified by the I2C IP designer.
439 * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard
440 * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when
441 * IWCR contains this specific value.
442 */
443 writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR);
444 }
445
spacemit_i2c_start(struct spacemit_i2c_dev * i2c)446 static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c)
447 {
448 u32 target_addr_rw, val;
449 struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx;
450
451 i2c->read = !!(cur_msg->flags & I2C_M_RD);
452
453 i2c->state = SPACEMIT_STATE_START;
454
455 target_addr_rw = (cur_msg->addr & 0x7f) << 1;
456 if (cur_msg->flags & I2C_M_RD)
457 target_addr_rw |= 1;
458
459 writel(target_addr_rw, i2c->base + SPACEMIT_IDBR);
460
461 /* send start pulse */
462 val = readl(i2c->base + SPACEMIT_ICR);
463 val &= ~SPACEMIT_CR_STOP;
464 val |= SPACEMIT_CR_START | SPACEMIT_CR_TB;
465
466 /* Enable the TX empty interrupt */
467 if (!i2c->use_pio)
468 val |= SPACEMIT_CR_DTEIE;
469
470 writel(val, i2c->base + SPACEMIT_ICR);
471 }
472
spacemit_i2c_is_last_msg(struct spacemit_i2c_dev * i2c)473 static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c)
474 {
475 if (i2c->msg_idx != i2c->msg_num - 1)
476 return false;
477
478 if (i2c->read)
479 return i2c->unprocessed == 1;
480
481 return !i2c->unprocessed;
482 }
483
spacemit_i2c_complete(struct spacemit_i2c_dev * i2c)484 static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c)
485 {
486 /* SPACEMIT_STATE_IDLE avoids triggering the next byte */
487 i2c->state = SPACEMIT_STATE_IDLE;
488
489 if (i2c->use_pio)
490 return;
491
492 complete(&i2c->complete);
493 }
494
spacemit_i2c_handle_write(struct spacemit_i2c_dev * i2c)495 static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c)
496 {
497 /* If there's no space in the IDBR, we're done */
498 if (!(i2c->status & SPACEMIT_SR_ITE))
499 return;
500
501 /* if transfer completes, SPACEMIT_ISR will handle it */
502 if (i2c->status & SPACEMIT_SR_MSD)
503 return;
504
505 if (i2c->unprocessed) {
506 writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR);
507 i2c->unprocessed--;
508 return;
509 }
510
511 spacemit_i2c_complete(i2c);
512 }
513
spacemit_i2c_handle_read(struct spacemit_i2c_dev * i2c)514 static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c)
515 {
516 /* If there's nothing in the IDBR, we're done */
517 if (!(i2c->status & SPACEMIT_SR_IRF))
518 return;
519
520 if (i2c->unprocessed) {
521 *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR);
522 i2c->unprocessed--;
523 return;
524 }
525
526 /* if transfer completes, SPACEMIT_ISR will handle it */
527 if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK))
528 return;
529
530 /* it has to append stop bit in icr that read last byte */
531 if (i2c->unprocessed)
532 return;
533
534 spacemit_i2c_complete(i2c);
535 }
536
spacemit_i2c_handle_start(struct spacemit_i2c_dev * i2c)537 static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c)
538 {
539 i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE;
540 if (i2c->state == SPACEMIT_STATE_WRITE)
541 spacemit_i2c_handle_write(i2c);
542 }
543
spacemit_i2c_err_check(struct spacemit_i2c_dev * i2c)544 static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c)
545 {
546 u32 val;
547
548 /*
549 * Send transaction complete signal:
550 * error happens, detect master stop
551 */
552 if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD)))
553 return;
554
555 /*
556 * Here the transaction is already done, we don't need any
557 * other interrupt signals from now, in case any interrupt
558 * happens before spacemit_i2c_xfer to disable irq and i2c unit,
559 * we mask all the interrupt signals and clear the interrupt
560 * status.
561 */
562 val = readl(i2c->base + SPACEMIT_ICR);
563 val &= ~SPACEMIT_I2C_INT_CTRL_MASK;
564 writel(val, i2c->base + SPACEMIT_ICR);
565
566 spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
567
568 spacemit_i2c_complete(i2c);
569 }
570
spacemit_i2c_handle_state(struct spacemit_i2c_dev * i2c)571 static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c)
572 {
573 u32 val;
574
575 if (i2c->status & SPACEMIT_SR_ERR)
576 goto err_out;
577
578 switch (i2c->state) {
579 case SPACEMIT_STATE_START:
580 spacemit_i2c_handle_start(i2c);
581 break;
582 case SPACEMIT_STATE_READ:
583 spacemit_i2c_handle_read(i2c);
584 break;
585 case SPACEMIT_STATE_WRITE:
586 spacemit_i2c_handle_write(i2c);
587 break;
588 default:
589 break;
590 }
591
592 if (i2c->state != SPACEMIT_STATE_IDLE) {
593 val = readl(i2c->base + SPACEMIT_ICR);
594 val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK |
595 SPACEMIT_CR_STOP | SPACEMIT_CR_START);
596 val |= SPACEMIT_CR_TB;
597 if (!i2c->use_pio)
598 val |= SPACEMIT_CR_ALDIE;
599
600 if (spacemit_i2c_is_last_msg(i2c)) {
601 /* trigger next byte with stop */
602 val |= SPACEMIT_CR_STOP;
603
604 if (i2c->read)
605 val |= SPACEMIT_CR_ACKNAK;
606 }
607 writel(val, i2c->base + SPACEMIT_ICR);
608 }
609
610 err_out:
611 spacemit_i2c_err_check(i2c);
612 }
613
614 /*
615 * In PIO mode, this function is used as a replacement for
616 * wait_for_completion_timeout(), whose return value indicates
617 * the remaining time.
618 *
619 * We do not have a meaningful remaining-time value here, so
620 * return a non-zero value on success to indicate "not timed out".
621 * Returning 1 ensures callers treating the return value as
622 * time_left will not incorrectly report a timeout.
623 */
spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev * i2c)624 static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c)
625 {
626 u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout);
627 ktime_t timeout = ktime_add_ms(ktime_get(), msec);
628 int ret;
629
630 mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE;
631
632 do {
633 i2c->status = readl(i2c->base + SPACEMIT_ISR);
634
635 spacemit_i2c_clear_int_status(i2c, i2c->status);
636
637 if (i2c->status & mask)
638 spacemit_i2c_handle_state(i2c);
639 else
640 udelay(SPACEMIT_POLL_INTERVAL);
641 } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0);
642
643 if (i2c->unprocessed)
644 return 0;
645
646 if (i2c->read)
647 return 1;
648
649 /*
650 * If this is the last byte to write of the current message,
651 * we have to wait here. Otherwise, control will proceed directly
652 * to start(), which would overwrite the current data.
653 */
654 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR,
655 i2c->status, i2c->status & SPACEMIT_SR_ITE,
656 SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT);
657 if (ret)
658 return 0;
659
660 /*
661 * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered
662 * after the last byte, and the MSD-related handling takes place there.
663 * In PIO mode, however, we need to explicitly call err_check() to emulate this
664 * step, otherwise the next transfer will fail.
665 */
666 if (i2c->msg_idx == i2c->msg_num - 1) {
667 mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR;
668 /*
669 * In some cases, MSD may not arrive immediately;
670 * wait here to handle that.
671 */
672 ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR,
673 i2c->status, i2c->status & mask,
674 SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT);
675 if (ret)
676 return 0;
677
678 spacemit_i2c_err_check(i2c);
679 }
680
681 return 1;
682 }
683
spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev * i2c)684 static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c)
685 {
686 if (i2c->use_pio)
687 return spacemit_i2c_wait_pio_xfer(i2c);
688
689 return wait_for_completion_timeout(&i2c->complete,
690 i2c->adapt.timeout);
691 }
692
spacemit_i2c_xfer_msg(struct spacemit_i2c_dev * i2c)693 static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c)
694 {
695 unsigned long time_left;
696 struct i2c_msg *msg;
697
698 for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) {
699 msg = &i2c->msgs[i2c->msg_idx];
700 i2c->msg_buf = msg->buf;
701 i2c->unprocessed = msg->len;
702 i2c->status = 0;
703
704 reinit_completion(&i2c->complete);
705
706 spacemit_i2c_start(i2c);
707
708 time_left = spacemit_i2c_wait_xfer_complete(i2c);
709
710 if (!time_left) {
711 dev_err(i2c->dev, "msg completion timeout\n");
712 spacemit_i2c_conditionally_reset_bus(i2c);
713 spacemit_i2c_reset(i2c);
714 return -ETIMEDOUT;
715 }
716
717 if (i2c->status & SPACEMIT_SR_ERR)
718 return spacemit_i2c_handle_err(i2c);
719 }
720
721 return 0;
722 }
723
spacemit_i2c_irq_handler(int irq,void * devid)724 static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid)
725 {
726 struct spacemit_i2c_dev *i2c = devid;
727 u32 status;
728
729 status = readl(i2c->base + SPACEMIT_ISR);
730 if (!status)
731 return IRQ_NONE;
732
733 i2c->status = status;
734
735 spacemit_i2c_clear_int_status(i2c, status);
736
737 spacemit_i2c_handle_state(i2c);
738
739 return IRQ_HANDLED;
740 }
741
spacemit_i2c_calc_timeout(struct spacemit_i2c_dev * i2c)742 static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c)
743 {
744 unsigned long timeout;
745 int idx = 0, cnt = 0;
746
747 if (i2c->use_pio) {
748 i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT);
749 return;
750 }
751
752 for (; idx < i2c->msg_num; idx++)
753 cnt += (i2c->msgs + idx)->len + 1;
754
755 /*
756 * Multiply by 9 because each byte in I2C transmission requires
757 * 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit.
758 */
759 timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq;
760
761 i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num;
762 }
763
764 static inline int
spacemit_i2c_xfer_common(struct i2c_adapter * adapt,struct i2c_msg * msgs,int num,bool use_pio)765 spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio)
766 {
767 struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt);
768 int ret;
769
770 i2c->use_pio = use_pio;
771
772 i2c->msgs = msgs;
773 i2c->msg_num = num;
774
775 spacemit_i2c_calc_timeout(i2c);
776
777 spacemit_i2c_init(i2c);
778
779 spacemit_i2c_enable(i2c);
780
781 ret = spacemit_i2c_wait_bus_idle(i2c);
782 if (!ret) {
783 ret = spacemit_i2c_xfer_msg(i2c);
784 if (ret < 0)
785 dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret);
786 } else {
787 spacemit_i2c_check_bus_release(i2c);
788 }
789
790 spacemit_i2c_disable(i2c);
791
792 if (ret == -ETIMEDOUT || ret == -EAGAIN)
793 dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n",
794 ret, i2c->status & SPACEMIT_SR_ERR);
795
796 return ret < 0 ? ret : num;
797 }
798
spacemit_i2c_xfer(struct i2c_adapter * adapt,struct i2c_msg * msgs,int num)799 static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num)
800 {
801 return spacemit_i2c_xfer_common(adapt, msgs, num, false);
802 }
803
spacemit_i2c_pio_xfer_atomic(struct i2c_adapter * adapt,struct i2c_msg * msgs,int num)804 static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num)
805 {
806 return spacemit_i2c_xfer_common(adapt, msgs, num, true);
807 }
808
spacemit_i2c_func(struct i2c_adapter * adap)809 static u32 spacemit_i2c_func(struct i2c_adapter *adap)
810 {
811 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
812 }
813
814 static const struct i2c_algorithm spacemit_i2c_algo = {
815 .xfer = spacemit_i2c_xfer,
816 .xfer_atomic = spacemit_i2c_pio_xfer_atomic,
817 .functionality = spacemit_i2c_func,
818 };
819
spacemit_i2c_probe(struct platform_device * pdev)820 static int spacemit_i2c_probe(struct platform_device *pdev)
821 {
822 struct clk *clk;
823 struct device *dev = &pdev->dev;
824 struct device_node *of_node = pdev->dev.of_node;
825 struct spacemit_i2c_dev *i2c;
826 struct reset_control *rst;
827 int ret;
828
829 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
830 if (!i2c)
831 return -ENOMEM;
832
833 of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq);
834
835 /* For now, this driver doesn't support high-speed. */
836 if (i2c->clock_freq > I2C_MAX_STANDARD_MODE_FREQ &&
837 i2c->clock_freq <= I2C_MAX_FAST_MODE_FREQ) {
838 i2c->mode = SPACEMIT_MODE_FAST;
839 } else if (i2c->clock_freq && i2c->clock_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
840 i2c->mode = SPACEMIT_MODE_STANDARD;
841 } else {
842 dev_info(dev, "clock-frequency not set or out of range, using fast mode\n");
843 i2c->mode = SPACEMIT_MODE_FAST;
844 i2c->clock_freq = I2C_MAX_FAST_MODE_FREQ;
845 }
846
847 i2c->dev = &pdev->dev;
848
849 i2c->base = devm_platform_ioremap_resource(pdev, 0);
850 if (IS_ERR(i2c->base))
851 return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap");
852
853 i2c->irq = platform_get_irq(pdev, 0);
854 if (i2c->irq < 0)
855 return i2c->irq;
856
857 clk = devm_clk_get_enabled(dev, "func");
858 if (IS_ERR(clk))
859 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock");
860
861 ret = spacemit_i2c_register_scl_clk(i2c);
862 if (ret)
863 return dev_err_probe(dev, ret, "failed to register scl clock\n");
864
865 i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl");
866 if (IS_ERR(i2c->scl_clk))
867 return dev_err_probe(dev, PTR_ERR(i2c->scl_clk),
868 "failed to get scl clock\n");
869
870 clk = devm_clk_get_enabled(dev, "bus");
871 if (IS_ERR(clk))
872 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock");
873
874 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
875 if (IS_ERR(rst))
876 return dev_err_probe(dev, PTR_ERR(rst),
877 "failed to acquire deasserted reset\n");
878
879 ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq);
880 if (ret)
881 return dev_err_probe(dev, ret, "failed to set rate for SCL clock");
882
883 ret = clk_prepare_enable(i2c->scl_clk);
884 if (ret)
885 return dev_err_probe(dev, ret, "failed to prepare and enable clock");
886
887 ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare,
888 i2c->scl_clk);
889 if (ret)
890 return ret;
891
892 spacemit_i2c_reset(i2c);
893
894 i2c_set_adapdata(&i2c->adapt, i2c);
895 i2c->adapt.owner = THIS_MODULE;
896 i2c->adapt.algo = &spacemit_i2c_algo;
897 i2c->adapt.dev.parent = i2c->dev;
898 i2c->adapt.nr = pdev->id;
899
900 i2c->adapt.dev.of_node = of_node;
901
902 strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name));
903
904 init_completion(&i2c->complete);
905
906 ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler,
907 IRQF_NO_SUSPEND, dev_name(i2c->dev), i2c);
908 if (ret)
909 return ret;
910
911 platform_set_drvdata(pdev, i2c);
912
913 ret = i2c_add_numbered_adapter(&i2c->adapt);
914 if (ret)
915 return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter");
916
917 return 0;
918 }
919
spacemit_i2c_remove(struct platform_device * pdev)920 static void spacemit_i2c_remove(struct platform_device *pdev)
921 {
922 struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev);
923
924 i2c_del_adapter(&i2c->adapt);
925 }
926
927 static const struct of_device_id spacemit_i2c_of_match[] = {
928 { .compatible = "spacemit,k1-i2c", },
929 { /* sentinel */ }
930 };
931 MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match);
932
933 static struct platform_driver spacemit_i2c_driver = {
934 .probe = spacemit_i2c_probe,
935 .remove = spacemit_i2c_remove,
936 .driver = {
937 .name = "i2c-k1",
938 .of_match_table = spacemit_i2c_of_match,
939 },
940 };
941 module_platform_driver(spacemit_i2c_driver);
942
943 MODULE_LICENSE("GPL");
944 MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC");
945