1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD4080 SPI ADC driver
4 *
5 * Copyright 2025 Analog Devices Inc.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/iio/backend.h>
15 #include <linux/iio/iio.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/types.h>
23 #include <linux/unaligned.h>
24 #include <linux/units.h>
25
26 /* Register Definition */
27 #define AD4080_REG_INTERFACE_CONFIG_A 0x00
28 #define AD4080_REG_INTERFACE_CONFIG_B 0x01
29 #define AD4080_REG_DEVICE_CONFIG 0x02
30 #define AD4080_REG_CHIP_TYPE 0x03
31 #define AD4080_REG_PRODUCT_ID_L 0x04
32 #define AD4080_REG_PRODUCT_ID_H 0x05
33 #define AD4080_REG_CHIP_GRADE 0x06
34 #define AD4080_REG_SCRATCH_PAD 0x0A
35 #define AD4080_REG_SPI_REVISION 0x0B
36 #define AD4080_REG_VENDOR_L 0x0C
37 #define AD4080_REG_VENDOR_H 0x0D
38 #define AD4080_REG_STREAM_MODE 0x0E
39 #define AD4080_REG_TRANSFER_CONFIG 0x0F
40 #define AD4080_REG_INTERFACE_CONFIG_C 0x10
41 #define AD4080_REG_INTERFACE_STATUS_A 0x11
42 #define AD4080_REG_DEVICE_STATUS 0x14
43 #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15
44 #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16
45 #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17
46 #define AD4080_REG_PWR_CTRL 0x18
47 #define AD4080_REG_GPIO_CONFIG_A 0x19
48 #define AD4080_REG_GPIO_CONFIG_B 0x1A
49 #define AD4080_REG_GPIO_CONFIG_C 0x1B
50 #define AD4080_REG_GENERAL_CONFIG 0x1C
51 #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D
52 #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E
53 #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F
54 #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20
55 #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21
56 #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22
57 #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23
58 #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24
59 #define AD4080_REG_OFFSET_LSB 0x25
60 #define AD4080_REG_OFFSET_MSB 0x26
61 #define AD4080_REG_GAIN_LSB 0x27
62 #define AD4080_REG_GAIN_MSB 0x28
63 #define AD4080_REG_FILTER_CONFIG 0x29
64
65 /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */
66 #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0))
67 #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5)
68 #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4)
69
70 /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */
71 #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7)
72 #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3)
73
74 /* AD4080_REG_DEVICE_CONFIG Bit Definition */
75 #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0)
76
77 /* AD4080_REG_TRANSFER_CONFIG Bit Definition */
78 #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2)
79
80 /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */
81 #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5)
82
83 /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */
84 #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6)
85 #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4)
86 #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2)
87 #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0)
88
89 /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */
90 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4)
91 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3)
92 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0)
93
94 /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */
95 #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4)
96
97 /* AD4080_REG_PWR_CTRL Bit Definition */
98 #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1)
99 #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0)
100
101 /* AD4080_REG_GPIO_CONFIG_A Bit Definition */
102 #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1)
103 #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0)
104
105 /* AD4080_REG_GPIO_CONFIG_B Bit Definition */
106 #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4)
107 #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0)
108 #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0
109 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1
110 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2
111 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3
112 #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4
113 #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5
114 #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6
115 #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7
116 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8
117 #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9
118
119 /* AD4080_REG_FIFO_CONFIG Bit Definition */
120 #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0)
121
122 /* AD4080_REG_FILTER_CONFIG Bit Definition */
123 #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3)
124 #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0)
125
126 /* Miscellaneous Definitions */
127 #define AD4080_SPI_READ BIT(7)
128 #define AD4080_CHIP_ID 0x0050
129 #define AD4081_CHIP_ID 0x0051
130 #define AD4082_CHIP_ID 0x0052
131 #define AD4083_CHIP_ID 0x0053
132 #define AD4084_CHIP_ID 0x0054
133 #define AD4085_CHIP_ID 0x0055
134 #define AD4086_CHIP_ID 0x0056
135 #define AD4087_CHIP_ID 0x0057
136 #define AD4088_CHIP_ID 0x0058
137
138 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7
139
140 #define AD4080_MAX_SAMP_FREQ 40000000
141 #define AD4080_MIN_SAMP_FREQ 1250000
142
143 enum ad4080_filter_type {
144 FILTER_NONE,
145 SINC_1,
146 SINC_5,
147 SINC_5_COMP
148 };
149
150 static const unsigned int ad4080_scale_table[][2] = {
151 { 6000, 0 },
152 };
153
154 static const char *const ad4080_filter_type_iio_enum[] = {
155 [FILTER_NONE] = "none",
156 [SINC_1] = "sinc1",
157 [SINC_5] = "sinc5",
158 [SINC_5_COMP] = "sinc5+pf1",
159 };
160
161 static const int ad4080_dec_rate_avail[] = {
162 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
163 };
164
165 static const int ad4080_dec_rate_none[] = { 1 };
166
167 static const char * const ad4080_power_supplies[] = {
168 "vdd33", "vdd11", "vddldo", "iovdd", "vrefin",
169 };
170
171 struct ad4080_chip_info {
172 const char *name;
173 unsigned int product_id;
174 int num_scales;
175 const unsigned int (*scale_table)[2];
176 const struct iio_chan_spec *channels;
177 unsigned int num_channels;
178 unsigned int lvds_cnv_clk_cnt_max;
179 };
180
181 struct ad4080_state {
182 struct regmap *regmap;
183 struct iio_backend *back;
184 const struct ad4080_chip_info *info;
185 /*
186 * Synchronize access to members the of driver state, and ensure
187 * atomicity of consecutive regmap operations.
188 */
189 struct mutex lock;
190 unsigned int num_lanes;
191 unsigned long clk_rate;
192 enum ad4080_filter_type filter_type;
193 bool lvds_cnv_en;
194 };
195
196 static const struct regmap_config ad4080_regmap_config = {
197 .reg_bits = 16,
198 .val_bits = 8,
199 .read_flag_mask = BIT(7),
200 .max_register = 0x29,
201 };
202
ad4080_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)203 static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg,
204 unsigned int writeval, unsigned int *readval)
205 {
206 struct ad4080_state *st = iio_priv(indio_dev);
207
208 if (readval)
209 return regmap_read(st->regmap, reg, readval);
210
211 return regmap_write(st->regmap, reg, writeval);
212 }
213
ad4080_get_scale(struct ad4080_state * st,int * val,int * val2)214 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2)
215 {
216 unsigned int tmp;
217
218 tmp = (st->info->scale_table[0][0] * 1000000ULL) >>
219 st->info->channels[0].scan_type.realbits;
220 *val = tmp / 1000000;
221 *val2 = tmp % 1000000;
222
223 return IIO_VAL_INT_PLUS_NANO;
224 }
225
ad4080_get_dec_rate(struct iio_dev * dev,const struct iio_chan_spec * chan)226 static unsigned int ad4080_get_dec_rate(struct iio_dev *dev,
227 const struct iio_chan_spec *chan)
228 {
229 struct ad4080_state *st = iio_priv(dev);
230 int ret;
231 unsigned int data;
232
233 ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data);
234 if (ret)
235 return ret;
236
237 return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1);
238 }
239
ad4080_set_dec_rate(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int mode)240 static int ad4080_set_dec_rate(struct iio_dev *dev,
241 const struct iio_chan_spec *chan,
242 unsigned int mode)
243 {
244 struct ad4080_state *st = iio_priv(dev);
245
246 guard(mutex)(&st->lock);
247
248 if ((st->filter_type >= SINC_5 && mode >= 512) || mode < 2)
249 return -EINVAL;
250
251 return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG,
252 AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
253 FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
254 (ilog2(mode) - 1)));
255 }
256
ad4080_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)257 static int ad4080_read_raw(struct iio_dev *indio_dev,
258 struct iio_chan_spec const *chan,
259 int *val, int *val2, long m)
260 {
261 struct ad4080_state *st = iio_priv(indio_dev);
262 int dec_rate;
263
264 switch (m) {
265 case IIO_CHAN_INFO_SCALE:
266 return ad4080_get_scale(st, val, val2);
267 case IIO_CHAN_INFO_SAMP_FREQ:
268 dec_rate = ad4080_get_dec_rate(indio_dev, chan);
269 if (dec_rate < 0)
270 return dec_rate;
271 if (st->filter_type == SINC_5_COMP)
272 dec_rate *= 2;
273 if (st->filter_type)
274 *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate);
275 else
276 *val = st->clk_rate;
277 return IIO_VAL_INT;
278 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
279 if (st->filter_type == FILTER_NONE) {
280 *val = 1;
281 } else {
282 *val = ad4080_get_dec_rate(indio_dev, chan);
283 if (*val < 0)
284 return *val;
285 }
286 return IIO_VAL_INT;
287 default:
288 return -EINVAL;
289 }
290 }
291
ad4080_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)292 static int ad4080_write_raw(struct iio_dev *indio_dev,
293 struct iio_chan_spec const *chan,
294 int val, int val2, long mask)
295 {
296 struct ad4080_state *st = iio_priv(indio_dev);
297
298 switch (mask) {
299 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
300 if (st->filter_type == FILTER_NONE && val > 1)
301 return -EINVAL;
302
303 return ad4080_set_dec_rate(indio_dev, chan, val);
304 default:
305 return -EINVAL;
306 }
307 }
308
ad4080_lvds_sync_write(struct ad4080_state * st)309 static int ad4080_lvds_sync_write(struct ad4080_state *st)
310 {
311 struct device *dev = regmap_get_device(st->regmap);
312 int ret;
313
314 ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
315 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
316 if (ret)
317 return ret;
318
319 ret = iio_backend_interface_data_align(st->back, 10000);
320 if (ret)
321 return dev_err_probe(dev, ret,
322 "Data alignment process failed\n");
323
324 dev_dbg(dev, "Success: Pattern correct and Locked!\n");
325 return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
326 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
327 }
328
ad4080_get_filter_type(struct iio_dev * dev,const struct iio_chan_spec * chan)329 static int ad4080_get_filter_type(struct iio_dev *dev,
330 const struct iio_chan_spec *chan)
331 {
332 struct ad4080_state *st = iio_priv(dev);
333 unsigned int data;
334 int ret;
335
336 ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data);
337 if (ret)
338 return ret;
339
340 return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data);
341 }
342
ad4080_set_filter_type(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int mode)343 static int ad4080_set_filter_type(struct iio_dev *dev,
344 const struct iio_chan_spec *chan,
345 unsigned int mode)
346 {
347 struct ad4080_state *st = iio_priv(dev);
348 int dec_rate;
349 int ret;
350
351 guard(mutex)(&st->lock);
352
353 dec_rate = ad4080_get_dec_rate(dev, chan);
354 if (dec_rate < 0)
355 return dec_rate;
356
357 if (mode >= SINC_5 && dec_rate >= 512)
358 return -EINVAL;
359
360 ret = iio_backend_filter_type_set(st->back, mode);
361 if (ret)
362 return ret;
363
364 ret = regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG,
365 AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
366 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
367 mode));
368 if (ret)
369 return ret;
370
371 st->filter_type = mode;
372
373 return 0;
374 }
375
ad4080_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)376 static int ad4080_read_avail(struct iio_dev *indio_dev,
377 struct iio_chan_spec const *chan,
378 const int **vals, int *type, int *length,
379 long mask)
380 {
381 struct ad4080_state *st = iio_priv(indio_dev);
382
383 switch (mask) {
384 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
385 switch (st->filter_type) {
386 case FILTER_NONE:
387 *vals = ad4080_dec_rate_none;
388 *length = ARRAY_SIZE(ad4080_dec_rate_none);
389 break;
390 default:
391 *vals = ad4080_dec_rate_avail;
392 *length = st->filter_type >= SINC_5 ?
393 (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) :
394 ARRAY_SIZE(ad4080_dec_rate_avail);
395 break;
396 }
397 *type = IIO_VAL_INT;
398 return IIO_AVAIL_LIST;
399 default:
400 return -EINVAL;
401 }
402 }
403
404 static const struct iio_info ad4080_iio_info = {
405 .debugfs_reg_access = ad4080_reg_access,
406 .read_raw = ad4080_read_raw,
407 .write_raw = ad4080_write_raw,
408 .read_avail = ad4080_read_avail,
409 };
410
411 static const struct iio_enum ad4080_filter_type_enum = {
412 .items = ad4080_filter_type_iio_enum,
413 .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum),
414 .set = ad4080_set_filter_type,
415 .get = ad4080_get_filter_type,
416 };
417
418 static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
419 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum),
420 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL,
421 &ad4080_filter_type_enum),
422 { }
423 };
424
425 #define AD4080_CHANNEL_DEFINE(bits, storage) { \
426 .type = IIO_VOLTAGE, \
427 .indexed = 1, \
428 .channel = 0, \
429 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \
430 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
431 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
432 .info_mask_shared_by_all_available = \
433 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
434 .ext_info = ad4080_ext_info, \
435 .scan_index = 0, \
436 .scan_type = { \
437 .sign = 's', \
438 .realbits = (bits), \
439 .storagebits = (storage), \
440 }, \
441 }
442
443 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32);
444
445 static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32);
446
447 static const struct iio_chan_spec ad4082_channel = AD4080_CHANNEL_DEFINE(20, 32);
448
449 static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16);
450
451 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16);
452
453 static const struct iio_chan_spec ad4085_channel = AD4080_CHANNEL_DEFINE(16, 16);
454
455 static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16);
456
457 static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16);
458
459 static const struct iio_chan_spec ad4088_channel = AD4080_CHANNEL_DEFINE(14, 16);
460
461 static const struct ad4080_chip_info ad4080_chip_info = {
462 .name = "ad4080",
463 .product_id = AD4080_CHIP_ID,
464 .scale_table = ad4080_scale_table,
465 .num_scales = ARRAY_SIZE(ad4080_scale_table),
466 .num_channels = 1,
467 .channels = &ad4080_channel,
468 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
469 };
470
471 static const struct ad4080_chip_info ad4081_chip_info = {
472 .name = "ad4081",
473 .product_id = AD4081_CHIP_ID,
474 .scale_table = ad4080_scale_table,
475 .num_scales = ARRAY_SIZE(ad4080_scale_table),
476 .num_channels = 1,
477 .channels = &ad4081_channel,
478 .lvds_cnv_clk_cnt_max = 2,
479 };
480
481 static const struct ad4080_chip_info ad4082_chip_info = {
482 .name = "ad4082",
483 .product_id = AD4082_CHIP_ID,
484 .scale_table = ad4080_scale_table,
485 .num_scales = ARRAY_SIZE(ad4080_scale_table),
486 .num_channels = 1,
487 .channels = &ad4082_channel,
488 .lvds_cnv_clk_cnt_max = 8,
489 };
490
491 static const struct ad4080_chip_info ad4083_chip_info = {
492 .name = "ad4083",
493 .product_id = AD4083_CHIP_ID,
494 .scale_table = ad4080_scale_table,
495 .num_scales = ARRAY_SIZE(ad4080_scale_table),
496 .num_channels = 1,
497 .channels = &ad4083_channel,
498 .lvds_cnv_clk_cnt_max = 5,
499 };
500
501 static const struct ad4080_chip_info ad4084_chip_info = {
502 .name = "ad4084",
503 .product_id = AD4084_CHIP_ID,
504 .scale_table = ad4080_scale_table,
505 .num_scales = ARRAY_SIZE(ad4080_scale_table),
506 .num_channels = 1,
507 .channels = &ad4084_channel,
508 .lvds_cnv_clk_cnt_max = 2,
509 };
510
511 static const struct ad4080_chip_info ad4085_chip_info = {
512 .name = "ad4085",
513 .product_id = AD4085_CHIP_ID,
514 .scale_table = ad4080_scale_table,
515 .num_scales = ARRAY_SIZE(ad4080_scale_table),
516 .num_channels = 1,
517 .channels = &ad4085_channel,
518 .lvds_cnv_clk_cnt_max = 8,
519 };
520
521 static const struct ad4080_chip_info ad4086_chip_info = {
522 .name = "ad4086",
523 .product_id = AD4086_CHIP_ID,
524 .scale_table = ad4080_scale_table,
525 .num_scales = ARRAY_SIZE(ad4080_scale_table),
526 .num_channels = 1,
527 .channels = &ad4086_channel,
528 .lvds_cnv_clk_cnt_max = 4,
529 };
530
531 static const struct ad4080_chip_info ad4087_chip_info = {
532 .name = "ad4087",
533 .product_id = AD4087_CHIP_ID,
534 .scale_table = ad4080_scale_table,
535 .num_scales = ARRAY_SIZE(ad4080_scale_table),
536 .num_channels = 1,
537 .channels = &ad4087_channel,
538 .lvds_cnv_clk_cnt_max = 1,
539 };
540
541 static const struct ad4080_chip_info ad4088_chip_info = {
542 .name = "ad4088",
543 .product_id = AD4088_CHIP_ID,
544 .scale_table = ad4080_scale_table,
545 .num_scales = ARRAY_SIZE(ad4080_scale_table),
546 .num_channels = 1,
547 .channels = &ad4088_channel,
548 .lvds_cnv_clk_cnt_max = 8,
549 };
550
ad4080_setup(struct iio_dev * indio_dev)551 static int ad4080_setup(struct iio_dev *indio_dev)
552 {
553 struct ad4080_state *st = iio_priv(indio_dev);
554 struct device *dev = regmap_get_device(st->regmap);
555 __le16 id_le;
556 u16 id;
557 int ret;
558
559 ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A,
560 AD4080_INTERFACE_CONFIG_A_SW_RESET);
561 if (ret)
562 return ret;
563
564 ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A,
565 AD4080_INTERFACE_CONFIG_A_SDO_ENABLE);
566 if (ret)
567 return ret;
568
569 ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id_le,
570 sizeof(id_le));
571 if (ret)
572 return ret;
573
574 id = le16_to_cpu(id_le);
575 if (id != st->info->product_id)
576 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
577
578 ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A,
579 AD4080_GPIO_CONFIG_A_GPO_1_EN);
580 if (ret)
581 return ret;
582
583 ret = regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B,
584 FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK,
585 AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY));
586 if (ret)
587 return ret;
588
589 ret = iio_backend_num_lanes_set(st->back, st->num_lanes);
590 if (ret)
591 return ret;
592
593 if (!st->lvds_cnv_en)
594 return 0;
595
596 /* Set maximum LVDS Data Transfer Latency */
597 ret = regmap_update_bits(st->regmap,
598 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
599 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
600 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
601 st->info->lvds_cnv_clk_cnt_max));
602 if (ret)
603 return ret;
604
605 if (st->num_lanes > 1) {
606 ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
607 AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES);
608 if (ret)
609 return ret;
610 }
611
612 ret = regmap_set_bits(st->regmap,
613 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
614 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN);
615 if (ret)
616 return ret;
617
618 return ad4080_lvds_sync_write(st);
619 }
620
ad4080_properties_parse(struct ad4080_state * st)621 static int ad4080_properties_parse(struct ad4080_state *st)
622 {
623 struct device *dev = regmap_get_device(st->regmap);
624
625 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable");
626
627 st->num_lanes = 1;
628 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes);
629 if (!st->num_lanes || st->num_lanes > 2)
630 return dev_err_probe(dev, -EINVAL,
631 "Invalid 'adi,num-lanes' value: %u",
632 st->num_lanes);
633
634 return 0;
635 }
636
ad4080_probe(struct spi_device * spi)637 static int ad4080_probe(struct spi_device *spi)
638 {
639 struct iio_dev *indio_dev;
640 struct device *dev = &spi->dev;
641 struct ad4080_state *st;
642 struct clk *clk;
643 int ret;
644
645 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
646 if (!indio_dev)
647 return -ENOMEM;
648
649 st = iio_priv(indio_dev);
650
651 ret = devm_regulator_bulk_get_enable(dev,
652 ARRAY_SIZE(ad4080_power_supplies),
653 ad4080_power_supplies);
654 if (ret)
655 return dev_err_probe(dev, ret,
656 "failed to get and enable supplies\n");
657
658 st->regmap = devm_regmap_init_spi(spi, &ad4080_regmap_config);
659 if (IS_ERR(st->regmap))
660 return PTR_ERR(st->regmap);
661
662 st->info = spi_get_device_match_data(spi);
663 if (!st->info)
664 return -ENODEV;
665
666 ret = devm_mutex_init(dev, &st->lock);
667 if (ret)
668 return ret;
669
670 indio_dev->name = st->info->name;
671 indio_dev->channels = st->info->channels;
672 indio_dev->num_channels = st->info->num_channels;
673 indio_dev->info = &ad4080_iio_info;
674
675 ret = ad4080_properties_parse(st);
676 if (ret)
677 return ret;
678
679 clk = devm_clk_get_enabled(&spi->dev, "cnv");
680 if (IS_ERR(clk))
681 return PTR_ERR(clk);
682
683 st->clk_rate = clk_get_rate(clk);
684
685 st->back = devm_iio_backend_get(dev, NULL);
686 if (IS_ERR(st->back))
687 return PTR_ERR(st->back);
688
689 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
690 if (ret)
691 return ret;
692
693 ret = devm_iio_backend_enable(dev, st->back);
694 if (ret)
695 return ret;
696
697 ret = ad4080_setup(indio_dev);
698 if (ret)
699 return ret;
700
701 return devm_iio_device_register(&spi->dev, indio_dev);
702 }
703
704 static const struct spi_device_id ad4080_id[] = {
705 { "ad4080", (kernel_ulong_t)&ad4080_chip_info },
706 { "ad4081", (kernel_ulong_t)&ad4081_chip_info },
707 { "ad4082", (kernel_ulong_t)&ad4082_chip_info },
708 { "ad4083", (kernel_ulong_t)&ad4083_chip_info },
709 { "ad4084", (kernel_ulong_t)&ad4084_chip_info },
710 { "ad4085", (kernel_ulong_t)&ad4085_chip_info },
711 { "ad4086", (kernel_ulong_t)&ad4086_chip_info },
712 { "ad4087", (kernel_ulong_t)&ad4087_chip_info },
713 { "ad4088", (kernel_ulong_t)&ad4088_chip_info },
714 { }
715 };
716 MODULE_DEVICE_TABLE(spi, ad4080_id);
717
718 static const struct of_device_id ad4080_of_match[] = {
719 { .compatible = "adi,ad4080", &ad4080_chip_info },
720 { .compatible = "adi,ad4081", &ad4081_chip_info },
721 { .compatible = "adi,ad4082", &ad4082_chip_info },
722 { .compatible = "adi,ad4083", &ad4083_chip_info },
723 { .compatible = "adi,ad4084", &ad4084_chip_info },
724 { .compatible = "adi,ad4085", &ad4085_chip_info },
725 { .compatible = "adi,ad4086", &ad4086_chip_info },
726 { .compatible = "adi,ad4087", &ad4087_chip_info },
727 { .compatible = "adi,ad4088", &ad4088_chip_info },
728 { }
729 };
730 MODULE_DEVICE_TABLE(of, ad4080_of_match);
731
732 static struct spi_driver ad4080_driver = {
733 .driver = {
734 .name = "ad4080",
735 .of_match_table = ad4080_of_match,
736 },
737 .probe = ad4080_probe,
738 .id_table = ad4080_id,
739 };
740 module_spi_driver(ad4080_driver);
741
742 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
743 MODULE_DESCRIPTION("Analog Devices AD4080");
744 MODULE_LICENSE("GPL");
745 MODULE_IMPORT_NS("IIO_BACKEND");
746