1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW_FW_H_
6 #define __RTW_FW_H_
7
8 #define H2C_PKT_SIZE 32
9 #define H2C_PKT_HDR_SIZE 8
10
11 /* FW bin information */
12 #define FW_HDR_SIZE 64
13 #define FW_HDR_CHKSUM_SIZE 8
14
15 #define FW_NLO_INFO_CHECK_SIZE 4
16
17 #define FIFO_PAGE_SIZE_SHIFT 12
18 #define FIFO_PAGE_SIZE 4096
19 #define FIFO_DUMP_ADDR 0x8000
20
21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12
22 #define DLFW_PAGE_SIZE_LEGACY 0x1000
23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2
24 #define DLFW_BLK_SIZE_LEGACY 4
25 #define FW_START_ADDR_LEGACY 0x1000
26
27 #define BCN_LOSS_CNT 10
28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0
29 #define BCN_FILTER_CONNECTION_LOSS 1
30 #define BCN_FILTER_CONNECTED 2
31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3
32 #define RTW_DEFAULT_CQM_THOLD -70
33 #define RTW_DEFAULT_CQM_HYST 4
34
35 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10)
36
37 #define RTW_CHANNEL_TIME 45
38 #define RTW_OFF_CHAN_TIME 100
39 #define RTW_PASS_CHAN_TIME 105
40 #define RTW_DFS_CHAN_TIME 20
41 #define RTW_CH_INFO_SIZE 4
42 #define RTW_EX_CH_INFO_SIZE 3
43 #define RTW_EX_CH_INFO_HDR_SIZE 2
44 #define RTW_SCAN_WIDTH 0
45 #define RTW_PRI_CH_IDX 1
46 #define RTW_OLD_PROBE_PG_CNT 2
47 #define RTW_PROBE_PG_CNT 4
48
49 #define RTW_DEBUG_DUMP_TIMES 10
50
51 enum rtw_c2h_cmd_id {
52 C2H_CCX_TX_RPT = 0x03,
53 C2H_BT_INFO = 0x09,
54 C2H_BT_MP_INFO = 0x0b,
55 C2H_BT_HID_INFO = 0x45,
56 C2H_RA_RPT = 0x0c,
57 C2H_HW_FEATURE_REPORT = 0x19,
58 C2H_WLAN_INFO = 0x27,
59 C2H_WLAN_RFON = 0x32,
60 C2H_BCN_FILTER_NOTIFY = 0x36,
61 C2H_ADAPTIVITY = 0x37,
62 C2H_SCAN_RESULT = 0x38,
63 C2H_HW_FEATURE_DUMP = 0xfd,
64 C2H_HALMAC = 0xff,
65 };
66
67 enum rtw_c2h_cmd_id_ext {
68 C2H_SCAN_STATUS_RPT = 0x3,
69 C2H_CCX_RPT = 0x0f,
70 C2H_CHAN_SWITCH = 0x22,
71 };
72
73 struct rtw_c2h_cmd {
74 u8 id;
75 u8 seq;
76 u8 payload[];
77 } __packed;
78
79 struct rtw_c2h_adaptivity {
80 u8 density;
81 u8 igi;
82 u8 l2h_th_init;
83 u8 l2h;
84 u8 h2l;
85 u8 option;
86 } __packed;
87
88 struct rtw_c2h_ra_rpt {
89 u8 rate_sgi;
90 u8 mac_id;
91 u8 byte2;
92 u8 status;
93 u8 byte4;
94 u8 ra_ratio;
95 u8 bw;
96 } __packed;
97
98 #define RTW_C2H_RA_RPT_RATE GENMASK(6, 0)
99 #define RTW_C2H_RA_RPT_SGI BIT(7)
100
101 struct rtw_h2c_register {
102 u32 w0;
103 u32 w1;
104 } __packed;
105
106 #define RTW_H2C_W0_CMDID GENMASK(7, 0)
107
108 /* H2C_CMD_DEFAULT_PORT command */
109 #define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)
110 #define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)
111
112 struct rtw_h2c_cmd {
113 __le32 msg;
114 __le32 msg_ext;
115 } __packed;
116
117 enum rtw_rsvd_packet_type {
118 RSVD_BEACON,
119 RSVD_DUMMY,
120 RSVD_PS_POLL,
121 RSVD_PROBE_RESP,
122 RSVD_NULL,
123 RSVD_QOS_NULL,
124 RSVD_LPS_PG_DPK,
125 RSVD_LPS_PG_INFO,
126 RSVD_PROBE_REQ,
127 RSVD_NLO_INFO,
128 RSVD_CH_INFO,
129 };
130
131 enum rtw_fw_rf_type {
132 FW_RF_1T2R = 0,
133 FW_RF_2T4R = 1,
134 FW_RF_2T2R = 2,
135 FW_RF_2T3R = 3,
136 FW_RF_1T1R = 4,
137 FW_RF_2T2R_GREEN = 5,
138 FW_RF_3T3R = 6,
139 FW_RF_3T4R = 7,
140 FW_RF_4T4R = 8,
141 FW_RF_MAX_TYPE = 0xF,
142 };
143
144 enum rtw_fw_feature {
145 FW_FEATURE_SIG = BIT(0),
146 FW_FEATURE_LPS_C2H = BIT(1),
147 FW_FEATURE_LCLK = BIT(2),
148 FW_FEATURE_PG = BIT(3),
149 FW_FEATURE_TX_WAKE = BIT(4),
150 FW_FEATURE_BCN_FILTER = BIT(5),
151 FW_FEATURE_NOTIFY_SCAN = BIT(6),
152 FW_FEATURE_ADAPTIVITY = BIT(7),
153 FW_FEATURE_SCAN_OFFLOAD = BIT(8),
154 FW_FEATURE_MAX = BIT(31),
155 };
156
157 enum rtw_fw_feature_ext {
158 FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0),
159 };
160
161 enum rtw_beacon_filter_offload_mode {
162 BCN_FILTER_OFFLOAD_MODE_0 = 0,
163 BCN_FILTER_OFFLOAD_MODE_1,
164 BCN_FILTER_OFFLOAD_MODE_2,
165 BCN_FILTER_OFFLOAD_MODE_3,
166
167 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
168 };
169
170 struct rtw_coex_info_req {
171 u8 seq;
172 u8 op_code;
173 u8 para1;
174 u8 para2;
175 u8 para3;
176 };
177
178 struct rtw_iqk_para {
179 u8 clear;
180 u8 segment_iqk;
181 };
182
183 struct rtw_lps_pg_dpk_hdr {
184 u16 dpk_path_ok;
185 u8 dpk_txagc[2];
186 u16 dpk_gs[2];
187 u32 coef[2][20];
188 u8 dpk_ch;
189 } __packed;
190
191 struct rtw_lps_pg_info_hdr {
192 u8 macid;
193 u8 mbssid;
194 u8 pattern_count;
195 u8 mu_tab_group_id;
196 u8 sec_cam_count;
197 u8 tx_bu_page_count;
198 u16 rsvd;
199 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
200 } __packed;
201
202 struct rtw_rsvd_page {
203 /* associated with each vif */
204 struct list_head vif_list;
205 struct rtw_vif *rtwvif;
206
207 /* associated when build rsvd page */
208 struct list_head build_list;
209
210 struct sk_buff *skb;
211 enum rtw_rsvd_packet_type type;
212 u8 page;
213 u16 tim_offset;
214 bool add_txdesc;
215 struct cfg80211_ssid *ssid;
216 u16 probe_req_size;
217 };
218
219 enum rtw_keep_alive_pkt_type {
220 KEEP_ALIVE_NULL_PKT = 0,
221 KEEP_ALIVE_ARP_RSP = 1,
222 };
223
224 struct rtw_nlo_info_hdr {
225 u8 nlo_count;
226 u8 hidden_ap_count;
227 u8 rsvd1[2];
228 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
229 u8 rsvd2[8];
230 u8 ssid_len[16];
231 u8 chiper[16];
232 u8 rsvd3[16];
233 u8 location[8];
234 } __packed;
235
236 enum rtw_packet_type {
237 RTW_PACKET_PROBE_REQ = 0x00,
238
239 RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
240 };
241
242 struct rtw_fw_wow_keep_alive_para {
243 bool adopt;
244 u8 pkt_type;
245 u8 period; /* unit: sec */
246 };
247
248 struct rtw_fw_wow_disconnect_para {
249 bool adopt;
250 u8 period; /* unit: sec */
251 u8 retry_count;
252 };
253
254 enum rtw_channel_type {
255 RTW_CHANNEL_PASSIVE,
256 RTW_CHANNEL_ACTIVE,
257 RTW_CHANNEL_RADAR,
258 };
259
260 enum rtw_scan_extra_id {
261 RTW_SCAN_EXTRA_ID_DFS,
262 };
263
264 enum rtw_scan_extra_info {
265 RTW_SCAN_EXTRA_ACTION_SCAN,
266 };
267
268 enum rtw_scan_report_code {
269 RTW_SCAN_REPORT_SUCCESS = 0x00,
270 RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
271 RTW_SCAN_REPORT_ERR_ID = 0x02,
272 RTW_SCAN_REPORT_ERR_TX = 0x03,
273 RTW_SCAN_REPORT_CANCELED = 0x10,
274 RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
275 RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
276 };
277
278 enum rtw_scan_notify_id {
279 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
280 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
281 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
282 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
283 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
284 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
285 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
286 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
287 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
288 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
289 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
290 };
291
292 enum rtw_scan_notify_status {
293 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
294 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
295 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
296 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
297 };
298
299 struct rtw_ch_switch_option {
300 u8 periodic_option;
301 u32 tsf_high;
302 u32 tsf_low;
303 u8 dest_ch_en;
304 u8 absolute_time_en;
305 u8 dest_ch;
306 u8 normal_period;
307 u8 normal_period_sel;
308 u8 normal_cycle;
309 u8 slow_period;
310 u8 slow_period_sel;
311 u8 nlo_en;
312 bool switch_en;
313 bool back_op_en;
314 };
315
316 struct rtw_fw_hdr {
317 __le16 signature;
318 u8 category;
319 u8 function;
320 __le16 version; /* 0x04 */
321 u8 subversion;
322 u8 subindex;
323 __le32 rsvd; /* 0x08 */
324 __le32 feature; /* 0x0C */
325 u8 month; /* 0x10 */
326 u8 day;
327 u8 hour;
328 u8 min;
329 __le16 year; /* 0x14 */
330 __le16 rsvd3;
331 u8 mem_usage; /* 0x18 */
332 u8 rsvd4[3];
333 __le16 h2c_fmt_ver; /* 0x1C */
334 __le16 rsvd5;
335 __le32 dmem_addr; /* 0x20 */
336 __le32 dmem_size;
337 __le32 rsvd6;
338 __le32 rsvd7;
339 __le32 imem_size; /* 0x30 */
340 __le32 emem_size;
341 __le32 emem_addr;
342 __le32 imem_addr;
343 } __packed;
344
345 struct rtw_fw_hdr_legacy {
346 __le16 signature;
347 u8 category;
348 u8 function;
349 __le16 version; /* 0x04 */
350 u8 subversion1;
351 u8 subversion2;
352 u8 month; /* 0x08 */
353 u8 day;
354 u8 hour;
355 u8 minute;
356 __le16 size;
357 __le16 rsvd2;
358 __le32 idx; /* 0x10 */
359 __le32 rsvd3;
360 __le32 rsvd4; /* 0x18 */
361 __le32 rsvd5;
362 } __packed;
363
364 #define RTW_FW_VER_CODE(ver, sub_ver, idx) \
365 (((ver) << 16) | ((sub_ver) << 8) | (idx))
366 #define RTW_FW_SUIT_VER_CODE(s) \
367 RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index)
368
369 /* C2H */
370 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc)
371 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0)
372 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc)
373 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0)
374
375 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff)
376
377 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2])
378 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3])
379 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4])
380
381 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf)
382 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10)
383 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100)
384
385 /* PKT H2C */
386 #define H2C_PKT_CMD_ID 0xFF
387 #define H2C_PKT_CATEGORY 0x01
388
389 #define H2C_PKT_GENERAL_INFO 0x0D
390 #define H2C_PKT_PHYDM_INFO 0x11
391 #define H2C_PKT_IQK 0x0E
392
393 #define H2C_PKT_CH_SWITCH 0x02
394 #define H2C_PKT_UPDATE_PKT 0x0C
395 #define H2C_PKT_SCAN_OFFLOAD 0x19
396
397 #define H2C_PKT_CH_SWITCH_LEN 0x20
398 #define H2C_PKT_UPDATE_PKT_LEN 0x4
399
400 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \
401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
402 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \
403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
404 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \
405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
406 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \
407 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
408
rtw_h2c_pkt_set_header(u8 * h2c_pkt,u8 sub_id)409 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
410 {
411 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
412 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
413 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
414 }
415
416 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
418 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
419 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
420
421 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
422 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
423 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
424 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
425 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
426 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
427 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
428 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
429 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
430 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
431 #define IQK_SET_CLEAR(h2c_pkt, value) \
432 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
433 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
434 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
435
436 #define CHSW_INFO_SET_CH(pkt, value) \
437 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
438 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \
439 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
440 #define CHSW_INFO_SET_BW(pkt, value) \
441 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
442 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \
443 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
444 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \
445 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
446 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \
447 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
448
449 #define CH_INFO_SET_CH(pkt, value) \
450 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
451 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \
452 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
453 #define CH_INFO_SET_BW(pkt, value) \
454 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
455 #define CH_INFO_SET_TIMEOUT(pkt, value) \
456 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
457 #define CH_INFO_SET_ACTION_ID(pkt, value) \
458 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
459 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \
460 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
461
462 #define EXTRA_CH_INFO_SET_ID(pkt, value) \
463 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
464 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \
465 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
466 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \
467 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
468 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \
469 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
470
471 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \
472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
473 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \
474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
475 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \
476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
477
478 #define CH_SWITCH_SET_START(h2c_pkt, value) \
479 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
480 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \
481 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
482 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \
483 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
484 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
485 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
486 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
487 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
488 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \
489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
490 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
491 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
492 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \
493 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
494 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \
495 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
496 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \
497 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
498 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \
499 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
500 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \
501 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
502 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \
503 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
504 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \
505 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
506 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \
507 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
508 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \
509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
510 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \
511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
512 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \
513 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
514 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \
515 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
516
517 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \
518 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
519 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \
520 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
521 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \
522 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
523 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \
524 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
525 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \
526 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
527 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \
528 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
529 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \
530 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
531 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \
532 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
533 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \
534 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
535 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \
536 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
537 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \
538 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
539 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \
540 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
541 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \
542 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
543 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \
544 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
545 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \
546 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
547 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \
548 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
549 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \
550 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
551
552 /* Command H2C */
553 #define H2C_CMD_RSVD_PAGE 0x0
554 #define H2C_CMD_MEDIA_STATUS_RPT 0x01
555 #define H2C_CMD_SET_PWR_MODE 0x20
556 #define H2C_CMD_LPS_PG_INFO 0x2b
557 #define H2C_CMD_DEFAULT_PORT 0x2c
558 #define H2C_CMD_RA_INFO 0x40
559 #define H2C_CMD_RSSI_MONITOR 0x42
560 #define H2C_CMD_RA_INFO_HI 0x46
561 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56
562 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57
563 #define H2C_CMD_WL_PHY_INFO 0x58
564 #define H2C_CMD_SCAN 0x59
565 #define H2C_CMD_ADAPTIVITY 0x5A
566
567 #define H2C_CMD_COEX_TDMA_TYPE 0x60
568 #define H2C_CMD_QUERY_BT_INFO 0x61
569 #define H2C_CMD_FORCE_BT_TX_POWER 0x62
570 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63
571 #define H2C_CMD_WL_CH_INFO 0x66
572 #define H2C_CMD_QUERY_BT_MP_INFO 0x67
573 #define H2C_CMD_BT_WIFI_CONTROL 0x69
574 #define H2C_CMD_WIFI_CALIBRATION 0x6d
575 #define H2C_CMD_QUERY_BT_HID_INFO 0x73
576
577 #define H2C_CMD_KEEP_ALIVE 0x03
578 #define H2C_CMD_DISCONNECT_DECISION 0x04
579 #define H2C_CMD_WOWLAN 0x80
580 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81
581 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82
582 #define H2C_CMD_NLO_INFO 0x8C
583
584 #define H2C_CMD_RECOVER_BT_DEV 0xD1
585
586 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
587 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
588
589 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
590 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
591 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
592 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
593
594 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \
595 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
596 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \
597 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
598 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \
599 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
600 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \
601 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
602 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \
603 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
604 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \
605 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
606 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \
607 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
608 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \
609 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
610 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \
611 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
612 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \
613 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
614 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \
615 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
616 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \
617 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
618
619 #define SET_SCAN_START(h2c_pkt, value) \
620 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
621
622 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \
623 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
624 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \
625 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
626 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \
627 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
628 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \
629 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
630 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \
631 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
632
633 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
634 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
635 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
636 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
637 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
638 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
639 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
640 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
641 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
642 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
643 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
644 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
645 #define LPS_PG_INFO_LOC(h2c_pkt, value) \
646 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
647 #define LPS_PG_DPK_LOC(h2c_pkt, value) \
648 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
649 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \
650 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
651 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \
652 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
653 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \
654 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
655 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \
656 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
657 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \
658 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
659 #define SET_RA_INFO_MACID(h2c_pkt, value) \
660 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
661 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \
662 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
663 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \
664 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
665 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \
666 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
667 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \
668 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
669 #define SET_RA_INFO_LDPC(h2c_pkt, value) \
670 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
671 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \
672 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
673 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \
674 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
675 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \
676 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
677 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \
678 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
679 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \
680 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
681 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \
682 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
683 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
684 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
685 #define SET_QUERY_BT_INFO(h2c_pkt, value) \
686 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
687 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
688 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
689 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
690 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
691 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \
692 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
693 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
694 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
695 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
696 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
697 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
698 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
699 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
700 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
701 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
702 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
703 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
704 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
705 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
706 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
707 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
708 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
709 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
710 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
711 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
712 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
713 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
714 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
715 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
716 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
717 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
718 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
719 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
720 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
721 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
722 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
723 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
724 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
725 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
726 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
727 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
728 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
729
730 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \
731 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
732 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \
733 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
734
735 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \
736 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
737 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \
738 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
739 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \
740 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
741 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \
742 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
743
744 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \
745 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
746 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \
747 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
748 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \
749 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
750 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \
751 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
752
753 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \
754 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
755 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \
756 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
757 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \
758 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
759 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \
760 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
761 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \
762 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
763 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \
764 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
765
766 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \
767 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
768 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \
769 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
770
771 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \
772 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
773 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \
774 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
775
776 #define SET_NLO_FUN_EN(h2c_pkt, value) \
777 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
778 #define SET_NLO_PS_32K(h2c_pkt, value) \
779 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
780 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \
781 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
782 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \
783 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
784
785 #define SET_RECOVER_BT_DEV_EN(h2c_pkt, value) \
786 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
787
788 #define GET_FW_DUMP_LEN(_header) \
789 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
790 #define GET_FW_DUMP_SEQ(_header) \
791 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
792 #define GET_FW_DUMP_MORE(_header) \
793 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
794 #define GET_FW_DUMP_VERSION(_header) \
795 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
796 #define GET_FW_DUMP_TLV_TYPE(_header) \
797 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
798 #define GET_FW_DUMP_TLV_LEN(_header) \
799 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
800 #define GET_FW_DUMP_TLV_VAL(_header) \
801 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
802
803 #define RFK_SET_INFORM_START(h2c_pkt, value) \
804 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
get_c2h_from_skb(struct sk_buff * skb)805 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
806 {
807 u32 pkt_offset;
808
809 pkt_offset = *((u32 *)skb->cb);
810 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
811 }
812
rtw_fw_feature_check(struct rtw_fw_state * fw,enum rtw_fw_feature feature)813 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
814 enum rtw_fw_feature feature)
815 {
816 return !!(fw->feature & feature);
817 }
818
rtw_fw_feature_ext_check(struct rtw_fw_state * fw,enum rtw_fw_feature_ext feature)819 static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw,
820 enum rtw_fw_feature_ext feature)
821 {
822 return !!(fw->feature_ext & feature);
823 }
824
825 void rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev);
826 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
827 struct sk_buff *skb);
828 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
829 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
830 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
831 void rtw_fw_default_port(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif);
832
833 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
834 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
835 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
836 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
837 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
838 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
839 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
840 struct rtw_coex_info_req *req);
841 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
842 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
843 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
844 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
845 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data);
846
847 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
848 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
849 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
850 bool reset_ra_mask);
851 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
852 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
853 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
854 struct ieee80211_vif *vif);
855 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
856 u8 *buf, u32 size);
857 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
858 struct rtw_vif *rtwvif);
859 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
860 struct rtw_vif *rtwvif);
861 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
862 struct rtw_vif *rtwvif);
863 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
864 struct rtw_vif *rtwvif);
865 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
866 void rtw_fw_update_beacon_work(struct work_struct *work);
867 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
868 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
869 u32 offset, u32 size, u32 *buf);
870 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
871 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
872 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
873 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
874 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
875 u8 pairwise_key_enc,
876 u8 group_key_enc);
877
878 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
879 void rtw_fw_set_recover_bt_device(struct rtw_dev *rtwdev);
880 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
881 struct cfg80211_ssid *ssid);
882 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
883 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
884 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
885 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
886 u32 *buffer);
887 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
888 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
889 void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup);
890 void rtw_clear_op_chan(struct rtw_dev *rtwdev);
891 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
892 struct ieee80211_scan_request *req);
893 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
894 bool aborted);
895 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
896 bool enable);
897 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
898 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
899 void rtw_hw_scan_abort(struct rtw_dev *rtwdev);
900 #endif
901