1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cortina Gemini SoC Clock Controller driver
4 * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
5 */
6
7 #define pr_fmt(fmt) "clk-gemini: " fmt
8
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/clk-provider.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/spinlock.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
24
25 /* Globally visible clocks */
26 static DEFINE_SPINLOCK(gemini_clk_lock);
27
28 #define GEMINI_GLOBAL_STATUS 0x04
29 #define PLL_OSC_SEL BIT(30)
30 #define AHBSPEED_SHIFT (15)
31 #define AHBSPEED_MASK 0x07
32 #define CPU_AHB_RATIO_SHIFT (18)
33 #define CPU_AHB_RATIO_MASK 0x03
34
35 #define GEMINI_GLOBAL_PLL_CONTROL 0x08
36
37 #define GEMINI_GLOBAL_SOFT_RESET 0x0c
38
39 #define GEMINI_GLOBAL_MISC_CONTROL 0x30
40 #define PCI_CLK_66MHZ BIT(18)
41
42 #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
43 #define PCI_CLKRUN_EN BIT(16)
44 #define TVC_HALFDIV_SHIFT (24)
45 #define TVC_HALFDIV_MASK 0x1f
46 #define SECURITY_CLK_SEL BIT(29)
47
48 #define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44
49 #define PCI_DLL_BYPASS BIT(31)
50 #define PCI_DLL_TAP_SEL_MASK 0x1f
51
52 /**
53 * struct gemini_gate_data - Gemini gated clocks
54 * @bit_idx: the bit used to gate this clock in the clock register
55 * @name: the clock name
56 * @parent_name: the name of the parent clock
57 * @flags: standard clock framework flags
58 */
59 struct gemini_gate_data {
60 u8 bit_idx;
61 const char *name;
62 const char *parent_name;
63 unsigned long flags;
64 };
65
66 /**
67 * struct clk_gemini_pci - Gemini PCI clock
68 * @hw: corresponding clock hardware entry
69 * @map: regmap to access the registers
70 */
71 struct clk_gemini_pci {
72 struct clk_hw hw;
73 struct regmap *map;
74 };
75
76 /**
77 * struct gemini_reset - gemini reset controller
78 * @map: regmap to access the containing system controller
79 * @rcdev: reset controller device
80 */
81 struct gemini_reset {
82 struct regmap *map;
83 struct reset_controller_dev rcdev;
84 };
85
86 /* Keeps track of all clocks */
87 static struct clk_hw_onecell_data *gemini_clk_data;
88
89 static const struct gemini_gate_data gemini_gates[] = {
90 { 1, "security-gate", "secdiv", 0 },
91 { 2, "gmac0-gate", "ahb", 0 },
92 { 3, "gmac1-gate", "ahb", 0 },
93 { 4, "sata0-gate", "ahb", 0 },
94 { 5, "sata1-gate", "ahb", 0 },
95 { 6, "usb0-gate", "ahb", 0 },
96 { 7, "usb1-gate", "ahb", 0 },
97 { 8, "ide-gate", "ahb", 0 },
98 { 9, "pci-gate", "ahb", 0 },
99 /*
100 * The DDR controller may never have a driver, but certainly must
101 * not be gated off.
102 */
103 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
104 /*
105 * The flash controller must be on to access NOR flash through the
106 * memory map.
107 */
108 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
109 { 12, "tvc-gate", "ahb", 0 },
110 { 13, "boot-gate", "apb", 0 },
111 };
112
113 #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
114
115 #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
116
gemini_pci_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)117 static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
118 unsigned long parent_rate)
119 {
120 struct clk_gemini_pci *pciclk = to_pciclk(hw);
121 u32 val;
122
123 regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
124 if (val & PCI_CLK_66MHZ)
125 return 66000000;
126 return 33000000;
127 }
128
gemini_pci_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)129 static int gemini_pci_determine_rate(struct clk_hw *hw,
130 struct clk_rate_request *req)
131 {
132 /* We support 33 and 66 MHz */
133 if (req->rate < 48000000)
134 req->rate = 33000000;
135 else
136 req->rate = 66000000;
137
138 return 0;
139 }
140
gemini_pci_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)141 static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
142 unsigned long parent_rate)
143 {
144 struct clk_gemini_pci *pciclk = to_pciclk(hw);
145
146 if (rate == 33000000)
147 return regmap_update_bits(pciclk->map,
148 GEMINI_GLOBAL_MISC_CONTROL,
149 PCI_CLK_66MHZ, 0);
150 if (rate == 66000000)
151 return regmap_update_bits(pciclk->map,
152 GEMINI_GLOBAL_MISC_CONTROL,
153 0, PCI_CLK_66MHZ);
154 return -EINVAL;
155 }
156
gemini_pci_enable(struct clk_hw * hw)157 static int gemini_pci_enable(struct clk_hw *hw)
158 {
159 struct clk_gemini_pci *pciclk = to_pciclk(hw);
160
161 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
162 0, PCI_CLKRUN_EN);
163 return 0;
164 }
165
gemini_pci_disable(struct clk_hw * hw)166 static void gemini_pci_disable(struct clk_hw *hw)
167 {
168 struct clk_gemini_pci *pciclk = to_pciclk(hw);
169
170 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
171 PCI_CLKRUN_EN, 0);
172 }
173
gemini_pci_is_enabled(struct clk_hw * hw)174 static int gemini_pci_is_enabled(struct clk_hw *hw)
175 {
176 struct clk_gemini_pci *pciclk = to_pciclk(hw);
177 unsigned int val;
178
179 regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
180 return !!(val & PCI_CLKRUN_EN);
181 }
182
183 static const struct clk_ops gemini_pci_clk_ops = {
184 .recalc_rate = gemini_pci_recalc_rate,
185 .determine_rate = gemini_pci_determine_rate,
186 .set_rate = gemini_pci_set_rate,
187 .enable = gemini_pci_enable,
188 .disable = gemini_pci_disable,
189 .is_enabled = gemini_pci_is_enabled,
190 };
191
gemini_pci_clk_setup(const char * name,const char * parent_name,struct regmap * map)192 static struct clk_hw *gemini_pci_clk_setup(const char *name,
193 const char *parent_name,
194 struct regmap *map)
195 {
196 struct clk_gemini_pci *pciclk;
197 struct clk_init_data init;
198 int ret;
199
200 pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
201 if (!pciclk)
202 return ERR_PTR(-ENOMEM);
203
204 init.name = name;
205 init.ops = &gemini_pci_clk_ops;
206 init.flags = 0;
207 init.parent_names = &parent_name;
208 init.num_parents = 1;
209 pciclk->map = map;
210 pciclk->hw.init = &init;
211
212 ret = clk_hw_register(NULL, &pciclk->hw);
213 if (ret) {
214 kfree(pciclk);
215 return ERR_PTR(ret);
216 }
217
218 return &pciclk->hw;
219 }
220
221 /*
222 * This is a self-deasserting reset controller.
223 */
gemini_reset(struct reset_controller_dev * rcdev,unsigned long id)224 static int gemini_reset(struct reset_controller_dev *rcdev,
225 unsigned long id)
226 {
227 struct gemini_reset *gr = to_gemini_reset(rcdev);
228
229 /* Manual says to always set BIT 30 (CPU1) to 1 */
230 return regmap_write(gr->map,
231 GEMINI_GLOBAL_SOFT_RESET,
232 BIT(GEMINI_RESET_CPU1) | BIT(id));
233 }
234
gemini_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)235 static int gemini_reset_assert(struct reset_controller_dev *rcdev,
236 unsigned long id)
237 {
238 return 0;
239 }
240
gemini_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)241 static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
242 unsigned long id)
243 {
244 return 0;
245 }
246
gemini_reset_status(struct reset_controller_dev * rcdev,unsigned long id)247 static int gemini_reset_status(struct reset_controller_dev *rcdev,
248 unsigned long id)
249 {
250 struct gemini_reset *gr = to_gemini_reset(rcdev);
251 u32 val;
252 int ret;
253
254 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
255 if (ret)
256 return ret;
257
258 return !!(val & BIT(id));
259 }
260
261 static const struct reset_control_ops gemini_reset_ops = {
262 .reset = gemini_reset,
263 .assert = gemini_reset_assert,
264 .deassert = gemini_reset_deassert,
265 .status = gemini_reset_status,
266 };
267
gemini_clk_probe(struct platform_device * pdev)268 static int gemini_clk_probe(struct platform_device *pdev)
269 {
270 /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
271 unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
272 unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
273 void __iomem *base;
274 struct gemini_reset *gr;
275 struct regmap *map;
276 struct clk_hw *hw;
277 struct device *dev = &pdev->dev;
278 struct device_node *np = dev->of_node;
279 unsigned int mult, div;
280 u32 val;
281 int ret;
282 int i;
283
284 gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
285 if (!gr)
286 return -ENOMEM;
287
288 /* Remap the system controller for the exclusive register */
289 base = devm_platform_ioremap_resource(pdev, 0);
290 if (IS_ERR(base))
291 return PTR_ERR(base);
292
293 map = syscon_node_to_regmap(np);
294 if (IS_ERR(map)) {
295 dev_err(dev, "no syscon regmap\n");
296 return PTR_ERR(map);
297 }
298
299 gr->map = map;
300 gr->rcdev.owner = THIS_MODULE;
301 gr->rcdev.nr_resets = 32;
302 gr->rcdev.ops = &gemini_reset_ops;
303 gr->rcdev.of_node = np;
304
305 ret = devm_reset_controller_register(dev, &gr->rcdev);
306 if (ret) {
307 dev_err(dev, "could not register reset controller\n");
308 return ret;
309 }
310
311 /* RTC clock 32768 Hz */
312 hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
313 gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
314
315 /* CPU clock derived as a fixed ratio from the AHB clock */
316 regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
317 val >>= CPU_AHB_RATIO_SHIFT;
318 val &= CPU_AHB_RATIO_MASK;
319 hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
320 cpu_ahb_mult[val],
321 cpu_ahb_div[val]);
322 gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
323
324 /* Security clock is 1:1 or 0.75 of APB */
325 regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
326 if (val & SECURITY_CLK_SEL) {
327 mult = 1;
328 div = 1;
329 } else {
330 mult = 3;
331 div = 4;
332 }
333 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
334
335 /*
336 * These are the leaf gates, at boot no clocks are gated.
337 */
338 for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
339 const struct gemini_gate_data *gd;
340
341 gd = &gemini_gates[i];
342 gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
343 clk_hw_register_gate(NULL, gd->name,
344 gd->parent_name,
345 gd->flags,
346 base + GEMINI_GLOBAL_CLOCK_CONTROL,
347 gd->bit_idx,
348 CLK_GATE_SET_TO_DISABLE,
349 &gemini_clk_lock);
350 }
351
352 /*
353 * The TV Interface Controller has a 5-bit half divider register.
354 * This clock is supposed to be 27MHz as this is an exact multiple
355 * of PAL and NTSC frequencies. The register is undocumented :(
356 * FIXME: figure out the parent and how the divider works.
357 */
358 mult = 1;
359 div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
360 dev_dbg(dev, "TVC half divider value = %d\n", div);
361 div += 1;
362 hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
363 gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
364
365 /* FIXME: very unclear what the parent is */
366 hw = gemini_pci_clk_setup("PCI", "xtal", map);
367 gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
368
369 /* FIXME: very unclear what the parent is */
370 hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
371 gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
372
373 return 0;
374 }
375
376 static const struct of_device_id gemini_clk_dt_ids[] = {
377 { .compatible = "cortina,gemini-syscon", },
378 { /* sentinel */ },
379 };
380
381 static struct platform_driver gemini_clk_driver = {
382 .probe = gemini_clk_probe,
383 .driver = {
384 .name = "gemini-clk",
385 .of_match_table = gemini_clk_dt_ids,
386 .suppress_bind_attrs = true,
387 },
388 };
389 builtin_platform_driver(gemini_clk_driver);
390
gemini_cc_init(struct device_node * np)391 static void __init gemini_cc_init(struct device_node *np)
392 {
393 struct regmap *map;
394 struct clk_hw *hw;
395 unsigned long freq;
396 unsigned int mult, div;
397 u32 val;
398 int ret;
399 int i;
400
401 gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,
402 GEMINI_NUM_CLKS),
403 GFP_KERNEL);
404 if (!gemini_clk_data)
405 return;
406 gemini_clk_data->num = GEMINI_NUM_CLKS;
407
408 /*
409 * This way all clock fetched before the platform device probes,
410 * except those we assign here for early use, will be deferred.
411 */
412 for (i = 0; i < GEMINI_NUM_CLKS; i++)
413 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
414
415 map = syscon_node_to_regmap(np);
416 if (IS_ERR(map)) {
417 pr_err("no syscon regmap\n");
418 return;
419 }
420 /*
421 * We check that the regmap works on this very first access,
422 * but as this is an MMIO-backed regmap, subsequent regmap
423 * access is not going to fail and we skip error checks from
424 * this point.
425 */
426 ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
427 if (ret) {
428 pr_err("failed to read global status register\n");
429 return;
430 }
431
432 /*
433 * XTAL is the crystal oscillator, 60 or 30 MHz selected from
434 * strap pin E6
435 */
436 if (val & PLL_OSC_SEL)
437 freq = 30000000;
438 else
439 freq = 60000000;
440 hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
441 pr_debug("main crystal @%lu MHz\n", freq / 1000000);
442
443 /* VCO clock derived from the crystal */
444 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
445 div = 2;
446 /* If we run on 30 MHz crystal we have to multiply with two */
447 if (val & PLL_OSC_SEL)
448 mult *= 2;
449 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
450
451 /* The AHB clock is always 1/3 of the VCO */
452 hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
453 gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
454
455 /* The APB clock is always 1/6 of the AHB */
456 hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
457 gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
458
459 /* Register the clocks to be accessed by the device tree */
460 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
461 }
462 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
463