1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_TYPE_H_ 5 #define _I40E_TYPE_H_ 6 7 #include <linux/bits.h> 8 #include <uapi/linux/if_ether.h> 9 #include "i40e_adminq.h" 10 #include "i40e_hmc.h" 11 12 #define I40E_MAX_VSI_QP 16 13 #define I40E_MAX_VF_VSI 4 14 #define I40E_MAX_CHAINED_RX_BUFFERS 5 15 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 16 17 /* Max default timeout in ms, */ 18 #define I40E_MAX_NVM_TIMEOUT 18000 19 20 /* Max timeout in ms for the phy to respond */ 21 #define I40E_MAX_PHY_TIMEOUT 500 22 23 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 24 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 25 26 /* forward declaration */ 27 struct i40e_hw; 28 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct libie_aq_desc *); 29 30 /* Data type manipulation macros. */ 31 32 #define I40E_DESC_UNUSED(R) \ 33 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 34 (R)->next_to_clean - (R)->next_to_use - 1) 35 36 /* bitfields for Tx queue mapping in QTX_CTL */ 37 #define I40E_QTX_CTL_VF_QUEUE 0x0 38 #define I40E_QTX_CTL_VM_QUEUE 0x1 39 #define I40E_QTX_CTL_PF_QUEUE 0x2 40 41 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_GLGEN_MSCA_STCODE_MASK(1) 42 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_GLGEN_MSCA_OPCODE_MASK(1) 43 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_GLGEN_MSCA_OPCODE_MASK(2) 44 45 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_GLGEN_MSCA_STCODE_MASK(0) 46 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_GLGEN_MSCA_OPCODE_MASK(0) 47 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_GLGEN_MSCA_OPCODE_MASK(1) 48 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_GLGEN_MSCA_OPCODE_MASK(3) 49 50 #define I40E_PHY_COM_REG_PAGE 0x1E 51 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0 52 #define I40E_PHY_LED_MANUAL_ON 0x100 53 #define I40E_PHY_LED_PROV_REG_1 0xC430 54 #define I40E_PHY_LED_MODE_MASK 0xFFFF 55 #define I40E_PHY_LED_MODE_ORIG 0x80000000 56 57 /* These are structs for managing the hardware information and the operations. 58 * The structures of function pointers are filled out at init time when we 59 * know for sure exactly which hardware we're working with. This gives us the 60 * flexibility of using the same main driver code but adapting to slightly 61 * different hardware needs as new parts are developed. For this architecture, 62 * the Firmware and AdminQ are intended to insulate the driver from most of the 63 * future changes, but these structures will also do part of the job. 64 */ 65 enum i40e_mac_type { 66 I40E_MAC_UNKNOWN = 0, 67 I40E_MAC_XL710, 68 I40E_MAC_X722, 69 I40E_MAC_GENERIC, 70 }; 71 72 enum i40e_media_type { 73 I40E_MEDIA_TYPE_UNKNOWN = 0, 74 I40E_MEDIA_TYPE_FIBER, 75 I40E_MEDIA_TYPE_BASET, 76 I40E_MEDIA_TYPE_BACKPLANE, 77 I40E_MEDIA_TYPE_CX4, 78 I40E_MEDIA_TYPE_DA, 79 I40E_MEDIA_TYPE_VIRTUAL 80 }; 81 82 enum i40e_fc_mode { 83 I40E_FC_NONE = 0, 84 I40E_FC_RX_PAUSE, 85 I40E_FC_TX_PAUSE, 86 I40E_FC_FULL, 87 I40E_FC_PFC, 88 I40E_FC_DEFAULT 89 }; 90 91 enum i40e_set_fc_aq_failures { 92 I40E_SET_FC_AQ_FAIL_NONE = 0, 93 I40E_SET_FC_AQ_FAIL_GET = 1, 94 I40E_SET_FC_AQ_FAIL_SET = 2, 95 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 96 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 97 }; 98 99 enum i40e_vsi_type { 100 I40E_VSI_MAIN = 0, 101 I40E_VSI_VMDQ1 = 1, 102 I40E_VSI_VMDQ2 = 2, 103 I40E_VSI_CTRL = 3, 104 I40E_VSI_FCOE = 4, 105 I40E_VSI_MIRROR = 5, 106 I40E_VSI_SRIOV = 6, 107 I40E_VSI_FDIR = 7, 108 I40E_VSI_IWARP = 8, 109 I40E_VSI_TYPE_UNKNOWN 110 }; 111 112 enum i40e_queue_type { 113 I40E_QUEUE_TYPE_RX = 0, 114 I40E_QUEUE_TYPE_TX, 115 I40E_QUEUE_TYPE_PE_CEQ, 116 I40E_QUEUE_TYPE_UNKNOWN 117 }; 118 119 struct i40e_link_status { 120 enum i40e_aq_phy_type phy_type; 121 enum i40e_aq_link_speed link_speed; 122 u8 link_info; 123 u8 an_info; 124 u8 req_fec_info; 125 u8 fec_info; 126 u8 ext_info; 127 u8 loopback; 128 /* is Link Status Event notification to SW enabled */ 129 bool lse_enable; 130 u16 max_frame_size; 131 bool crc_enable; 132 u8 pacing; 133 u8 requested_speeds; 134 u8 module_type[3]; 135 /* 1st byte: module identifier */ 136 #define I40E_MODULE_TYPE_SFP 0x03 137 /* 3rd byte: ethernet compliance codes for 1G */ 138 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 139 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 140 }; 141 142 struct i40e_phy_info { 143 struct i40e_link_status link_info; 144 struct i40e_link_status link_info_old; 145 bool get_link_info; 146 enum i40e_media_type media_type; 147 /* all the phy types the NVM is capable of */ 148 u64 phy_types; 149 }; 150 151 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) 152 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) 153 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) 154 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) 155 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) 156 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) 157 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) 158 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) 159 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) 160 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) 161 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) 162 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) 163 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) 164 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) 165 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) 166 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) 167 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) 168 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) 169 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) 170 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) 171 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) 172 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) 173 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) 174 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) 175 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) 176 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) 177 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ 178 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) 179 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) 180 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some 181 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit 182 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, 183 * a shift is needed to adjust for this with values larger than 31. The 184 * only affected values are I40E_PHY_TYPE_25GBASE_*. 185 */ 186 #define I40E_PHY_TYPE_OFFSET 1 187 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ 188 I40E_PHY_TYPE_OFFSET) 189 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ 190 I40E_PHY_TYPE_OFFSET) 191 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 192 I40E_PHY_TYPE_OFFSET) 193 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 194 I40E_PHY_TYPE_OFFSET) 195 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 196 I40E_PHY_TYPE_OFFSET) 197 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 198 I40E_PHY_TYPE_OFFSET) 199 /* Offset for 2.5G/5G PHY Types value to bit number conversion */ 200 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) 201 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T) 202 #define I40E_HW_CAP_MAX_GPIO 30 203 /* Capabilities of a PF or a VF or the whole device */ 204 struct i40e_hw_capabilities { 205 u32 switch_mode; 206 207 /* Cloud filter modes: 208 * Mode1: Filter on L4 port only 209 * Mode2: Filter for non-tunneled traffic 210 * Mode3: Filter for tunnel traffic 211 */ 212 #define I40E_CLOUD_FILTER_MODE1 0x6 213 #define I40E_CLOUD_FILTER_MODE2 0x7 214 #define I40E_SWITCH_MODE_MASK 0xF 215 216 u32 management_mode; 217 u32 mng_protocols_over_mctp; 218 u32 npar_enable; 219 u32 os2bmc; 220 u32 valid_functions; 221 bool sr_iov_1_1; 222 bool vmdq; 223 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 224 bool evb_802_1_qbh; /* Bridge Port Extension */ 225 bool dcb; 226 bool fcoe; 227 bool iscsi; /* Indicates iSCSI enabled */ 228 bool flex10_enable; 229 bool flex10_capable; 230 u32 flex10_mode; 231 232 u32 flex10_status; 233 234 bool sec_rev_disabled; 235 bool update_disabled; 236 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 237 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 238 239 bool mgmt_cem; 240 bool ieee_1588; 241 bool iwarp; 242 bool fd; 243 u32 fd_filters_guaranteed; 244 u32 fd_filters_best_effort; 245 bool rss; 246 u32 rss_table_size; 247 u32 rss_table_entry_width; 248 bool led[I40E_HW_CAP_MAX_GPIO]; 249 bool sdp[I40E_HW_CAP_MAX_GPIO]; 250 u32 nvm_image_type; 251 u32 num_flow_director_filters; 252 u32 num_vfs; 253 u32 vf_base_id; 254 u32 num_vsis; 255 u32 num_rx_qp; 256 u32 num_tx_qp; 257 u32 base_queue; 258 u32 num_msix_vectors; 259 u32 num_msix_vectors_vf; 260 u32 led_pin_num; 261 u32 sdp_pin_num; 262 u32 mdio_port_num; 263 u32 mdio_port_mode; 264 u8 rx_buf_chain_len; 265 u32 enabled_tcmap; 266 u32 maxtc; 267 u64 wr_csr_prot; 268 }; 269 270 struct i40e_mac_info { 271 enum i40e_mac_type type; 272 u8 addr[ETH_ALEN]; 273 u8 perm_addr[ETH_ALEN]; 274 u8 port_addr[ETH_ALEN]; 275 }; 276 277 enum i40e_aq_resources_ids { 278 I40E_NVM_RESOURCE_ID = 1 279 }; 280 281 enum i40e_aq_resource_access_type { 282 I40E_RESOURCE_READ = 1, 283 I40E_RESOURCE_WRITE 284 }; 285 286 struct i40e_nvm_info { 287 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 288 u32 timeout; /* [ms] */ 289 u16 sr_size; /* Shadow RAM size in words */ 290 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 291 u16 version; /* NVM package version */ 292 u32 eetrack; /* NVM data version */ 293 u32 oem_ver; /* OEM version info */ 294 }; 295 296 /* definitions used in NVM update support */ 297 298 enum i40e_nvmupd_cmd { 299 I40E_NVMUPD_INVALID, 300 I40E_NVMUPD_READ_CON, 301 I40E_NVMUPD_READ_SNT, 302 I40E_NVMUPD_READ_LCB, 303 I40E_NVMUPD_READ_SA, 304 I40E_NVMUPD_WRITE_ERA, 305 I40E_NVMUPD_WRITE_CON, 306 I40E_NVMUPD_WRITE_SNT, 307 I40E_NVMUPD_WRITE_LCB, 308 I40E_NVMUPD_WRITE_SA, 309 I40E_NVMUPD_CSUM_CON, 310 I40E_NVMUPD_CSUM_SA, 311 I40E_NVMUPD_CSUM_LCB, 312 I40E_NVMUPD_STATUS, 313 I40E_NVMUPD_EXEC_AQ, 314 I40E_NVMUPD_GET_AQ_RESULT, 315 I40E_NVMUPD_GET_AQ_EVENT, 316 }; 317 318 enum i40e_nvmupd_state { 319 I40E_NVMUPD_STATE_INIT, 320 I40E_NVMUPD_STATE_READING, 321 I40E_NVMUPD_STATE_WRITING, 322 I40E_NVMUPD_STATE_INIT_WAIT, 323 I40E_NVMUPD_STATE_WRITE_WAIT, 324 I40E_NVMUPD_STATE_ERROR 325 }; 326 327 /* nvm_access definition and its masks/shifts need to be accessible to 328 * application, core driver, and shared code. Where is the right file? 329 */ 330 #define I40E_NVM_READ 0xB 331 #define I40E_NVM_WRITE 0xC 332 333 #define I40E_NVM_MOD_PNT_MASK 0xFF 334 335 #define I40E_NVM_TRANS_SHIFT 8 336 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 337 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 338 #define I40E_NVM_PRESERVATION_FLAGS_MASK \ 339 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) 340 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 341 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 342 #define I40E_NVM_CON 0x0 343 #define I40E_NVM_SNT 0x1 344 #define I40E_NVM_LCB 0x2 345 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 346 #define I40E_NVM_ERA 0x4 347 #define I40E_NVM_CSUM 0x8 348 #define I40E_NVM_AQE 0xe 349 #define I40E_NVM_EXEC 0xf 350 351 352 #define I40E_NVMUPD_MAX_DATA 4096 353 354 struct i40e_nvm_access { 355 u32 command; 356 u32 config; 357 u32 offset; /* in bytes */ 358 u32 data_size; /* in bytes */ 359 u8 data[1]; 360 }; 361 362 /* (Q)SFP module access definitions */ 363 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0 364 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 365 #define I40E_MODULE_REVISION_ADDR 0x01 366 #define I40E_MODULE_SFF_8472_COMP 0x5E 367 #define I40E_MODULE_SFF_8472_SWAP 0x5C 368 #define I40E_MODULE_SFF_ADDR_MODE 0x04 369 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40 370 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D 371 #define I40E_MODULE_TYPE_QSFP28 0x11 372 #define I40E_MODULE_QSFP_MAX_LEN 640 373 374 /* PCI bus types */ 375 enum i40e_bus_type { 376 i40e_bus_type_unknown = 0, 377 i40e_bus_type_pci, 378 i40e_bus_type_pcix, 379 i40e_bus_type_pci_express, 380 i40e_bus_type_reserved 381 }; 382 383 /* PCI bus speeds */ 384 enum i40e_bus_speed { 385 i40e_bus_speed_unknown = 0, 386 i40e_bus_speed_33 = 33, 387 i40e_bus_speed_66 = 66, 388 i40e_bus_speed_100 = 100, 389 i40e_bus_speed_120 = 120, 390 i40e_bus_speed_133 = 133, 391 i40e_bus_speed_2500 = 2500, 392 i40e_bus_speed_5000 = 5000, 393 i40e_bus_speed_8000 = 8000, 394 i40e_bus_speed_reserved 395 }; 396 397 /* PCI bus widths */ 398 enum i40e_bus_width { 399 i40e_bus_width_unknown = 0, 400 i40e_bus_width_pcie_x1 = 1, 401 i40e_bus_width_pcie_x2 = 2, 402 i40e_bus_width_pcie_x4 = 4, 403 i40e_bus_width_pcie_x8 = 8, 404 i40e_bus_width_32 = 32, 405 i40e_bus_width_64 = 64, 406 i40e_bus_width_reserved 407 }; 408 409 /* Bus parameters */ 410 struct i40e_bus_info { 411 enum i40e_bus_speed speed; 412 enum i40e_bus_width width; 413 enum i40e_bus_type type; 414 415 u16 func; 416 u16 device; 417 u16 lan_id; 418 u16 bus_id; 419 }; 420 421 /* Flow control (FC) parameters */ 422 struct i40e_fc_info { 423 enum i40e_fc_mode current_mode; /* FC mode in effect */ 424 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 425 }; 426 427 #define I40E_MAX_TRAFFIC_CLASS 8 428 #define I40E_MAX_USER_PRIORITY 8 429 #define I40E_DCBX_MAX_APPS 32 430 #define I40E_LLDPDU_SIZE 1500 431 #define I40E_TLV_STATUS_OPER 0x1 432 #define I40E_TLV_STATUS_SYNC 0x2 433 #define I40E_TLV_STATUS_ERR 0x4 434 #define I40E_CEE_OPER_MAX_APPS 3 435 #define I40E_APP_PROTOID_FCOE 0x8906 436 #define I40E_APP_PROTOID_ISCSI 0x0cbc 437 #define I40E_APP_PROTOID_FIP 0x8914 438 #define I40E_APP_SEL_ETHTYPE 0x1 439 #define I40E_APP_SEL_TCPIP 0x2 440 #define I40E_CEE_APP_SEL_ETHTYPE 0x0 441 #define I40E_CEE_APP_SEL_TCPIP 0x1 442 443 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 444 struct i40e_dcb_ets_config { 445 u8 willing; 446 u8 cbs; 447 u8 maxtcs; 448 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 449 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 450 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 451 }; 452 453 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 454 struct i40e_dcb_pfc_config { 455 u8 willing; 456 u8 mbc; 457 u8 pfccap; 458 u8 pfcenable; 459 }; 460 461 /* CEE or IEEE 802.1Qaz Application Priority data */ 462 struct i40e_dcb_app_priority_table { 463 u8 priority; 464 u8 selector; 465 u16 protocolid; 466 }; 467 468 struct i40e_dcbx_config { 469 u8 dcbx_mode; 470 #define I40E_DCBX_MODE_CEE 0x1 471 #define I40E_DCBX_MODE_IEEE 0x2 472 u8 app_mode; 473 #define I40E_DCBX_APPS_NON_WILLING 0x1 474 u32 numapps; 475 u32 tlv_status; /* CEE mode TLV status */ 476 struct i40e_dcb_ets_config etscfg; 477 struct i40e_dcb_ets_config etsrec; 478 struct i40e_dcb_pfc_config pfc; 479 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 480 }; 481 482 enum i40e_hw_flags { 483 I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE, 484 I40E_HW_CAP_802_1AD, 485 I40E_HW_CAP_AQ_PHY_ACCESS, 486 I40E_HW_CAP_NVM_READ_REQUIRES_LOCK, 487 I40E_HW_CAP_FW_LLDP_STOPPABLE, 488 I40E_HW_CAP_FW_LLDP_PERSISTENT, 489 I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, 490 I40E_HW_CAP_X722_FEC_REQUEST, 491 I40E_HW_CAP_RSS_AQ, 492 I40E_HW_CAP_128_QP_RSS, 493 I40E_HW_CAP_ATR_EVICT, 494 I40E_HW_CAP_WB_ON_ITR, 495 I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, 496 I40E_HW_CAP_NO_PCI_LINK_CHECK, 497 I40E_HW_CAP_100M_SGMII, 498 I40E_HW_CAP_NO_DCB_SUPPORT, 499 I40E_HW_CAP_USE_SET_LLDP_MIB, 500 I40E_HW_CAP_GENEVE_OFFLOAD, 501 I40E_HW_CAP_PTP_L4, 502 I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, 503 I40E_HW_CAP_CRT_RETIMER, 504 I40E_HW_CAP_OUTER_UDP_CSUM, 505 I40E_HW_CAP_PHY_CONTROLS_LEDS, 506 I40E_HW_CAP_STOP_FW_LLDP, 507 I40E_HW_CAP_PORT_ID_VALID, 508 I40E_HW_CAP_RESTART_AUTONEG, 509 I40E_HW_CAPS_NBITS, 510 }; 511 512 /* Port hardware description */ 513 struct i40e_hw { 514 u8 __iomem *hw_addr; 515 516 /* subsystem structs */ 517 struct i40e_phy_info phy; 518 struct i40e_mac_info mac; 519 struct i40e_bus_info bus; 520 struct i40e_nvm_info nvm; 521 struct i40e_fc_info fc; 522 523 /* PBA ID */ 524 const char *pba_id; 525 526 /* pci info */ 527 u16 device_id; 528 u16 vendor_id; 529 u16 subsystem_device_id; 530 u16 subsystem_vendor_id; 531 u8 revision_id; 532 u8 port; 533 bool adapter_stopped; 534 535 /* capabilities for entire device and PCI func */ 536 struct i40e_hw_capabilities dev_caps; 537 struct i40e_hw_capabilities func_caps; 538 539 /* Flow Director shared filter space */ 540 u16 fdir_shared_filter_count; 541 542 /* device profile info */ 543 u8 pf_id; 544 u16 main_vsi_seid; 545 546 /* for multi-function MACs */ 547 u16 partition_id; 548 u16 num_partitions; 549 u16 num_ports; 550 551 /* Closest numa node to the device */ 552 u16 numa_node; 553 554 /* Admin Queue info */ 555 struct i40e_adminq_info aq; 556 557 /* state of nvm update process */ 558 enum i40e_nvmupd_state nvmupd_state; 559 struct libie_aq_desc nvm_wb_desc; 560 struct libie_aq_desc nvm_aq_event_desc; 561 struct i40e_virt_mem nvm_buff; 562 bool nvm_release_on_done; 563 u16 nvm_wait_opcode; 564 565 /* HMC info */ 566 struct i40e_hmc_info hmc; /* HMC info struct */ 567 568 /* LLDP/DCBX Status */ 569 u16 dcbx_status; 570 571 /* DCBX info */ 572 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 573 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 574 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 575 576 DECLARE_BITMAP(caps, I40E_HW_CAPS_NBITS); 577 578 /* Used in set switch config AQ command */ 579 u16 switch_tag; 580 u16 first_tag; 581 u16 second_tag; 582 583 /* debug mask */ 584 u32 debug_mask; 585 char err_str[16]; 586 }; 587 588 struct i40e_driver_version { 589 u8 major_version; 590 u8 minor_version; 591 u8 build_version; 592 u8 subbuild_version; 593 u8 driver_string[32]; 594 }; 595 596 /* RX Descriptors */ 597 union i40e_16byte_rx_desc { 598 struct { 599 __le64 pkt_addr; /* Packet buffer address */ 600 __le64 hdr_addr; /* Header buffer address */ 601 } read; 602 struct { 603 struct i40e_16b_rx_wb_qw0 { 604 struct { 605 union { 606 __le16 mirroring_status; 607 __le16 fcoe_ctx_id; 608 } mirr_fcoe; 609 __le16 l2tag1; 610 } lo_dword; 611 union { 612 __le32 rss; /* RSS Hash */ 613 __le32 fd_id; /* Flow director filter id */ 614 __le32 fcoe_param; /* FCoE DDP Context id */ 615 } hi_dword; 616 } qword0; 617 struct { 618 /* ext status/error/pktype/length */ 619 __le64 status_error_len; 620 } qword1; 621 } wb; /* writeback */ 622 struct { 623 u64 qword[2]; 624 } raw; 625 }; 626 627 union i40e_32byte_rx_desc { 628 struct { 629 __le64 pkt_addr; /* Packet buffer address */ 630 __le64 hdr_addr; /* Header buffer address */ 631 /* bit 0 of hdr_buffer_addr is DD bit */ 632 __le64 rsvd1; 633 __le64 rsvd2; 634 } read; 635 struct { 636 struct i40e_32b_rx_wb_qw0 { 637 struct { 638 union { 639 __le16 mirroring_status; 640 __le16 fcoe_ctx_id; 641 } mirr_fcoe; 642 __le16 l2tag1; 643 } lo_dword; 644 union { 645 __le32 rss; /* RSS Hash */ 646 __le32 fcoe_param; /* FCoE DDP Context id */ 647 /* Flow director filter id in case of 648 * Programming status desc WB 649 */ 650 __le32 fd_id; 651 } hi_dword; 652 } qword0; 653 struct { 654 /* status/error/pktype/length */ 655 __le64 status_error_len; 656 } qword1; 657 struct { 658 __le16 ext_status; /* extended status */ 659 __le16 rsvd; 660 __le16 l2tag2_1; 661 __le16 l2tag2_2; 662 } qword2; 663 struct { 664 union { 665 __le32 flex_bytes_lo; 666 __le32 pe_status; 667 } lo_dword; 668 union { 669 __le32 flex_bytes_hi; 670 __le32 fd_id; 671 } hi_dword; 672 } qword3; 673 } wb; /* writeback */ 674 struct { 675 u64 qword[4]; 676 } raw; 677 }; 678 679 enum i40e_rx_desc_status_bits { 680 /* Note: These are predefined bit offsets */ 681 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 682 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 683 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 684 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 685 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 686 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 687 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 688 /* Note: Bit 8 is reserved in X710 and XL710 */ 689 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 690 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 691 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 692 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 693 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 694 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 695 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 696 /* Note: For non-tunnel packets INT_UDP_0 is the right status for 697 * UDP header 698 */ 699 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 700 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 701 }; 702 703 #define I40E_RX_DESC_STATUS_FLTSTAT_MASK \ 704 GENMASK_ULL(I40E_RX_DESC_STATUS_FLTSTAT_SHIFT + 1, \ 705 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) 706 707 #define I40E_RXD_QW1_STATUS_SHIFT 0 708 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \ 709 << I40E_RXD_QW1_STATUS_SHIFT) 710 711 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 712 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 713 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 714 715 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 716 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \ 717 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 718 719 enum i40e_rx_desc_fltstat_values { 720 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 721 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 722 I40E_RX_DESC_FLTSTAT_RSV = 2, 723 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 724 }; 725 726 #define I40E_RXD_QW1_ERROR_SHIFT 19 727 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 728 729 enum i40e_rx_desc_error_bits { 730 /* Note: These are predefined bit offsets */ 731 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 732 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 733 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 734 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 735 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 736 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 737 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 738 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 739 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 740 }; 741 742 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 743 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 744 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 745 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 746 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 747 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 748 }; 749 750 #define I40E_RXD_QW1_PTYPE_SHIFT 30 751 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 752 753 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 754 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 755 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 756 757 758 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 759 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 760 761 enum i40e_rx_desc_ext_status_bits { 762 /* Note: These are predefined bit offsets */ 763 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 764 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 765 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 766 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 767 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 768 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 769 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 770 }; 771 772 enum i40e_rx_desc_pe_status_bits { 773 /* Note: These are predefined bit offsets */ 774 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 775 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 776 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 777 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 778 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 779 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 780 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 781 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 782 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 783 }; 784 785 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 786 787 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 788 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 789 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 790 791 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 792 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 793 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 794 795 enum i40e_rx_prog_status_desc_status_bits { 796 /* Note: These are predefined bit offsets */ 797 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 798 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 799 }; 800 801 enum i40e_rx_prog_status_desc_prog_id_masks { 802 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 803 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 804 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 805 }; 806 807 enum i40e_rx_prog_status_desc_error_bits { 808 /* Note: These are predefined bit offsets */ 809 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 810 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 811 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 812 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 813 }; 814 815 /* TX Descriptor */ 816 struct i40e_tx_desc { 817 __le64 buffer_addr; /* Address of descriptor's data buf */ 818 __le64 cmd_type_offset_bsz; 819 }; 820 821 822 enum i40e_tx_desc_dtype_value { 823 I40E_TX_DESC_DTYPE_DATA = 0x0, 824 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 825 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 826 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 827 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 828 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 829 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 830 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 831 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 832 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 833 }; 834 835 #define I40E_TXD_QW1_CMD_SHIFT 4 836 837 enum i40e_tx_desc_cmd_bits { 838 I40E_TX_DESC_CMD_EOP = 0x0001, 839 I40E_TX_DESC_CMD_RS = 0x0002, 840 I40E_TX_DESC_CMD_ICRC = 0x0004, 841 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 842 I40E_TX_DESC_CMD_DUMMY = 0x0010, 843 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 844 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 845 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 846 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 847 I40E_TX_DESC_CMD_FCOET = 0x0080, 848 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 849 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 850 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 851 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 852 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 853 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 854 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 855 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 856 }; 857 858 #define I40E_TXD_QW1_OFFSET_SHIFT 16 859 860 enum i40e_tx_desc_length_fields { 861 /* Note: These are predefined bit offsets */ 862 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 863 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 864 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 865 }; 866 867 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 868 869 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 870 871 /* Context descriptors */ 872 struct i40e_tx_context_desc { 873 __le32 tunneling_params; 874 __le16 l2tag2; 875 __le16 rsvd; 876 __le64 type_cmd_tso_mss; 877 }; 878 879 880 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 881 882 enum i40e_tx_ctx_desc_cmd_bits { 883 I40E_TX_CTX_DESC_TSO = 0x01, 884 I40E_TX_CTX_DESC_TSYN = 0x02, 885 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 886 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 887 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 888 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 889 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 890 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 891 I40E_TX_CTX_DESC_SWPE = 0x40 892 }; 893 894 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 895 896 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 897 898 899 900 enum i40e_tx_ctx_desc_eipt_offload { 901 I40E_TX_CTX_EXT_IP_NONE = 0x0, 902 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 903 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 904 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 905 }; 906 907 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 908 909 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 910 911 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 912 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 913 914 915 916 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 917 918 919 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 920 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 921 struct i40e_filter_program_desc { 922 __le32 qindex_flex_ptype_vsi; 923 __le32 rsvd; 924 __le32 dtype_cmd_cntindex; 925 __le32 fd_id; 926 }; 927 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 928 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 929 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 930 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 931 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 932 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 933 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 934 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 935 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 936 937 enum i40e_filter_program_desc_dest { 938 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 939 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 940 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 941 }; 942 943 enum i40e_filter_program_desc_fd_status { 944 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 945 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 946 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 947 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 948 }; 949 950 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 951 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 952 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 953 954 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 955 956 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 957 958 enum i40e_filter_program_desc_pcmd { 959 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 960 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 961 }; 962 963 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 964 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 965 966 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 967 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 968 969 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 970 I40E_TXD_FLTR_QW1_CMD_SHIFT) 971 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 972 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 973 974 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 975 I40E_TXD_FLTR_QW1_CMD_SHIFT) 976 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 977 978 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 979 I40E_TXD_FLTR_QW1_CMD_SHIFT) 980 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 981 982 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 983 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 984 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 985 986 enum i40e_filter_type { 987 I40E_FLOW_DIRECTOR_FLTR = 0, 988 I40E_PE_QUAD_HASH_FLTR = 1, 989 I40E_ETHERTYPE_FLTR, 990 I40E_FCOE_CTX_FLTR, 991 I40E_MAC_VLAN_FLTR, 992 I40E_HASH_FLTR 993 }; 994 995 struct i40e_vsi_context { 996 u16 seid; 997 u16 uplink_seid; 998 u16 vsi_number; 999 u16 vsis_allocated; 1000 u16 vsis_unallocated; 1001 u16 flags; 1002 u8 pf_num; 1003 u8 vf_num; 1004 u8 connection_type; 1005 struct i40e_aqc_vsi_properties_data info; 1006 }; 1007 1008 struct i40e_veb_context { 1009 u16 seid; 1010 u16 uplink_seid; 1011 u16 veb_number; 1012 u16 vebs_allocated; 1013 u16 vebs_unallocated; 1014 u16 flags; 1015 struct i40e_aqc_get_veb_parameters_completion info; 1016 }; 1017 1018 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1019 struct i40e_eth_stats { 1020 u64 rx_bytes; /* gorc */ 1021 u64 rx_unicast; /* uprc */ 1022 u64 rx_multicast; /* mprc */ 1023 u64 rx_broadcast; /* bprc */ 1024 u64 rx_discards; /* rdpc */ 1025 u64 rx_unknown_protocol; /* rupp */ 1026 u64 tx_bytes; /* gotc */ 1027 u64 tx_unicast; /* uptc */ 1028 u64 tx_multicast; /* mptc */ 1029 u64 tx_broadcast; /* bptc */ 1030 u64 tx_discards; /* tdpc */ 1031 u64 tx_errors; /* tepc */ 1032 u64 rx_discards_other; /* rxerr1 */ 1033 }; 1034 1035 /* Statistics collected per VEB per TC */ 1036 struct i40e_veb_tc_stats { 1037 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1038 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1039 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1040 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1041 }; 1042 1043 /* Statistics collected by the MAC */ 1044 struct i40e_hw_port_stats { 1045 /* eth stats collected by the port */ 1046 struct i40e_eth_stats eth; 1047 1048 /* additional port specific stats */ 1049 u64 tx_dropped_link_down; /* tdold */ 1050 u64 crc_errors; /* crcerrs */ 1051 u64 illegal_bytes; /* illerrc */ 1052 u64 error_bytes; /* errbc */ 1053 u64 mac_local_faults; /* mlfc */ 1054 u64 mac_remote_faults; /* mrfc */ 1055 u64 rx_length_errors; /* rlec */ 1056 u64 link_xon_rx; /* lxonrxc */ 1057 u64 link_xoff_rx; /* lxoffrxc */ 1058 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1059 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1060 u64 link_xon_tx; /* lxontxc */ 1061 u64 link_xoff_tx; /* lxofftxc */ 1062 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1063 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1064 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1065 u64 rx_size_64; /* prc64 */ 1066 u64 rx_size_127; /* prc127 */ 1067 u64 rx_size_255; /* prc255 */ 1068 u64 rx_size_511; /* prc511 */ 1069 u64 rx_size_1023; /* prc1023 */ 1070 u64 rx_size_1522; /* prc1522 */ 1071 u64 rx_size_big; /* prc9522 */ 1072 u64 rx_undersize; /* ruc */ 1073 u64 rx_fragments; /* rfc */ 1074 u64 rx_oversize; /* roc */ 1075 u64 rx_jabber; /* rjc */ 1076 u64 tx_size_64; /* ptc64 */ 1077 u64 tx_size_127; /* ptc127 */ 1078 u64 tx_size_255; /* ptc255 */ 1079 u64 tx_size_511; /* ptc511 */ 1080 u64 tx_size_1023; /* ptc1023 */ 1081 u64 tx_size_1522; /* ptc1522 */ 1082 u64 tx_size_big; /* ptc9522 */ 1083 u64 mac_short_packet_dropped; /* mspdc */ 1084 u64 checksum_error; /* xec */ 1085 /* flow director stats */ 1086 u64 fd_atr_match; 1087 u64 fd_sb_match; 1088 u64 fd_atr_tunnel_match; 1089 u32 fd_atr_status; 1090 u32 fd_sb_status; 1091 /* EEE LPI */ 1092 u32 tx_lpi_status; 1093 u32 rx_lpi_status; 1094 u64 tx_lpi_count; /* etlpic */ 1095 u64 rx_lpi_count; /* erlpic */ 1096 }; 1097 1098 /* Checksum and Shadow RAM pointers */ 1099 #define I40E_SR_NVM_CONTROL_WORD 0x00 1100 #define I40E_EMP_MODULE_PTR 0x0F 1101 #define I40E_SR_EMP_MODULE_PTR 0x48 1102 #define I40E_SR_PBA_FLAGS 0x15 1103 #define I40E_SR_PBA_BLOCK_PTR 0x16 1104 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1105 #define I40E_NVM_OEM_VER_OFF 0x83 1106 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1107 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1108 #define I40E_SR_NVM_EETRACK_LO 0x2D 1109 #define I40E_SR_NVM_EETRACK_HI 0x2E 1110 #define I40E_SR_VPD_PTR 0x2F 1111 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1112 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1113 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1114 1115 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1116 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1117 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1118 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1119 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1120 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1121 #define I40E_PTR_TYPE BIT(15) 1122 #define I40E_SR_OCP_CFG_WORD0 0x2B 1123 #define I40E_SR_OCP_ENABLED BIT(15) 1124 1125 /* Shadow RAM related */ 1126 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1127 #define I40E_SR_WORDS_IN_1KB 512 1128 /* Checksum should be calculated such that after adding all the words, 1129 * including the checksum word itself, the sum should be 0xBABA. 1130 */ 1131 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1132 1133 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1134 1135 enum i40e_switch_element_types { 1136 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1137 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1138 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1139 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1140 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1141 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1142 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1143 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1144 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1145 }; 1146 1147 /* Supported EtherType filters */ 1148 enum i40e_ether_type_index { 1149 I40E_ETHER_TYPE_1588 = 0, 1150 I40E_ETHER_TYPE_FIP = 1, 1151 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1152 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1153 I40E_ETHER_TYPE_LLDP = 4, 1154 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1155 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1156 I40E_ETHER_TYPE_QCN_CNM = 7, 1157 I40E_ETHER_TYPE_8021X = 8, 1158 I40E_ETHER_TYPE_ARP = 9, 1159 I40E_ETHER_TYPE_RSV1 = 10, 1160 I40E_ETHER_TYPE_RSV2 = 11, 1161 }; 1162 1163 /* Filter context base size is 1K */ 1164 #define I40E_HASH_FILTER_BASE_SIZE 1024 1165 /* Supported Hash filter values */ 1166 enum i40e_hash_filter_size { 1167 I40E_HASH_FILTER_SIZE_1K = 0, 1168 I40E_HASH_FILTER_SIZE_2K = 1, 1169 I40E_HASH_FILTER_SIZE_4K = 2, 1170 I40E_HASH_FILTER_SIZE_8K = 3, 1171 I40E_HASH_FILTER_SIZE_16K = 4, 1172 I40E_HASH_FILTER_SIZE_32K = 5, 1173 I40E_HASH_FILTER_SIZE_64K = 6, 1174 I40E_HASH_FILTER_SIZE_128K = 7, 1175 I40E_HASH_FILTER_SIZE_256K = 8, 1176 I40E_HASH_FILTER_SIZE_512K = 9, 1177 I40E_HASH_FILTER_SIZE_1M = 10, 1178 }; 1179 1180 /* DMA context base size is 0.5K */ 1181 #define I40E_DMA_CNTX_BASE_SIZE 512 1182 /* Supported DMA context values */ 1183 enum i40e_dma_cntx_size { 1184 I40E_DMA_CNTX_SIZE_512 = 0, 1185 I40E_DMA_CNTX_SIZE_1K = 1, 1186 I40E_DMA_CNTX_SIZE_2K = 2, 1187 I40E_DMA_CNTX_SIZE_4K = 3, 1188 I40E_DMA_CNTX_SIZE_8K = 4, 1189 I40E_DMA_CNTX_SIZE_16K = 5, 1190 I40E_DMA_CNTX_SIZE_32K = 6, 1191 I40E_DMA_CNTX_SIZE_64K = 7, 1192 I40E_DMA_CNTX_SIZE_128K = 8, 1193 I40E_DMA_CNTX_SIZE_256K = 9, 1194 }; 1195 1196 /* Supported Hash look up table (LUT) sizes */ 1197 enum i40e_hash_lut_size { 1198 I40E_HASH_LUT_SIZE_128 = 0, 1199 I40E_HASH_LUT_SIZE_512 = 1, 1200 }; 1201 1202 /* Structure to hold a per PF filter control settings */ 1203 struct i40e_filter_control_settings { 1204 /* number of PE Quad Hash filter buckets */ 1205 enum i40e_hash_filter_size pe_filt_num; 1206 /* number of PE Quad Hash contexts */ 1207 enum i40e_dma_cntx_size pe_cntx_num; 1208 /* number of FCoE filter buckets */ 1209 enum i40e_hash_filter_size fcoe_filt_num; 1210 /* number of FCoE DDP contexts */ 1211 enum i40e_dma_cntx_size fcoe_cntx_num; 1212 /* size of the Hash LUT */ 1213 enum i40e_hash_lut_size hash_lut_size; 1214 /* enable FDIR filters for PF and its VFs */ 1215 bool enable_fdir; 1216 /* enable Ethertype filters for PF and its VFs */ 1217 bool enable_ethtype; 1218 /* enable MAC/VLAN filters for PF and its VFs */ 1219 bool enable_macvlan; 1220 }; 1221 1222 /* Structure to hold device level control filter counts */ 1223 struct i40e_control_filter_stats { 1224 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1225 u16 etype_used; /* Used perfect EtherType filters */ 1226 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1227 u16 etype_free; /* Un-used perfect EtherType filters */ 1228 }; 1229 1230 enum i40e_reset_type { 1231 I40E_RESET_POR = 0, 1232 I40E_RESET_CORER = 1, 1233 I40E_RESET_GLOBR = 2, 1234 I40E_RESET_EMPR = 3, 1235 }; 1236 1237 /* IEEE 802.1AB LLDP Agent Variables from NVM */ 1238 #define I40E_NVM_LLDP_CFG_PTR 0x06 1239 #define I40E_SR_LLDP_CFG_PTR 0x31 1240 struct i40e_lldp_variables { 1241 u16 length; 1242 u16 adminstatus; 1243 u16 msgfasttx; 1244 u16 msgtxinterval; 1245 u16 txparams; 1246 u16 timers; 1247 u16 crc8; 1248 }; 1249 1250 /* Offsets into Alternate Ram */ 1251 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1252 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1253 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1254 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1255 1256 /* Alternate Ram Bandwidth Masks */ 1257 #define I40E_ALT_BW_VALUE_MASK 0xFF 1258 #define I40E_ALT_BW_VALID_MASK 0x80000000 1259 1260 /* RSS Hash Table Size */ 1261 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1262 1263 /* INPUT SET MASK for RSS, flow director, and flexible payload */ 1264 #define I40E_X722_L3_SRC_SHIFT 49 1265 #define I40E_X722_L3_SRC_MASK (0x3ULL << I40E_X722_L3_SRC_SHIFT) 1266 #define I40E_X722_L3_DST_SHIFT 41 1267 #define I40E_X722_L3_DST_MASK (0x3ULL << I40E_X722_L3_DST_SHIFT) 1268 #define I40E_L3_SRC_SHIFT 47 1269 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) 1270 #define I40E_L3_V6_SRC_SHIFT 43 1271 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT) 1272 #define I40E_L3_DST_SHIFT 35 1273 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT) 1274 #define I40E_L3_V6_DST_SHIFT 35 1275 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) 1276 #define I40E_L4_SRC_SHIFT 34 1277 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) 1278 #define I40E_L4_DST_SHIFT 33 1279 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) 1280 #define I40E_VERIFY_TAG_SHIFT 31 1281 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) 1282 #define I40E_VLAN_SRC_SHIFT 55 1283 #define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT) 1284 1285 #define I40E_FLEX_50_SHIFT 13 1286 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) 1287 #define I40E_FLEX_51_SHIFT 12 1288 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) 1289 #define I40E_FLEX_52_SHIFT 11 1290 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) 1291 #define I40E_FLEX_53_SHIFT 10 1292 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT) 1293 #define I40E_FLEX_54_SHIFT 9 1294 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1295 #define I40E_FLEX_55_SHIFT 8 1296 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1297 #define I40E_FLEX_56_SHIFT 7 1298 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1299 #define I40E_FLEX_57_SHIFT 6 1300 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) 1301 1302 /* Version format for Dynamic Device Personalization(DDP) */ 1303 struct i40e_ddp_version { 1304 u8 major; 1305 u8 minor; 1306 u8 update; 1307 u8 draft; 1308 }; 1309 1310 #define I40E_DDP_NAME_SIZE 32 1311 1312 /* Package header */ 1313 struct i40e_package_header { 1314 struct i40e_ddp_version version; 1315 u32 segment_count; 1316 u32 segment_offset[]; 1317 }; 1318 1319 /* Generic segment header */ 1320 struct i40e_generic_seg_header { 1321 #define SEGMENT_TYPE_METADATA 0x00000001 1322 #define SEGMENT_TYPE_I40E 0x00000011 1323 u32 type; 1324 struct i40e_ddp_version version; 1325 u32 size; 1326 char name[I40E_DDP_NAME_SIZE]; 1327 }; 1328 1329 struct i40e_metadata_segment { 1330 struct i40e_generic_seg_header header; 1331 struct i40e_ddp_version version; 1332 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF 1333 u32 track_id; 1334 char name[I40E_DDP_NAME_SIZE]; 1335 }; 1336 1337 struct i40e_device_id_entry { 1338 u32 vendor_dev_id; 1339 u32 sub_vendor_dev_id; 1340 }; 1341 1342 struct i40e_profile_segment { 1343 struct i40e_generic_seg_header header; 1344 struct i40e_ddp_version version; 1345 char name[I40E_DDP_NAME_SIZE]; 1346 u32 device_table_count; 1347 struct i40e_device_id_entry device_table[]; 1348 }; 1349 1350 struct i40e_section_table { 1351 u32 section_count; 1352 u32 section_offset[]; 1353 }; 1354 1355 struct i40e_profile_section_header { 1356 u16 tbl_size; 1357 u16 data_end; 1358 struct { 1359 #define SECTION_TYPE_INFO 0x00000010 1360 #define SECTION_TYPE_MMIO 0x00000800 1361 #define SECTION_TYPE_RB_MMIO 0x00001800 1362 #define SECTION_TYPE_AQ 0x00000801 1363 #define SECTION_TYPE_RB_AQ 0x00001801 1364 #define SECTION_TYPE_NOTE 0x80000000 1365 u32 type; 1366 u32 offset; 1367 u32 size; 1368 } section; 1369 }; 1370 1371 struct i40e_profile_tlv_section_record { 1372 u8 rtype; 1373 u8 type; 1374 u16 len; 1375 u8 data[12]; 1376 }; 1377 1378 /* Generic AQ section in proflie */ 1379 struct i40e_profile_aq_section { 1380 u16 opcode; 1381 u16 flags; 1382 u8 param[16]; 1383 u16 datalen; 1384 u8 data[]; 1385 }; 1386 1387 struct i40e_profile_info { 1388 u32 track_id; 1389 struct i40e_ddp_version version; 1390 u8 op; 1391 #define I40E_DDP_ADD_TRACKID 0x01 1392 #define I40E_DDP_REMOVE_TRACKID 0x02 1393 u8 reserved[7]; 1394 u8 name[I40E_DDP_NAME_SIZE]; 1395 }; 1396 #endif /* _I40E_TYPE_H_ */ 1397