1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __HAL_COMMON_REG_H__ 8 #define __HAL_COMMON_REG_H__ 9 10 /* */ 11 /* */ 12 /* 0x0000h ~ 0x00FFh System Configuration */ 13 /* */ 14 /* */ 15 #define REG_SYS_FUNC_EN 0x0002 16 #define REG_APS_FSMCO 0x0004 17 #define REG_SYS_CLKR 0x0008 18 #define REG_9346CR 0x000A 19 #define REG_SYS_EEPROM_CTRL 0x000A 20 #define REG_RSV_CTRL 0x001C 21 #define REG_RF_CTRL 0x001F 22 #define REG_AFE_XTAL_CTRL 0x0024 23 #define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */ 24 #define REG_EFUSE_CTRL 0x0030 25 #define REG_EFUSE_TEST 0x0034 26 #define REG_PWR_DATA 0x0038 27 #define REG_GPIO_MUXCFG 0x0040 28 #define REG_GPIO_INTM 0x0048 29 #define REG_LEDCFG0 0x004C 30 #define REG_LEDCFG2 0x004E 31 #define REG_HSIMR 0x0058 32 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 33 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 34 #define REG_MCUFWDL 0x0080 35 #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ 36 #define REG_SYS_CFG 0x00F0 37 #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ 38 39 /* */ 40 /* */ 41 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 42 /* */ 43 /* */ 44 #define REG_CR 0x0100 45 #define REG_PBP 0x0104 46 #define REG_TRXDMA_CTRL 0x010C 47 #define REG_TRXFF_BNDY 0x0114 48 #define REG_HIMR 0x0120 49 #define REG_HISR 0x0124 50 51 #define REG_C2HEVT_MSG_NORMAL 0x01A0 52 #define REG_C2HEVT_CLEAR 0x01AF 53 #define REG_HMETFR 0x01CC 54 #define REG_HMEBOX_0 0x01D0 55 56 /* */ 57 /* */ 58 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 59 /* */ 60 /* */ 61 #define REG_RQPN 0x0200 62 #define REG_TDECTRL 0x0208 63 #define REG_TXDMA_STATUS 0x0210 64 #define REG_RQPN_NPQ 0x0214 65 #define REG_AUTO_LLT 0x0224 66 67 68 /* */ 69 /* */ 70 /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 71 /* */ 72 /* */ 73 #define REG_RXDMA_AGG_PG_TH 0x0280 74 #define REG_RXPKT_NUM 0x0284 75 76 /* */ 77 /* */ 78 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 79 /* */ 80 /* */ 81 #define REG_TXPKT_EMPTY 0x041A 82 #define REG_FWHW_TXQ_CTRL 0x0420 83 #define REG_HWSEQ_CTRL 0x0423 84 #define REG_SPEC_SIFS 0x0428 85 #define REG_RL 0x042A 86 #define REG_RRSR 0x0440 87 88 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 89 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 90 #define REG_BAR_MODE_CTRL 0x04CC 91 #define REG_EARLY_MODE_CONTROL 0x04D0 92 #define REG_MACID_SLEEP 0x04D4 93 #define REG_NQOS_SEQ 0x04DC 94 95 /* */ 96 /* */ 97 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 98 /* */ 99 /* */ 100 #define REG_EDCA_VO_PARAM 0x0500 101 #define REG_EDCA_VI_PARAM 0x0504 102 #define REG_EDCA_BE_PARAM 0x0508 103 #define REG_EDCA_BK_PARAM 0x050C 104 #define REG_BCNTCFG 0x0510 105 #define REG_SIFS_CTX 0x0514 106 #define REG_SIFS_TRX 0x0516 107 #define REG_TSFTR_SYN_OFFSET 0x0518 108 #define REG_SLOT 0x051B 109 #define REG_TXPAUSE 0x0522 110 #define REG_RD_CTRL 0x0524 111 /* */ 112 /* Format for offset 540h-542h: */ 113 /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ 114 /* [7:4]: Reserved. */ 115 /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ 116 /* [23:20]: Reserved */ 117 /* Description: */ 118 /* | */ 119 /* |<--Setup--|--Hold------------>| */ 120 /* --------------|---------------------- */ 121 /* | */ 122 /* TBTT */ 123 /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 124 /* Described by Designer Tim and Bruce, 2011-01-14. */ 125 /* */ 126 #define REG_TBTT_PROHIBIT 0x0540 127 #define REG_BCN_CTRL 0x0550 128 #define REG_BCN_CTRL_1 0x0551 129 #define REG_DUAL_TSF_RST 0x0553 130 #define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ 131 #define REG_DRVERLYINT 0x0558 132 #define REG_BCNDMATIM 0x0559 133 #define REG_ATIMWND 0x055A 134 #define REG_BCN_MAX_ERR 0x055D 135 #define REG_RXTSF_OFFSET_CCK 0x055E 136 #define REG_RXTSF_OFFSET_OFDM 0x055F 137 #define REG_TSFTR 0x0560 138 #define REG_ACMHWCTRL 0x05C0 139 140 /* */ 141 /* */ 142 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 143 /* */ 144 /* */ 145 #define REG_BWOPMODE 0x0603 146 #define REG_TCR 0x0604 147 #define REG_RCR 0x0608 148 #define REG_RX_DRVINFO_SZ 0x060F 149 150 #define REG_MACID 0x0610 151 #define REG_BSSID 0x0618 152 #define REG_MAR 0x0620 153 154 #define REG_MAC_SPEC_SIFS 0x063A 155 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 156 #define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 157 #define REG_RESP_SIFS_OFDM 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 158 159 #define REG_ACKTO 0x0640 160 161 /* */ 162 /* Note: */ 163 /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */ 164 /* always too small, but the WiFi TestPlan test by 25, 000 microseconds of NAV through sending */ 165 /* CTS in the air. We must update this value greater than 25, 000 microseconds to pass the item. */ 166 /* The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */ 167 /* by SD1 Scott. */ 168 /* By Bruce, 2011-07-18. */ 169 /* */ 170 #define REG_NAV_UPPER 0x0652 /* unit of 128 */ 171 172 /* WMA, BA, CCX */ 173 #define REG_RXERR_RPT 0x0664 174 175 /* Security */ 176 #define REG_CAMCMD 0x0670 177 #define REG_CAMWRITE 0x0674 178 #define REG_CAMREAD 0x0678 179 #define REG_SECCFG 0x0680 180 181 /* Power */ 182 #define REG_RXFLTMAP0 0x06A0 183 #define REG_RXFLTMAP1 0x06A2 184 #define REG_RXFLTMAP2 0x06A4 185 #define REG_BCN_PSR_RPT 0x06A8 186 187 /* */ 188 /* */ 189 /* Redifine 8192C register definition for compatibility */ 190 /* */ 191 /* */ 192 #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ 193 #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ 194 #define MSR (REG_CR + 2) /* Media Status register */ 195 196 #define PBP REG_PBP 197 198 /* */ 199 /* 9. Security Control Registers (Offset:) */ 200 /* */ 201 #define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ 202 #define WCAMI REG_CAMWRITE /* Software write CAM input content */ 203 204 /* */ 205 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 206 /* */ 207 #define HSISR_GPIO12_0_INT BIT0 208 #define HSISR_SPS_OCP_INT BIT5 209 #define HSISR_RON_INT BIT6 210 #define HSISR_PDNINT BIT7 211 #define HSISR_GPIO9_INT BIT25 212 213 /* */ 214 /* Response Rate Set Register (offset 0x440, 24bits) */ 215 /* */ 216 #define RRSR_1M BIT0 217 #define RRSR_2M BIT1 218 #define RRSR_5_5M BIT2 219 #define RRSR_11M BIT3 220 #define RRSR_6M BIT4 221 #define RRSR_12M BIT6 222 #define RRSR_24M BIT8 223 224 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M) 225 226 /* */ 227 /* Rate Definition */ 228 /* */ 229 /* CCK */ 230 #define RATE_1M BIT(0) 231 #define RATE_2M BIT(1) 232 #define RATE_5_5M BIT(2) 233 #define RATE_11M BIT(3) 234 /* OFDM */ 235 #define RATE_6M BIT(4) 236 #define RATE_9M BIT(5) 237 #define RATE_12M BIT(6) 238 #define RATE_18M BIT(7) 239 #define RATE_24M BIT(8) 240 #define RATE_36M BIT(9) 241 #define RATE_48M BIT(10) 242 #define RATE_54M BIT(11) 243 244 /* ALL CCK Rate */ 245 #define RATE_BITMAP_ALL 0xFFFFF 246 247 /* Only use CCK 1M rate for ACK */ 248 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 249 250 /* */ 251 /* BW_OPMODE bits (Offset 0x603, 8bit) */ 252 /* */ 253 #define BW_OPMODE_20MHZ BIT2 254 255 /* */ 256 /* CAM Config Setting (offset 0x680, 1 byte) */ 257 /* */ 258 #define CAM_VALID BIT15 259 260 #define CAM_CONTENT_COUNT 8 261 262 #define CAM_AES 0x04 263 264 #define TOTAL_CAM_ENTRY 32 265 266 #define CAM_WRITE BIT16 267 #define CAM_POLLINIG BIT31 268 269 /* */ 270 /* 12. Host Interrupt Status Registers */ 271 /* */ 272 273 /* */ 274 /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ 275 /* */ 276 #define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ 277 #define RCR_APP_MIC BIT30 /* MACRX will retain the MIC at the bottom of the packet. */ 278 #define RCR_APP_ICV BIT29 /* MACRX will retain the ICV at the bottom of the packet. */ 279 #define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */ 280 #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 281 #define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC = 1 MFC-->HTC = 0 */ 282 #define RCR_AMF BIT13 /* Accept management type frame */ 283 #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ 284 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ 285 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ 286 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ 287 #define RCR_AB BIT3 /* Accept broadcast packet */ 288 #define RCR_AM BIT2 /* Accept multicast packet */ 289 #define RCR_APM BIT1 /* Accept physical match packet */ 290 291 292 /* */ 293 /* */ 294 /* 0x0000h ~ 0x00FFh System Configuration */ 295 /* */ 296 /* */ 297 298 /* 2 SYS_FUNC_EN */ 299 #define FEN_BBRSTB BIT(0) 300 #define FEN_BB_GLB_RSTn BIT(1) 301 #define FEN_DIO_PCIE BIT(5) 302 #define FEN_PCIEA BIT(6) 303 #define FEN_PPLL BIT(7) 304 #define FEN_CPUEN BIT(10) 305 #define FEN_ELDR BIT(12) 306 307 /* 2 APS_FSMCO */ 308 #define EnPDN BIT(4) 309 310 /* 2 SYS_CLKR */ 311 #define ANA8M BIT(1) 312 #define LOADER_CLK_EN BIT(5) 313 314 315 /* 2 9346CR /REG_SYS_EEPROM_CTRL */ 316 #define BOOT_FROM_EEPROM BIT(4) 317 #define EEPROM_EN BIT(5) 318 319 320 /* 2 RF_CTRL */ 321 #define RF_EN BIT(0) 322 #define RF_RSTB BIT(1) 323 #define RF_SDMRSTB BIT(2) 324 325 /* 2 EFUSE_TEST (For RTL8723 partially) */ 326 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 327 #define EFUSE_SEL_MASK 0x300 328 #define EFUSE_WIFI_SEL_0 0x0 329 #define EFUSE_BT_SEL_0 0x1 330 #define EFUSE_BT_SEL_1 0x2 331 #define EFUSE_BT_SEL_2 0x3 332 333 334 /* 2 8051FWDL */ 335 /* 2 MCUFWDL */ 336 #define MCUFWDL_RDY BIT(1) 337 #define FWDL_ChkSum_rpt BIT(2) 338 #define WINTINI_RDY BIT(6) 339 #define RAM_DL_SEL BIT(7) 340 341 /* 2 REG_SYS_CFG */ 342 #define VENDOR_ID BIT(19) 343 344 #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ 345 #define SPS_SEL BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */ 346 347 348 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 349 #define CHIP_VER_RTL_SHIFT 12 350 351 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */ 352 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 353 354 /* */ 355 /* */ 356 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 357 /* */ 358 /* */ 359 360 /* 2 Function Enable Registers */ 361 /* 2 CR */ 362 #define HCI_TXDMA_EN BIT(0) 363 #define HCI_RXDMA_EN BIT(1) 364 #define TXDMA_EN BIT(2) 365 #define RXDMA_EN BIT(3) 366 #define PROTOCOL_EN BIT(4) 367 #define SCHEDULE_EN BIT(5) 368 #define MACTXEN BIT(6) 369 #define MACRXEN BIT(7) 370 #define ENSWBCN BIT(8) 371 #define ENSEC BIT(9) 372 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 373 374 /* Network type */ 375 #define _NETTYPE(x) (((x) & 0x3) << 16) 376 #define MASK_NETTYPE 0x30000 377 #define NT_LINK_AD_HOC 0x1 378 #define NT_LINK_AP 0x2 379 380 /* 2 PBP - Page Size Register */ 381 #define _PSRX(x) (x) 382 #define _PSTX(x) ((x) << 4) 383 384 #define PBP_128 0x1 385 386 /* 2 TX/RXDMA */ 387 #define RXDMA_AGG_EN BIT(2) 388 389 /* For normal driver, 0x10C */ 390 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 391 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 392 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 393 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 394 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 395 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 396 397 #define QUEUE_LOW 1 398 #define QUEUE_NORMAL 2 399 #define QUEUE_HIGH 3 400 401 /* */ 402 /* */ 403 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 404 /* */ 405 /* */ 406 /* 2 RQPN */ 407 #define _HPQ(x) ((x) & 0xFF) 408 #define _LPQ(x) (((x) & 0xFF) << 8) 409 #define _PUBQ(x) (((x) & 0xFF) << 16) 410 #define _NPQ(x) ((x) & 0xFF) /* NOTE: in RQPN_NPQ register */ 411 412 #define LD_RQPN BIT(31) 413 414 /* 2 AUTO_LLT */ 415 #define BIT_AUTO_INIT_LLT BIT(16) 416 417 /* */ 418 /* */ 419 /* 0x0280h ~ 0x028Bh RX DMA Configuration */ 420 /* */ 421 /* */ 422 423 /* 2 REG_RXDMA_CONTROL, 0x0286h */ 424 /* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ 425 /* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ 426 /* define RXPKT_RELEASE_POLL BIT(0) */ 427 /* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ 428 /* this bit. FW can start releasing packets after RXDMA entering idle mode. */ 429 /* define RXDMA_IDLE BIT(1) */ 430 /* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ 431 /* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ 432 /* define RW_RELEASE_EN BIT(2) */ 433 434 /* 2 REG_RXPKT_NUM, 0x0284 */ 435 #define RXPKT_RELEASE_POLL BIT(16) 436 #define RXDMA_IDLE BIT(17) 437 #define RW_RELEASE_EN BIT(18) 438 439 /* */ 440 /* */ 441 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 442 /* */ 443 /* */ 444 /* 2 FWHW_TXQ_CTRL */ 445 #define EN_AMPDU_RTY_NEW BIT(7) 446 447 448 /* 2 SPEC SIFS */ 449 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 450 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 451 452 /* 2 RL */ 453 #define RETRY_LIMIT_SHORT_SHIFT 8 454 #define RETRY_LIMIT_LONG_SHIFT 0 455 456 /* */ 457 /* */ 458 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 459 /* */ 460 /* */ 461 462 #define _LRL(x) ((x) & 0x3F) 463 #define _SRL(x) (((x) & 0x3F) << 8) 464 465 466 /* 2 BCN_CTRL */ 467 #define EN_TXBCN_RPT BIT(2) 468 #define EN_BCN_FUNCTION BIT(3) 469 470 #define DIS_ATIM BIT(0) 471 #define DIS_BCNQ_SUB BIT(1) 472 #define DIS_TSF_UDT BIT(4) 473 474 /* 2 ACMHWCTRL */ 475 #define AcmHw_HwEn BIT(0) 476 #define AcmHw_BeqEn BIT(1) 477 #define AcmHw_ViqEn BIT(2) 478 #define AcmHw_VoqEn BIT(3) 479 480 /* */ 481 /* */ 482 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 483 /* */ 484 /* */ 485 486 /* 2 TCR */ 487 #define TSFRST BIT(0) 488 489 /* 2 RCR */ 490 #define AB BIT(3) 491 492 /* 2 SECCFG */ 493 #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ 494 #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ 495 #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ 496 #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ 497 #define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ 498 #define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ 499 #define SCR_CHK_KEYID BIT(8) 500 501 /* */ 502 /* */ 503 /* SDIO Bus Specification */ 504 /* */ 505 /* */ 506 507 /* I/O bus domain address mapping */ 508 #define SDIO_LOCAL_BASE 0x10250000 509 510 /* SDIO host local register space mapping. */ 511 #define SDIO_LOCAL_MSK 0x0FFF 512 #define WLAN_IOREG_MSK 0x7FFF 513 #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ 514 #define WLAN_RX0FF_MSK 0x0003 515 516 #define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ 517 #define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ 518 #define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ 519 #define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ 520 #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ 521 #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ 522 523 /* SDIO Tx Free Page Index */ 524 #define HI_QUEUE_IDX 0 525 #define MID_QUEUE_IDX 1 526 #define LOW_QUEUE_IDX 2 527 #define PUBLIC_QUEUE_IDX 3 528 529 #define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ 530 531 #define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ 532 #define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ 533 #define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ 534 #define SDIO_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ 535 #define SDIO_REG_OQT_FREE_PG 0x001E /* OQT Free Page */ 536 #define SDIO_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ 537 #define SDIO_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ 538 #define SDIO_REG_HSUS_CTRL 0x0086 /* SDIO HCI Suspend Control */ 539 540 #define SDIO_HIMR_DISABLED 0 541 542 /* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ 543 #define SDIO_HIMR_RX_REQUEST_MSK BIT0 544 #define SDIO_HIMR_AVAL_MSK BIT1 545 546 /* SDIO Host Interrupt Service Routine */ 547 #define SDIO_HISR_RX_REQUEST BIT0 548 #define SDIO_HISR_AVAL BIT1 549 #define SDIO_HISR_TXERR BIT2 550 #define SDIO_HISR_RXERR BIT3 551 #define SDIO_HISR_TXFOVW BIT4 552 #define SDIO_HISR_RXFOVW BIT5 553 #define SDIO_HISR_TXBCNOK BIT6 554 #define SDIO_HISR_TXBCNERR BIT7 555 #define SDIO_HISR_C2HCMD BIT17 556 #define SDIO_HISR_CPWM1 BIT18 557 #define SDIO_HISR_CPWM2 BIT19 558 #define SDIO_HISR_HSISR_IND BIT20 559 #define SDIO_HISR_GTINT3_IND BIT21 560 #define SDIO_HISR_GTINT4_IND BIT22 561 #define SDIO_HISR_PSTIMEOUT BIT23 562 #define SDIO_HISR_OCPINT BIT24 563 564 #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ 565 SDIO_HISR_RXERR |\ 566 SDIO_HISR_TXFOVW |\ 567 SDIO_HISR_RXFOVW |\ 568 SDIO_HISR_TXBCNOK |\ 569 SDIO_HISR_TXBCNERR |\ 570 SDIO_HISR_C2HCMD |\ 571 SDIO_HISR_CPWM1 |\ 572 SDIO_HISR_CPWM2 |\ 573 SDIO_HISR_HSISR_IND |\ 574 SDIO_HISR_GTINT3_IND |\ 575 SDIO_HISR_GTINT4_IND |\ 576 SDIO_HISR_PSTIMEOUT |\ 577 SDIO_HISR_OCPINT) 578 579 /* SDIO Tx FIFO related */ 580 #define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ 581 582 /* */ 583 /* */ 584 /* 0xFE00h ~ 0xFE55h USB Configuration */ 585 /* */ 586 /* */ 587 588 /* 2REG_C2HEVT_CLEAR */ 589 #define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ 590 #define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ 591 592 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 593 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ 594 #define WL_FUNC_EN BIT2 /* WiFi function enable */ 595 #define BT_FUNC_EN BIT18 /* BT function enable */ 596 #define GPS_FUNC_EN BIT22 /* GPS function enable */ 597 598 #endif /* __HAL_COMMON_H__ */ 599