1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Device Tree binding constants for AST2700 clock controller. 4 * 5 * Copyright (c) 2024 Aspeed Technology Inc. 6 */ 7 8 #ifndef __DT_BINDINGS_CLOCK_AST2700_H 9 #define __DT_BINDINGS_CLOCK_AST2700_H 10 11 /* SOC0 clk */ 12 #define SCU0_CLKIN 0 13 #define SCU0_CLK_24M 1 14 #define SCU0_CLK_192M 2 15 #define SCU0_CLK_UART 3 16 #define SCU0_CLK_UART_DIV13 3 17 #define SCU0_CLK_PSP 4 18 #define SCU0_CLK_HPLL 5 19 #define SCU0_CLK_HPLL_DIV2 6 20 #define SCU0_CLK_HPLL_DIV4 7 21 #define SCU0_CLK_HPLL_DIV_AHB 8 22 #define SCU0_CLK_DPLL 9 23 #define SCU0_CLK_MPLL 10 24 #define SCU0_CLK_MPLL_DIV2 11 25 #define SCU0_CLK_MPLL_DIV4 12 26 #define SCU0_CLK_MPLL_DIV8 13 27 #define SCU0_CLK_MPLL_DIV_AHB 14 28 #define SCU0_CLK_D0 15 29 #define SCU0_CLK_D1 16 30 #define SCU0_CLK_CRT0 17 31 #define SCU0_CLK_CRT1 18 32 #define SCU0_CLK_MPHY 19 33 #define SCU0_CLK_AXI0 20 34 #define SCU0_CLK_AXI1 21 35 #define SCU0_CLK_AHB 22 36 #define SCU0_CLK_APB 23 37 #define SCU0_CLK_UART4 24 38 #define SCU0_CLK_EMMCMUX 25 39 #define SCU0_CLK_EMMC 26 40 #define SCU0_CLK_U2PHY_CLK12M 27 41 #define SCU0_CLK_U2PHY_REFCLK 28 42 43 /* SOC0 clk-gate */ 44 #define SCU0_CLK_GATE_MCLK 29 45 #define SCU0_CLK_GATE_ECLK 30 46 #define SCU0_CLK_GATE_2DCLK 31 47 #define SCU0_CLK_GATE_VCLK 32 48 #define SCU0_CLK_GATE_BCLK 33 49 #define SCU0_CLK_GATE_VGA0CLK 34 50 #define SCU0_CLK_GATE_REFCLK 35 51 #define SCU0_CLK_GATE_PORTBUSB2CLK 36 52 #define SCU0_CLK_GATE_UHCICLK 37 53 #define SCU0_CLK_GATE_VGA1CLK 38 54 #define SCU0_CLK_GATE_DDRPHYCLK 39 55 #define SCU0_CLK_GATE_E2M0CLK 40 56 #define SCU0_CLK_GATE_HACCLK 41 57 #define SCU0_CLK_GATE_PORTAUSB2CLK 42 58 #define SCU0_CLK_GATE_UART4CLK 43 59 #define SCU0_CLK_GATE_SLICLK 44 60 #define SCU0_CLK_GATE_DACCLK 45 61 #define SCU0_CLK_GATE_DP 46 62 #define SCU0_CLK_GATE_E2M1CLK 47 63 #define SCU0_CLK_GATE_CRT0CLK 48 64 #define SCU0_CLK_GATE_CRT1CLK 49 65 #define SCU0_CLK_GATE_ECDSACLK 50 66 #define SCU0_CLK_GATE_RSACLK 51 67 #define SCU0_CLK_GATE_RVAS0CLK 52 68 #define SCU0_CLK_GATE_UFSCLK 53 69 #define SCU0_CLK_GATE_EMMCCLK 54 70 #define SCU0_CLK_GATE_RVAS1CLK 55 71 #define SCU0_CLK_U2PHY_REFCLKSRC 56 72 #define SCU0_CLK_AHBMUX 57 73 #define SCU0_CLK_MPHYSRC 58 74 75 /* SOC1 clk */ 76 #define SCU1_CLKIN 0 77 #define SCU1_CLK_HPLL 1 78 #define SCU1_CLK_APLL 2 79 #define SCU1_CLK_APLL_DIV2 3 80 #define SCU1_CLK_APLL_DIV4 4 81 #define SCU1_CLK_DPLL 5 82 #define SCU1_CLK_UXCLK 6 83 #define SCU1_CLK_HUXCLK 7 84 #define SCU1_CLK_UARTX 8 85 #define SCU1_CLK_HUARTX 9 86 #define SCU1_CLK_AHB 10 87 #define SCU1_CLK_APB 11 88 #define SCU1_CLK_UART0 12 89 #define SCU1_CLK_UART1 13 90 #define SCU1_CLK_UART2 14 91 #define SCU1_CLK_UART3 15 92 #define SCU1_CLK_UART5 16 93 #define SCU1_CLK_UART6 17 94 #define SCU1_CLK_UART7 18 95 #define SCU1_CLK_UART8 19 96 #define SCU1_CLK_UART9 20 97 #define SCU1_CLK_UART10 21 98 #define SCU1_CLK_UART11 22 99 #define SCU1_CLK_UART12 23 100 #define SCU1_CLK_UART13 24 101 #define SCU1_CLK_UART14 25 102 #define SCU1_CLK_APLL_DIVN 26 103 #define SCU1_CLK_SDMUX 27 104 #define SCU1_CLK_SDCLK 28 105 #define SCU1_CLK_RMII 29 106 #define SCU1_CLK_RGMII 30 107 #define SCU1_CLK_MACHCLK 31 108 #define SCU1_CLK_MAC0RCLK 32 109 #define SCU1_CLK_MAC1RCLK 33 110 #define SCU1_CLK_CAN 34 111 112 /* SOC1 clk gate */ 113 #define SCU1_CLK_GATE_LCLK0 35 114 #define SCU1_CLK_GATE_LCLK1 36 115 #define SCU1_CLK_GATE_ESPI0CLK 37 116 #define SCU1_CLK_GATE_ESPI1CLK 38 117 #define SCU1_CLK_GATE_SDCLK 39 118 #define SCU1_CLK_GATE_IPEREFCLK 40 119 #define SCU1_CLK_GATE_REFCLK 41 120 #define SCU1_CLK_GATE_LPCHCLK 42 121 #define SCU1_CLK_GATE_MAC0CLK 43 122 #define SCU1_CLK_GATE_MAC1CLK 44 123 #define SCU1_CLK_GATE_MAC2CLK 45 124 #define SCU1_CLK_GATE_UART0CLK 46 125 #define SCU1_CLK_GATE_UART1CLK 47 126 #define SCU1_CLK_GATE_UART2CLK 48 127 #define SCU1_CLK_GATE_UART3CLK 49 128 #define SCU1_CLK_GATE_I2CCLK 50 129 #define SCU1_CLK_GATE_I3C0CLK 51 130 #define SCU1_CLK_GATE_I3C1CLK 52 131 #define SCU1_CLK_GATE_I3C2CLK 53 132 #define SCU1_CLK_GATE_I3C3CLK 54 133 #define SCU1_CLK_GATE_I3C4CLK 55 134 #define SCU1_CLK_GATE_I3C5CLK 56 135 #define SCU1_CLK_GATE_I3C6CLK 57 136 #define SCU1_CLK_GATE_I3C7CLK 58 137 #define SCU1_CLK_GATE_I3C8CLK 59 138 #define SCU1_CLK_GATE_I3C9CLK 60 139 #define SCU1_CLK_GATE_I3C10CLK 61 140 #define SCU1_CLK_GATE_I3C11CLK 62 141 #define SCU1_CLK_GATE_I3C12CLK 63 142 #define SCU1_CLK_GATE_I3C13CLK 64 143 #define SCU1_CLK_GATE_I3C14CLK 65 144 #define SCU1_CLK_GATE_I3C15CLK 66 145 #define SCU1_CLK_GATE_UART5CLK 67 146 #define SCU1_CLK_GATE_UART6CLK 68 147 #define SCU1_CLK_GATE_UART7CLK 69 148 #define SCU1_CLK_GATE_UART8CLK 70 149 #define SCU1_CLK_GATE_UART9CLK 71 150 #define SCU1_CLK_GATE_UART10CLK 72 151 #define SCU1_CLK_GATE_UART11CLK 73 152 #define SCU1_CLK_GATE_UART12CLK 74 153 #define SCU1_CLK_GATE_FSICLK 75 154 #define SCU1_CLK_GATE_LTPIPHYCLK 76 155 #define SCU1_CLK_GATE_LTPICLK 77 156 #define SCU1_CLK_GATE_VGALCLK 78 157 #define SCU1_CLK_GATE_UHCICLK 79 158 #define SCU1_CLK_GATE_CANCLK 80 159 #define SCU1_CLK_GATE_PCICLK 81 160 #define SCU1_CLK_GATE_SLICLK 82 161 #define SCU1_CLK_GATE_E2MCLK 83 162 #define SCU1_CLK_GATE_PORTCUSB2CLK 84 163 #define SCU1_CLK_GATE_PORTDUSB2CLK 85 164 #define SCU1_CLK_GATE_LTPI1TXCLK 86 165 #define SCU1_CLK_I3C 87 166 167 #endif 168