xref: /linux/include/linux/edac.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /*
2  * Generic EDAC defs
3  *
4  * Author: Dave Jiang <djiang@mvista.com>
5  *
6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  *
11  */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14 
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20 #include <linux/numa.h>
21 
22 #define EDAC_DEVICE_NAME_LEN	31
23 
24 struct device;
25 
26 #define EDAC_OPSTATE_INVAL	-1
27 #define EDAC_OPSTATE_POLL	0
28 #define EDAC_OPSTATE_NMI	1
29 #define EDAC_OPSTATE_INT	2
30 
31 extern int edac_op_state;
32 
33 const struct bus_type *edac_get_sysfs_subsys(void);
34 
opstate_init(void)35 static inline void opstate_init(void)
36 {
37 	switch (edac_op_state) {
38 	case EDAC_OPSTATE_POLL:
39 	case EDAC_OPSTATE_NMI:
40 		break;
41 	default:
42 		edac_op_state = EDAC_OPSTATE_POLL;
43 	}
44 	return;
45 }
46 
47 /* Max length of a DIMM label*/
48 #define EDAC_MC_LABEL_LEN	31
49 
50 /* Maximum size of the location string */
51 #define LOCATION_SIZE 256
52 
53 /* Defines the maximum number of labels that can be reported */
54 #define EDAC_MAX_LABELS		8
55 
56 /* String used to join two or more labels */
57 #define OTHER_LABEL " or "
58 
59 /**
60  * enum dev_type - describe the type of memory DRAM chips used at the stick
61  * @DEV_UNKNOWN:	Can't be determined, or MC doesn't support detect it
62  * @DEV_X1:		1 bit for data
63  * @DEV_X2:		2 bits for data
64  * @DEV_X4:		4 bits for data
65  * @DEV_X8:		8 bits for data
66  * @DEV_X16:		16 bits for data
67  * @DEV_X32:		32 bits for data
68  * @DEV_X64:		64 bits for data
69  *
70  * Typical values are x4 and x8.
71  */
72 enum dev_type {
73 	DEV_UNKNOWN = 0,
74 	DEV_X1,
75 	DEV_X2,
76 	DEV_X4,
77 	DEV_X8,
78 	DEV_X16,
79 	DEV_X32,		/* Do these parts exist? */
80 	DEV_X64			/* Do these parts exist? */
81 };
82 
83 #define DEV_FLAG_UNKNOWN	BIT(DEV_UNKNOWN)
84 #define DEV_FLAG_X1		BIT(DEV_X1)
85 #define DEV_FLAG_X2		BIT(DEV_X2)
86 #define DEV_FLAG_X4		BIT(DEV_X4)
87 #define DEV_FLAG_X8		BIT(DEV_X8)
88 #define DEV_FLAG_X16		BIT(DEV_X16)
89 #define DEV_FLAG_X32		BIT(DEV_X32)
90 #define DEV_FLAG_X64		BIT(DEV_X64)
91 
92 /**
93  * enum hw_event_mc_err_type - type of the detected error
94  *
95  * @HW_EVENT_ERR_CORRECTED:	Corrected Error - Indicates that an ECC
96  *				corrected error was detected
97  * @HW_EVENT_ERR_UNCORRECTED:	Uncorrected Error - Indicates an error that
98  *				can't be corrected by ECC, but it is not
99  *				fatal (maybe it is on an unused memory area,
100  *				or the memory controller could recover from
101  *				it for example, by re-trying the operation).
102  * @HW_EVENT_ERR_DEFERRED:	Deferred Error - Indicates an uncorrectable
103  *				error whose handling is not urgent. This could
104  *				be due to hardware data poisoning where the
105  *				system can continue operation until the poisoned
106  *				data is consumed. Preemptive measures may also
107  *				be taken, e.g. offlining pages, etc.
108  * @HW_EVENT_ERR_FATAL:		Fatal Error - Uncorrected error that could not
109  *				be recovered.
110  * @HW_EVENT_ERR_INFO:		Informational - The CPER spec defines a forth
111  *				type of error: informational logs.
112  */
113 enum hw_event_mc_err_type {
114 	HW_EVENT_ERR_CORRECTED,
115 	HW_EVENT_ERR_UNCORRECTED,
116 	HW_EVENT_ERR_DEFERRED,
117 	HW_EVENT_ERR_FATAL,
118 	HW_EVENT_ERR_INFO,
119 };
120 
mc_event_error_type(const unsigned int err_type)121 static inline char *mc_event_error_type(const unsigned int err_type)
122 {
123 	switch (err_type) {
124 	case HW_EVENT_ERR_CORRECTED:
125 		return "Corrected";
126 	case HW_EVENT_ERR_UNCORRECTED:
127 		return "Uncorrected";
128 	case HW_EVENT_ERR_DEFERRED:
129 		return "Deferred";
130 	case HW_EVENT_ERR_FATAL:
131 		return "Fatal";
132 	default:
133 	case HW_EVENT_ERR_INFO:
134 		return "Info";
135 	}
136 }
137 
138 /**
139  * enum mem_type - memory types. For a more detailed reference, please see
140  *			http://en.wikipedia.org/wiki/DRAM
141  *
142  * @MEM_EMPTY:		Empty csrow
143  * @MEM_RESERVED:	Reserved csrow type
144  * @MEM_UNKNOWN:	Unknown csrow type
145  * @MEM_FPM:		FPM - Fast Page Mode, used on systems up to 1995.
146  * @MEM_EDO:		EDO - Extended data out, used on systems up to 1998.
147  * @MEM_BEDO:		BEDO - Burst Extended data out, an EDO variant.
148  * @MEM_SDR:		SDR - Single data rate SDRAM
149  *			http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
150  *			They use 3 pins for chip select: Pins 0 and 2 are
151  *			for rank 0; pins 1 and 3 are for rank 1, if the memory
152  *			is dual-rank.
153  * @MEM_RDR:		Registered SDR SDRAM
154  * @MEM_DDR:		Double data rate SDRAM
155  *			http://en.wikipedia.org/wiki/DDR_SDRAM
156  * @MEM_RDDR:		Registered Double data rate SDRAM
157  *			This is a variant of the DDR memories.
158  *			A registered memory has a buffer inside it, hiding
159  *			part of the memory details to the memory controller.
160  * @MEM_RMBS:		Rambus DRAM, used on a few Pentium III/IV controllers.
161  * @MEM_DDR2:		DDR2 RAM, as described at JEDEC JESD79-2F.
162  *			Those memories are labeled as "PC2-" instead of "PC" to
163  *			differentiate from DDR.
164  * @MEM_FB_DDR2:	Fully-Buffered DDR2, as described at JEDEC Std No. 205
165  *			and JESD206.
166  *			Those memories are accessed per DIMM slot, and not by
167  *			a chip select signal.
168  * @MEM_RDDR2:		Registered DDR2 RAM
169  *			This is a variant of the DDR2 memories.
170  * @MEM_XDR:		Rambus XDR
171  *			It is an evolution of the original RAMBUS memories,
172  *			created to compete with DDR2. Weren't used on any
173  *			x86 arch, but cell_edac PPC memory controller uses it.
174  * @MEM_DDR3:		DDR3 RAM
175  * @MEM_RDDR3:		Registered DDR3 RAM
176  *			This is a variant of the DDR3 memories.
177  * @MEM_LRDDR3:		Load-Reduced DDR3 memory.
178  * @MEM_LPDDR3:		Low-Power DDR3 memory.
179  * @MEM_DDR4:		Unbuffered DDR4 RAM
180  * @MEM_RDDR4:		Registered DDR4 RAM
181  *			This is a variant of the DDR4 memories.
182  * @MEM_LRDDR4:		Load-Reduced DDR4 memory.
183  * @MEM_LPDDR4:		Low-Power DDR4 memory.
184  * @MEM_DDR5:		Unbuffered DDR5 RAM
185  * @MEM_RDDR5:		Registered DDR5 RAM
186  * @MEM_LRDDR5:		Load-Reduced DDR5 memory.
187  * @MEM_NVDIMM:		Non-volatile RAM
188  * @MEM_WIO2:		Wide I/O 2.
189  * @MEM_HBM2:		High bandwidth Memory Gen 2.
190  * @MEM_HBM3:		High bandwidth Memory Gen 3.
191  */
192 enum mem_type {
193 	MEM_EMPTY = 0,
194 	MEM_RESERVED,
195 	MEM_UNKNOWN,
196 	MEM_FPM,
197 	MEM_EDO,
198 	MEM_BEDO,
199 	MEM_SDR,
200 	MEM_RDR,
201 	MEM_DDR,
202 	MEM_RDDR,
203 	MEM_RMBS,
204 	MEM_DDR2,
205 	MEM_FB_DDR2,
206 	MEM_RDDR2,
207 	MEM_XDR,
208 	MEM_DDR3,
209 	MEM_RDDR3,
210 	MEM_LRDDR3,
211 	MEM_LPDDR3,
212 	MEM_DDR4,
213 	MEM_RDDR4,
214 	MEM_LRDDR4,
215 	MEM_LPDDR4,
216 	MEM_DDR5,
217 	MEM_RDDR5,
218 	MEM_LRDDR5,
219 	MEM_NVDIMM,
220 	MEM_WIO2,
221 	MEM_HBM2,
222 	MEM_HBM3,
223 };
224 
225 #define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
226 #define MEM_FLAG_RESERVED	BIT(MEM_RESERVED)
227 #define MEM_FLAG_UNKNOWN	BIT(MEM_UNKNOWN)
228 #define MEM_FLAG_FPM		BIT(MEM_FPM)
229 #define MEM_FLAG_EDO		BIT(MEM_EDO)
230 #define MEM_FLAG_BEDO		BIT(MEM_BEDO)
231 #define MEM_FLAG_SDR		BIT(MEM_SDR)
232 #define MEM_FLAG_RDR		BIT(MEM_RDR)
233 #define MEM_FLAG_DDR		BIT(MEM_DDR)
234 #define MEM_FLAG_RDDR		BIT(MEM_RDDR)
235 #define MEM_FLAG_RMBS		BIT(MEM_RMBS)
236 #define MEM_FLAG_DDR2		BIT(MEM_DDR2)
237 #define MEM_FLAG_FB_DDR2	BIT(MEM_FB_DDR2)
238 #define MEM_FLAG_RDDR2		BIT(MEM_RDDR2)
239 #define MEM_FLAG_XDR		BIT(MEM_XDR)
240 #define MEM_FLAG_DDR3		BIT(MEM_DDR3)
241 #define MEM_FLAG_RDDR3		BIT(MEM_RDDR3)
242 #define MEM_FLAG_LPDDR3		BIT(MEM_LPDDR3)
243 #define MEM_FLAG_DDR4		BIT(MEM_DDR4)
244 #define MEM_FLAG_RDDR4		BIT(MEM_RDDR4)
245 #define MEM_FLAG_LRDDR4		BIT(MEM_LRDDR4)
246 #define MEM_FLAG_LPDDR4		BIT(MEM_LPDDR4)
247 #define MEM_FLAG_DDR5		BIT(MEM_DDR5)
248 #define MEM_FLAG_RDDR5		BIT(MEM_RDDR5)
249 #define MEM_FLAG_LRDDR5		BIT(MEM_LRDDR5)
250 #define MEM_FLAG_NVDIMM		BIT(MEM_NVDIMM)
251 #define MEM_FLAG_WIO2		BIT(MEM_WIO2)
252 #define MEM_FLAG_HBM2		BIT(MEM_HBM2)
253 #define MEM_FLAG_HBM3		BIT(MEM_HBM3)
254 
255 /**
256  * enum edac_type - Error Detection and Correction capabilities and mode
257  * @EDAC_UNKNOWN:	Unknown if ECC is available
258  * @EDAC_NONE:		Doesn't support ECC
259  * @EDAC_RESERVED:	Reserved ECC type
260  * @EDAC_PARITY:	Detects parity errors
261  * @EDAC_EC:		Error Checking - no correction
262  * @EDAC_SECDED:	Single bit error correction, Double detection
263  * @EDAC_S2ECD2ED:	Chipkill x2 devices - do these exist?
264  * @EDAC_S4ECD4ED:	Chipkill x4 devices
265  * @EDAC_S8ECD8ED:	Chipkill x8 devices
266  * @EDAC_S16ECD16ED:	Chipkill x16 devices
267  */
268 enum edac_type {
269 	EDAC_UNKNOWN =	0,
270 	EDAC_NONE,
271 	EDAC_RESERVED,
272 	EDAC_PARITY,
273 	EDAC_EC,
274 	EDAC_SECDED,
275 	EDAC_S2ECD2ED,
276 	EDAC_S4ECD4ED,
277 	EDAC_S8ECD8ED,
278 	EDAC_S16ECD16ED,
279 };
280 
281 #define EDAC_FLAG_UNKNOWN	BIT(EDAC_UNKNOWN)
282 #define EDAC_FLAG_NONE		BIT(EDAC_NONE)
283 #define EDAC_FLAG_PARITY	BIT(EDAC_PARITY)
284 #define EDAC_FLAG_EC		BIT(EDAC_EC)
285 #define EDAC_FLAG_SECDED	BIT(EDAC_SECDED)
286 #define EDAC_FLAG_S2ECD2ED	BIT(EDAC_S2ECD2ED)
287 #define EDAC_FLAG_S4ECD4ED	BIT(EDAC_S4ECD4ED)
288 #define EDAC_FLAG_S8ECD8ED	BIT(EDAC_S8ECD8ED)
289 #define EDAC_FLAG_S16ECD16ED	BIT(EDAC_S16ECD16ED)
290 
291 /**
292  * enum scrub_type - scrubbing capabilities
293  * @SCRUB_UNKNOWN:		Unknown if scrubber is available
294  * @SCRUB_NONE:			No scrubber
295  * @SCRUB_SW_PROG:		SW progressive (sequential) scrubbing
296  * @SCRUB_SW_SRC:		Software scrub only errors
297  * @SCRUB_SW_PROG_SRC:		Progressive software scrub from an error
298  * @SCRUB_SW_TUNABLE:		Software scrub frequency is tunable
299  * @SCRUB_HW_PROG:		HW progressive (sequential) scrubbing
300  * @SCRUB_HW_SRC:		Hardware scrub only errors
301  * @SCRUB_HW_PROG_SRC:		Progressive hardware scrub from an error
302  * @SCRUB_HW_TUNABLE:		Hardware scrub frequency is tunable
303  */
304 enum scrub_type {
305 	SCRUB_UNKNOWN =	0,
306 	SCRUB_NONE,
307 	SCRUB_SW_PROG,
308 	SCRUB_SW_SRC,
309 	SCRUB_SW_PROG_SRC,
310 	SCRUB_SW_TUNABLE,
311 	SCRUB_HW_PROG,
312 	SCRUB_HW_SRC,
313 	SCRUB_HW_PROG_SRC,
314 	SCRUB_HW_TUNABLE
315 };
316 
317 #define SCRUB_FLAG_SW_PROG	BIT(SCRUB_SW_PROG)
318 #define SCRUB_FLAG_SW_SRC	BIT(SCRUB_SW_SRC)
319 #define SCRUB_FLAG_SW_PROG_SRC	BIT(SCRUB_SW_PROG_SRC)
320 #define SCRUB_FLAG_SW_TUN	BIT(SCRUB_SW_SCRUB_TUNABLE)
321 #define SCRUB_FLAG_HW_PROG	BIT(SCRUB_HW_PROG)
322 #define SCRUB_FLAG_HW_SRC	BIT(SCRUB_HW_SRC)
323 #define SCRUB_FLAG_HW_PROG_SRC	BIT(SCRUB_HW_PROG_SRC)
324 #define SCRUB_FLAG_HW_TUN	BIT(SCRUB_HW_TUNABLE)
325 
326 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
327 
328 /* EDAC internal operation states */
329 #define	OP_ALLOC		0x100
330 #define OP_RUNNING_POLL		0x201
331 #define OP_RUNNING_INTERRUPT	0x202
332 #define OP_RUNNING_POLL_INTR	0x203
333 #define OP_OFFLINE		0x300
334 
335 /**
336  * enum edac_mc_layer_type - memory controller hierarchy layer
337  *
338  * @EDAC_MC_LAYER_BRANCH:	memory layer is named "branch"
339  * @EDAC_MC_LAYER_CHANNEL:	memory layer is named "channel"
340  * @EDAC_MC_LAYER_SLOT:		memory layer is named "slot"
341  * @EDAC_MC_LAYER_CHIP_SELECT:	memory layer is named "chip select"
342  * @EDAC_MC_LAYER_ALL_MEM:	memory layout is unknown. All memory is mapped
343  *				as a single memory area. This is used when
344  *				retrieving errors from a firmware driven driver.
345  *
346  * This enum is used by the drivers to tell edac_mc_sysfs what name should
347  * be used when describing a memory stick location.
348  */
349 enum edac_mc_layer_type {
350 	EDAC_MC_LAYER_BRANCH,
351 	EDAC_MC_LAYER_CHANNEL,
352 	EDAC_MC_LAYER_SLOT,
353 	EDAC_MC_LAYER_CHIP_SELECT,
354 	EDAC_MC_LAYER_ALL_MEM,
355 };
356 
357 /**
358  * struct edac_mc_layer - describes the memory controller hierarchy
359  * @type:		layer type
360  * @size:		number of components per layer. For example,
361  *			if the channel layer has two channels, size = 2
362  * @is_virt_csrow:	This layer is part of the "csrow" when old API
363  *			compatibility mode is enabled. Otherwise, it is
364  *			a channel
365  */
366 struct edac_mc_layer {
367 	enum edac_mc_layer_type	type;
368 	unsigned		size;
369 	bool			is_virt_csrow;
370 };
371 
372 /*
373  * Maximum number of layers used by the memory controller to uniquely
374  * identify a single memory stick.
375  * NOTE: Changing this constant requires not only to change the constant
376  * below, but also to change the existing code at the core, as there are
377  * some code there that are optimized for 3 layers.
378  */
379 #define EDAC_MAX_LAYERS		3
380 
381 struct dimm_info {
382 	struct device dev;
383 
384 	char label[EDAC_MC_LABEL_LEN + 1];	/* DIMM label on motherboard */
385 
386 	/* Memory location data */
387 	unsigned int location[EDAC_MAX_LAYERS];
388 
389 	struct mem_ctl_info *mci;	/* the parent */
390 	unsigned int idx;		/* index within the parent dimm array */
391 
392 	u32 grain;		/* granularity of reported error in bytes */
393 	enum dev_type dtype;	/* memory device type */
394 	enum mem_type mtype;	/* memory dimm type */
395 	enum edac_type edac_mode;	/* EDAC mode for this dimm */
396 
397 	u32 nr_pages;			/* number of pages on this dimm */
398 
399 	unsigned int csrow, cschannel;	/* Points to the old API data */
400 
401 	u16 smbios_handle;              /* Handle for SMBIOS type 17 */
402 
403 	u32 ce_count;
404 	u32 ue_count;
405 };
406 
407 /**
408  * struct rank_info - contains the information for one DIMM rank
409  *
410  * @chan_idx:	channel number where the rank is (typically, 0 or 1)
411  * @ce_count:	number of correctable errors for this rank
412  * @csrow:	A pointer to the chip select row structure (the parent
413  *		structure). The location of the rank is given by
414  *		the (csrow->csrow_idx, chan_idx) vector.
415  * @dimm:	A pointer to the DIMM structure, where the DIMM label
416  *		information is stored.
417  *
418  * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
419  *	  This is a bad assumption, but it makes this patch easier. Later
420  *	  patches in this series will fix this issue.
421  */
422 struct rank_info {
423 	int chan_idx;
424 	struct csrow_info *csrow;
425 	struct dimm_info *dimm;
426 
427 	u32 ce_count;		/* Correctable Errors for this csrow */
428 };
429 
430 struct csrow_info {
431 	struct device dev;
432 
433 	/* Used only by edac_mc_find_csrow_by_page() */
434 	unsigned long first_page;	/* first page number in csrow */
435 	unsigned long last_page;	/* last page number in csrow */
436 	unsigned long page_mask;	/* used for interleaving -
437 					 * 0UL for non intlv */
438 
439 	int csrow_idx;			/* the chip-select row */
440 
441 	u32 ue_count;		/* Uncorrectable Errors for this csrow */
442 	u32 ce_count;		/* Correctable Errors for this csrow */
443 
444 	struct mem_ctl_info *mci;	/* the parent */
445 
446 	/* channel information for this csrow */
447 	u32 nr_channels;
448 	struct rank_info **channels;
449 };
450 
451 /*
452  * struct errcount_attribute - used to store the several error counts
453  */
454 struct errcount_attribute_data {
455 	int n_layers;
456 	int pos[EDAC_MAX_LAYERS];
457 	int layer0, layer1, layer2;
458 };
459 
460 /**
461  * struct edac_raw_error_desc - Raw error report structure
462  * @grain:			minimum granularity for an error report, in bytes
463  * @error_count:		number of errors of the same type
464  * @type:			severity of the error (CE/UE/Fatal)
465  * @top_layer:			top layer of the error (layer[0])
466  * @mid_layer:			middle layer of the error (layer[1])
467  * @low_layer:			low layer of the error (layer[2])
468  * @page_frame_number:		page where the error happened
469  * @offset_in_page:		page offset
470  * @syndrome:			syndrome of the error (or 0 if unknown or if
471  * 				the syndrome is not applicable)
472  * @msg:			error message
473  * @location:			location of the error
474  * @label:			label of the affected DIMM(s)
475  * @other_detail:		other driver-specific detail about the error
476  */
477 struct edac_raw_error_desc {
478 	char location[LOCATION_SIZE];
479 	char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
480 	long grain;
481 
482 	u16 error_count;
483 	enum hw_event_mc_err_type type;
484 	int top_layer;
485 	int mid_layer;
486 	int low_layer;
487 	unsigned long page_frame_number;
488 	unsigned long offset_in_page;
489 	unsigned long syndrome;
490 	const char *msg;
491 	const char *other_detail;
492 };
493 
494 /* MEMORY controller information structure
495  */
496 struct mem_ctl_info {
497 	struct device			dev;
498 	const struct bus_type		*bus;
499 
500 	struct list_head link;	/* for global list of mem_ctl_info structs */
501 
502 	struct module *owner;	/* Module owner of this control struct */
503 
504 	unsigned long mtype_cap;	/* memory types supported by mc */
505 	unsigned long edac_ctl_cap;	/* Mem controller EDAC capabilities */
506 	unsigned long edac_cap;	/* configuration capabilities - this is
507 				 * closely related to edac_ctl_cap.  The
508 				 * difference is that the controller may be
509 				 * capable of s4ecd4ed which would be listed
510 				 * in edac_ctl_cap, but if channels aren't
511 				 * capable of s4ecd4ed then the edac_cap would
512 				 * not have that capability.
513 				 */
514 	unsigned long scrub_cap;	/* chipset scrub capabilities */
515 	enum scrub_type scrub_mode;	/* current scrub mode */
516 
517 	/* Translates sdram memory scrub rate given in bytes/sec to the
518 	   internal representation and configures whatever else needs
519 	   to be configured.
520 	 */
521 	int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
522 
523 	/* Get the current sdram memory scrub rate from the internal
524 	   representation and converts it to the closest matching
525 	   bandwidth in bytes/sec.
526 	 */
527 	int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
528 
529 
530 	/* pointer to edac checking routine */
531 	void (*edac_check) (struct mem_ctl_info * mci);
532 
533 	/*
534 	 * Remaps memory pages: controller pages to physical pages.
535 	 * For most MC's, this will be NULL.
536 	 */
537 	/* FIXME - why not send the phys page to begin with? */
538 	unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
539 					   unsigned long page);
540 	int mc_idx;
541 	struct csrow_info **csrows;
542 	unsigned int nr_csrows, num_cschannel;
543 
544 	/*
545 	 * Memory Controller hierarchy
546 	 *
547 	 * There are basically two types of memory controller: the ones that
548 	 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
549 	 * All old memory controllers enumerate memories per rank, but most
550 	 * of the recent drivers enumerate memories per DIMM, instead.
551 	 * When the memory controller is per rank, csbased is true.
552 	 */
553 	unsigned int n_layers;
554 	struct edac_mc_layer *layers;
555 	bool csbased;
556 
557 	/*
558 	 * DIMM info. Will eventually remove the entire csrows_info some day
559 	 */
560 	unsigned int tot_dimms;
561 	struct dimm_info **dimms;
562 
563 	/*
564 	 * FIXME - what about controllers on other busses? - IDs must be
565 	 * unique.  dev pointer should be sufficiently unique, but
566 	 * BUS:SLOT.FUNC numbers may not be unique.
567 	 */
568 	struct device *pdev;
569 	const char *mod_name;
570 	const char *ctl_name;
571 	const char *dev_name;
572 	void *pvt_info;
573 	unsigned long start_time;	/* mci load start time (in jiffies) */
574 
575 	/*
576 	 * drivers shouldn't access those fields directly, as the core
577 	 * already handles that.
578 	 */
579 	u32 ce_noinfo_count, ue_noinfo_count;
580 	u32 ue_mc, ce_mc;
581 
582 	struct completion complete;
583 
584 	/* Additional top controller level attributes, but specified
585 	 * by the low level driver.
586 	 *
587 	 * Set by the low level driver to provide attributes at the
588 	 * controller level.
589 	 * An array of structures, NULL terminated
590 	 *
591 	 * If attributes are desired, then set to array of attributes
592 	 * If no attributes are desired, leave NULL
593 	 */
594 	const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
595 
596 	/* work struct for this MC */
597 	struct delayed_work work;
598 
599 	/*
600 	 * Used to report an error - by being at the global struct
601 	 * makes the memory allocated by the EDAC core
602 	 */
603 	struct edac_raw_error_desc error_desc;
604 
605 	/* the internal state of this controller instance */
606 	int op_state;
607 
608 	struct dentry *debugfs;
609 	u8 fake_inject_layer[EDAC_MAX_LAYERS];
610 	bool fake_inject_ue;
611 	u16 fake_inject_count;
612 };
613 
614 #define mci_for_each_dimm(mci, dimm)				\
615 	for ((dimm) = (mci)->dimms[0];				\
616 	     (dimm);						\
617 	     (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms	\
618 		     ? (mci)->dimms[(dimm)->idx + 1]		\
619 		     : NULL)
620 
621 /**
622  * edac_get_dimm - Get DIMM info from a memory controller given by
623  *                 [layer0,layer1,layer2] position
624  *
625  * @mci:	MC descriptor struct mem_ctl_info
626  * @layer0:	layer0 position
627  * @layer1:	layer1 position. Unused if n_layers < 2
628  * @layer2:	layer2 position. Unused if n_layers < 3
629  *
630  * For 1 layer, this function returns "dimms[layer0]";
631  *
632  * For 2 layers, this function is similar to allocating a two-dimensional
633  * array and returning "dimms[layer0][layer1]";
634  *
635  * For 3 layers, this function is similar to allocating a tri-dimensional
636  * array and returning "dimms[layer0][layer1][layer2]";
637  */
edac_get_dimm(struct mem_ctl_info * mci,int layer0,int layer1,int layer2)638 static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
639 	int layer0, int layer1, int layer2)
640 {
641 	int index;
642 
643 	if (layer0 < 0
644 	    || (mci->n_layers > 1 && layer1 < 0)
645 	    || (mci->n_layers > 2 && layer2 < 0))
646 		return NULL;
647 
648 	index = layer0;
649 
650 	if (mci->n_layers > 1)
651 		index = index * mci->layers[1].size + layer1;
652 
653 	if (mci->n_layers > 2)
654 		index = index * mci->layers[2].size + layer2;
655 
656 	if (index < 0 || index >= mci->tot_dimms)
657 		return NULL;
658 
659 	if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
660 		return NULL;
661 
662 	return mci->dimms[index];
663 }
664 #endif /* _LINUX_EDAC_H_ */
665