1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SC16IS7xx tty serial driver - common code
4 *
5 * Copyright (C) 2014 GridPoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
8 */
9
10 #undef DEFAULT_SYMBOL_NAMESPACE
11 #define DEFAULT_SYMBOL_NAMESPACE "SERIAL_NXP_SC16IS7XX"
12
13 #include <linux/bits.h>
14 #include <linux/cleanup.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/export.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/idr.h>
22 #include <linux/kthread.h>
23 #include <linux/mod_devicetable.h>
24 #include <linux/module.h>
25 #include <linux/property.h>
26 #include <linux/regmap.h>
27 #include <linux/sched.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/string.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/uaccess.h>
34 #include <linux/units.h>
35
36 #include "sc16is7xx.h"
37
38 #define SC16IS7XX_MAX_DEVS 8
39
40 /* SC16IS7XX register definitions */
41 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
42 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
43 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
44 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
45 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
46 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
47 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
48 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
49 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
50 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
51 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
52 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
53 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */
54 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */
55 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */
56 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */
57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
58
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
62
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
66
67 /* Enhanced Register set: Only if (LCR == 0xBF) */
68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
73
74 /* IER register bits */
75 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */
77 #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */
78 #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */
79
80 /* IER register bits - write only if (EFR[4] == 1) */
81 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
82 #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */
83 #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */
84 #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */
85
86 /* FCR register bits */
87 #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */
88 #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */
89 #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */
90 #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */
91 #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */
92
93 /* FCR register bits - write only if (EFR[4] == 1) */
94 #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */
95 #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */
96
97 /* IIR register bits */
98 #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */
99 #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */
100 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
101 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
102 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
103 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
104 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
105 * - only on 75x/76x
106 */
107 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
108 * - only on 75x/76x
109 */
110 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
111 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active
112 * (LOW) to inactive (HIGH)
113 */
114 /* LCR register bits */
115 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
116 #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1
117 *
118 * Word length bits table:
119 * 00 -> 5 bit words
120 * 01 -> 6 bit words
121 * 10 -> 7 bit words
122 * 11 -> 8 bit words
123 */
124 #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit
125 *
126 * STOP length bit table:
127 * 0 -> 1 stop bit
128 * 1 -> 1-1.5 stop bits if word length is 5,
129 * 2 stop bits otherwise
130 */
131 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
132 #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */
133 #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */
134 #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */
135 #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */
136 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
137 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
138 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
139 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
140 #define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */
141 #define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */
142
143 /* MCR register bits */
144 #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */
145 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
146 #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */
147 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
148 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
149 * - write enabled if (EFR[4] == 1)
150 */
151 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
152 * - write enabled if (EFR[4] == 1)
153 */
154 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
155 * - write enabled if (EFR[4] == 1)
156 */
157
158 /* LSR register bits */
159 #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */
160 #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */
161 #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */
162 #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */
163 #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */
164 #define SC16IS7XX_LSR_BRK_ERROR_MASK \
165 (SC16IS7XX_LSR_OE_BIT | \
166 SC16IS7XX_LSR_PE_BIT | \
167 SC16IS7XX_LSR_FE_BIT | \
168 SC16IS7XX_LSR_BI_BIT)
169
170 #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */
171 #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */
172 #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */
173
174 /* MSR register bits */
175 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
176 #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4)
177 * - only on 75x/76x
178 */
179 #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7)
180 * - only on 75x/76x
181 */
182 #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6)
183 * - only on 75x/76x
184 */
185 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
186 #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */
187 #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */
188 #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */
189
190 /*
191 * TCR register bits
192 * TCR trigger levels are available from 0 to 60 characters with a granularity
193 * of four.
194 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
195 * no built-in hardware check to make sure this condition is met. Also, the TCR
196 * must be programmed with this condition before auto RTS or software flow
197 * control is enabled to avoid spurious operation of the device.
198 */
199 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
200 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
201
202 /*
203 * TLR register bits
204 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
205 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
206 * trigger levels. Trigger levels from 4 characters to 60 characters are
207 * available with a granularity of four.
208 *
209 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
210 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
211 * the trigger level defined in FCR is discarded. This applies to both transmit
212 * FIFO and receive FIFO trigger level setting.
213 *
214 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
215 * default state, that is, '00'.
216 */
217 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
219
220 /* IOControl register bits (Only 75x/76x) */
221 #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */
222 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */
223 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */
224 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
225
226 /* EFCR register bits */
227 #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */
228 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
229 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
230 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
231 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
232 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
233 * 0 = rate up to 115.2 kbit/s - Only 75x/76x
234 * 1 = rate up to 1.152 Mbit/s - Only 76x
235 */
236
237 /* EFR register bits */
238 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
239 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
240 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
241 #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to
242 * IER[7:4], FCR[5:4], MCR[7:5]
243 */
244 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
245 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
246 /*
247 * SWFLOW bits 3 & 2 table:
248 * 00 -> no transmitter flow control
249 * 01 -> transmitter generates XON2 and XOFF2
250 * 10 -> transmitter generates XON1 and XOFF1
251 * 11 -> transmitter generates XON1, XON2,
252 * XOFF1 and XOFF2
253 */
254 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
255 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
256 /*
257 * SWFLOW bits 1 & 0 table:
258 * 00 -> no received flow control
259 * 01 -> receiver compares XON2 and XOFF2
260 * 10 -> receiver compares XON1 and XOFF1
261 * 11 -> receiver compares XON1, XON2,
262 * XOFF1 and XOFF2
263 */
264 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
265 SC16IS7XX_EFR_AUTOCTS_BIT | \
266 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
267 SC16IS7XX_EFR_SWFLOW3_BIT | \
268 SC16IS7XX_EFR_SWFLOW2_BIT | \
269 SC16IS7XX_EFR_SWFLOW1_BIT | \
270 SC16IS7XX_EFR_SWFLOW0_BIT)
271
272
273 /* Misc definitions */
274 #define SC16IS7XX_FIFO_SIZE (64)
275 #define SC16IS7XX_GPIOS_PER_BANK 4
276
277 #define SC16IS7XX_POLL_PERIOD_MS 10
278 #define SC16IS7XX_RECONF_MD BIT(0)
279 #define SC16IS7XX_RECONF_IER BIT(1)
280 #define SC16IS7XX_RECONF_RS485 BIT(2)
281
282 struct sc16is7xx_one_config {
283 unsigned int flags;
284 u8 ier_mask;
285 u8 ier_val;
286 };
287
288 struct sc16is7xx_one {
289 struct uart_port port;
290 struct regmap *regmap;
291 struct mutex lock; /* For registers sharing same address space. */
292 struct kthread_work tx_work;
293 struct kthread_work reg_work;
294 struct kthread_delayed_work ms_work;
295 struct sc16is7xx_one_config config;
296 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */
297 unsigned int old_mctrl;
298 u8 old_lcr; /* Value before EFR access. */
299 bool irda_mode;
300 };
301
302 struct sc16is7xx_port {
303 const struct sc16is7xx_devtype *devtype;
304 struct clk *clk;
305 #ifdef CONFIG_GPIOLIB
306 struct gpio_chip gpio;
307 unsigned long gpio_valid_mask;
308 #endif
309 u8 mctrl_mask;
310 struct kthread_worker kworker;
311 struct task_struct *kworker_task;
312 struct kthread_delayed_work poll_work;
313 bool polling;
314 struct sc16is7xx_one p[];
315 };
316
317 static DEFINE_IDA(sc16is7xx_lines);
318
319 static struct uart_driver sc16is7xx_uart = {
320 .owner = THIS_MODULE,
321 .driver_name = KBUILD_MODNAME,
322 .dev_name = "ttySC",
323 .nr = SC16IS7XX_MAX_DEVS,
324 };
325
326 #define to_sc16is7xx_one(p) container_of((p), struct sc16is7xx_one, port)
327
sc16is7xx_port_read(struct uart_port * port,u8 reg)328 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
329 {
330 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
331 unsigned int val = 0;
332
333 regmap_read(one->regmap, reg, &val);
334
335 return val;
336 }
337
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)338 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
339 {
340 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
341
342 regmap_write(one->regmap, reg, val);
343 }
344
sc16is7xx_fifo_read(struct uart_port * port,u8 * rxbuf,unsigned int rxlen)345 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
346 {
347 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
348
349 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
350 }
351
sc16is7xx_fifo_write(struct uart_port * port,u8 * txbuf,u8 to_send)352 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
353 {
354 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
355
356 /*
357 * Don't send zero-length data, at least on SPI it confuses the chip
358 * delivering wrong TXLVL data.
359 */
360 if (unlikely(!to_send))
361 return;
362
363 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
364 }
365
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)366 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
367 u8 mask, u8 val)
368 {
369 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
370
371 regmap_update_bits(one->regmap, reg, mask, val);
372 }
373
sc16is7xx_power(struct uart_port * port,int on)374 static void sc16is7xx_power(struct uart_port *port, int on)
375 {
376 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
377 SC16IS7XX_IER_SLEEP_BIT,
378 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
379 }
380
381 /*
382 * In an amazing feat of design, the enhanced register set shares the
383 * addresses 0x02 and 0x04-0x07 with the general register set.
384 * The special register set also shares the addresses 0x00-0x01 with the
385 * general register set.
386 *
387 * Access to the enhanced or special register set is enabled by writing a magic
388 * value to the Line Control Register (LCR). When enhanced register set access
389 * is enabled, for example, any interrupt firing during this time will see the
390 * EFR where it expects the IIR to be, leading to
391 * "Unexpected interrupt" messages.
392 *
393 * Prevent this possibility by claiming a mutex when access to the enhanced
394 * or special register set is enabled, and claiming the same mutex from within
395 * the interrupt handler. This is similar to disabling the interrupt, but that
396 * doesn't work because the bulk of the interrupt processing is run as a
397 * workqueue job in thread context.
398 */
sc16is7xx_regs_lock(struct uart_port * port,u8 register_set)399 static void sc16is7xx_regs_lock(struct uart_port *port, u8 register_set)
400 {
401 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
402
403 mutex_lock(&one->lock);
404
405 /* Backup content of LCR. */
406 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
407
408 /* Enable access to the desired register set */
409 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, register_set);
410
411 /* Disable cache updates when writing to non-general registers */
412 regcache_cache_bypass(one->regmap, true);
413 }
414
sc16is7xx_regs_unlock(struct uart_port * port)415 static void sc16is7xx_regs_unlock(struct uart_port *port)
416 {
417 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
418
419 /* Re-enable cache updates when writing to general registers */
420 regcache_cache_bypass(one->regmap, false);
421
422 /* Restore original content of LCR */
423 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
424
425 mutex_unlock(&one->lock);
426 }
427
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)428 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
429 {
430 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
431 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
432
433 lockdep_assert_held_once(&port->lock);
434
435 one->config.flags |= SC16IS7XX_RECONF_IER;
436 one->config.ier_mask |= bit;
437 one->config.ier_val &= ~bit;
438 kthread_queue_work(&s->kworker, &one->reg_work);
439 }
440
sc16is7xx_ier_set(struct uart_port * port,u8 bit)441 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
442 {
443 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
444 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
445
446 lockdep_assert_held_once(&port->lock);
447
448 one->config.flags |= SC16IS7XX_RECONF_IER;
449 one->config.ier_mask |= bit;
450 one->config.ier_val |= bit;
451 kthread_queue_work(&s->kworker, &one->reg_work);
452 }
453
sc16is7xx_stop_tx(struct uart_port * port)454 static void sc16is7xx_stop_tx(struct uart_port *port)
455 {
456 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
457 }
458
sc16is7xx_stop_rx(struct uart_port * port)459 static void sc16is7xx_stop_rx(struct uart_port *port)
460 {
461 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
462 }
463
464 const struct sc16is7xx_devtype sc16is74x_devtype = {
465 .name = "SC16IS74X",
466 .nr_gpio = 0,
467 .nr_uart = 1,
468 };
469 EXPORT_SYMBOL_GPL(sc16is74x_devtype);
470
471 const struct sc16is7xx_devtype sc16is750_devtype = {
472 .name = "SC16IS750",
473 .nr_gpio = 8,
474 .nr_uart = 1,
475 };
476 EXPORT_SYMBOL_GPL(sc16is750_devtype);
477
478 const struct sc16is7xx_devtype sc16is752_devtype = {
479 .name = "SC16IS752",
480 .nr_gpio = 8,
481 .nr_uart = 2,
482 };
483 EXPORT_SYMBOL_GPL(sc16is752_devtype);
484
485 const struct sc16is7xx_devtype sc16is760_devtype = {
486 .name = "SC16IS760",
487 .nr_gpio = 8,
488 .nr_uart = 1,
489 };
490 EXPORT_SYMBOL_GPL(sc16is760_devtype);
491
492 const struct sc16is7xx_devtype sc16is762_devtype = {
493 .name = "SC16IS762",
494 .nr_gpio = 8,
495 .nr_uart = 2,
496 };
497 EXPORT_SYMBOL_GPL(sc16is762_devtype);
498
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)499 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
500 {
501 switch (reg) {
502 case SC16IS7XX_RHR_REG: /* Shared address space with THR & DLL */
503 case SC16IS7XX_IIR_REG: /* Shared address space with FCR & EFR */
504 case SC16IS7XX_LSR_REG: /* Shared address space with XON2 */
505 case SC16IS7XX_MSR_REG: /* Shared address space with TCR & XOFF1 */
506 case SC16IS7XX_SPR_REG: /* Shared address space with TLR & XOFF2 */
507 case SC16IS7XX_TXLVL_REG:
508 case SC16IS7XX_RXLVL_REG:
509 case SC16IS7XX_IOSTATE_REG:
510 case SC16IS7XX_IOCONTROL_REG:
511 return true;
512 default:
513 return false;
514 }
515 }
516
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)517 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
518 {
519 switch (reg) {
520 case SC16IS7XX_RHR_REG:
521 return true;
522 default:
523 return false;
524 }
525 }
526
sc16is7xx_regmap_noinc(struct device * dev,unsigned int reg)527 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
528 {
529 return reg == SC16IS7XX_RHR_REG;
530 }
531
532 /*
533 * Configure programmable baud rate generator (divisor) according to the
534 * desired baud rate.
535 *
536 * From the datasheet, the divisor is computed according to:
537 *
538 * XTAL1 input frequency
539 * -----------------------
540 * prescaler
541 * divisor = ---------------------------
542 * baud-rate x sampling-rate
543 */
sc16is7xx_set_baud(struct uart_port * port,int baud)544 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
545 {
546 unsigned int prescaler = 1;
547 unsigned long clk = port->uartclk, div = clk / 16 / baud;
548
549 if (div >= BIT(16)) {
550 prescaler = 4;
551 div /= prescaler;
552 }
553
554 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
555 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
556 SC16IS7XX_MCR_CLKSEL_BIT,
557 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
558
559 /* Access special register set (DLL/DLH) */
560 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_SPECIAL);
561
562 /* Write the new divisor */
563 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
564 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
565
566 /* Restore access to general register set */
567 sc16is7xx_regs_unlock(port);
568
569 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
570 }
571
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)572 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
573 unsigned int iir)
574 {
575 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
576 unsigned int lsr = 0, bytes_read, i;
577 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC);
578 u8 ch, flag;
579
580 if (unlikely(rxlen >= sizeof(one->buf))) {
581 dev_warn_ratelimited(port->dev,
582 "ttySC%i: Possible RX FIFO overrun: %d\n",
583 port->line, rxlen);
584 port->icount.buf_overrun++;
585 /* Ensure sanity of RX level */
586 rxlen = sizeof(one->buf);
587 }
588
589 while (rxlen) {
590 /* Only read lsr if there are possible errors in FIFO */
591 if (read_lsr) {
592 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
593 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
594 read_lsr = false; /* No errors left in FIFO */
595 } else
596 lsr = 0;
597
598 if (read_lsr) {
599 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
600 bytes_read = 1;
601 } else {
602 sc16is7xx_fifo_read(port, one->buf, rxlen);
603 bytes_read = rxlen;
604 }
605
606 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
607
608 port->icount.rx++;
609 flag = TTY_NORMAL;
610
611 if (unlikely(lsr)) {
612 if (lsr & SC16IS7XX_LSR_BI_BIT) {
613 port->icount.brk++;
614 if (uart_handle_break(port))
615 continue;
616 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
617 port->icount.parity++;
618 else if (lsr & SC16IS7XX_LSR_FE_BIT)
619 port->icount.frame++;
620 else if (lsr & SC16IS7XX_LSR_OE_BIT)
621 port->icount.overrun++;
622
623 lsr &= port->read_status_mask;
624 if (lsr & SC16IS7XX_LSR_BI_BIT)
625 flag = TTY_BREAK;
626 else if (lsr & SC16IS7XX_LSR_PE_BIT)
627 flag = TTY_PARITY;
628 else if (lsr & SC16IS7XX_LSR_FE_BIT)
629 flag = TTY_FRAME;
630 else if (lsr & SC16IS7XX_LSR_OE_BIT)
631 flag = TTY_OVERRUN;
632 }
633
634 for (i = 0; i < bytes_read; ++i) {
635 ch = one->buf[i];
636 if (uart_handle_sysrq_char(port, ch))
637 continue;
638
639 if (lsr & port->ignore_status_mask)
640 continue;
641
642 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
643 flag);
644 }
645 rxlen -= bytes_read;
646 }
647
648 tty_flip_buffer_push(&port->state->port);
649 }
650
sc16is7xx_handle_tx(struct uart_port * port)651 static void sc16is7xx_handle_tx(struct uart_port *port)
652 {
653 struct tty_port *tport = &port->state->port;
654 unsigned long flags;
655 unsigned int txlen;
656 unsigned char *tail;
657
658 if (unlikely(port->x_char)) {
659 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
660 port->icount.tx++;
661 port->x_char = 0;
662 return;
663 }
664
665 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
666 uart_port_lock_irqsave(port, &flags);
667 sc16is7xx_stop_tx(port);
668 uart_port_unlock_irqrestore(port, flags);
669 return;
670 }
671
672 /* Limit to space available in TX FIFO */
673 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
674 if (txlen > SC16IS7XX_FIFO_SIZE) {
675 dev_err_ratelimited(port->dev,
676 "chip reports %d free bytes in TX fifo, but it only has %d",
677 txlen, SC16IS7XX_FIFO_SIZE);
678 txlen = 0;
679 }
680
681 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);
682 sc16is7xx_fifo_write(port, tail, txlen);
683 uart_xmit_advance(port, txlen);
684
685 uart_port_lock_irqsave(port, &flags);
686 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
687 uart_write_wakeup(port);
688
689 if (kfifo_is_empty(&tport->xmit_fifo))
690 sc16is7xx_stop_tx(port);
691 else
692 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
693 uart_port_unlock_irqrestore(port, flags);
694 }
695
sc16is7xx_get_hwmctrl(struct uart_port * port)696 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
697 {
698 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
699 unsigned int mctrl = 0;
700
701 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
702 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
703 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
704 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
705 return mctrl;
706 }
707
sc16is7xx_update_mlines(struct sc16is7xx_one * one)708 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
709 {
710 struct uart_port *port = &one->port;
711 unsigned long flags;
712 unsigned int status, changed;
713
714 /* Lock required as MSR address is shared with TCR and XOFF1. */
715 lockdep_assert_held_once(&one->lock);
716
717 status = sc16is7xx_get_hwmctrl(port);
718 changed = status ^ one->old_mctrl;
719
720 if (changed == 0)
721 return;
722
723 one->old_mctrl = status;
724
725 uart_port_lock_irqsave(port, &flags);
726 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
727 port->icount.rng++;
728 if (changed & TIOCM_DSR)
729 port->icount.dsr++;
730 if (changed & TIOCM_CAR)
731 uart_handle_dcd_change(port, status & TIOCM_CAR);
732 if (changed & TIOCM_CTS)
733 uart_handle_cts_change(port, status & TIOCM_CTS);
734
735 wake_up_interruptible(&port->state->port.delta_msr_wait);
736 uart_port_unlock_irqrestore(port, flags);
737 }
738
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)739 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
740 {
741 unsigned int iir, rxlen;
742 struct uart_port *port = &s->p[portno].port;
743 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
744
745 guard(mutex)(&one->lock);
746
747 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
748 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
749 return false;
750
751 iir &= SC16IS7XX_IIR_ID_MASK;
752
753 switch (iir) {
754 case SC16IS7XX_IIR_RDI_SRC:
755 case SC16IS7XX_IIR_RLSE_SRC:
756 case SC16IS7XX_IIR_RTOI_SRC:
757 case SC16IS7XX_IIR_XOFFI_SRC:
758 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
759
760 /*
761 * There is a silicon bug that makes the chip report a
762 * time-out interrupt but no data in the FIFO. This is
763 * described in errata section 18.1.4.
764 *
765 * When this happens, read one byte from the FIFO to
766 * clear the interrupt.
767 */
768 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
769 rxlen = 1;
770
771 if (rxlen)
772 sc16is7xx_handle_rx(port, rxlen, iir);
773 break;
774 /* CTSRTS interrupt comes only when CTS goes inactive */
775 case SC16IS7XX_IIR_CTSRTS_SRC:
776 case SC16IS7XX_IIR_MSI_SRC:
777 sc16is7xx_update_mlines(one);
778 break;
779 case SC16IS7XX_IIR_THRI_SRC:
780 sc16is7xx_handle_tx(port);
781 break;
782 default:
783 dev_err_ratelimited(port->dev,
784 "ttySC%i: Unexpected interrupt: %x",
785 port->line, iir);
786 break;
787 }
788
789 return true;
790 }
791
sc16is7xx_irq(int irq,void * dev_id)792 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
793 {
794 struct sc16is7xx_port *s = dev_id;
795 bool keep_polling;
796
797 do {
798 int i;
799
800 keep_polling = false;
801
802 for (i = 0; i < s->devtype->nr_uart; ++i)
803 keep_polling |= sc16is7xx_port_irq(s, i);
804 } while (keep_polling);
805
806 return IRQ_HANDLED;
807 }
808
sc16is7xx_poll_proc(struct kthread_work * ws)809 static void sc16is7xx_poll_proc(struct kthread_work *ws)
810 {
811 struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work);
812
813 /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */
814 sc16is7xx_irq(0, s);
815
816 /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */
817 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
818 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
819 }
820
sc16is7xx_tx_proc(struct kthread_work * ws)821 static void sc16is7xx_tx_proc(struct kthread_work *ws)
822 {
823 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, tx_work);
824 struct uart_port *port = &one->port;
825
826 if ((port->rs485.flags & SER_RS485_ENABLED) &&
827 (port->rs485.delay_rts_before_send > 0))
828 msleep(port->rs485.delay_rts_before_send);
829
830 guard(mutex)(&one->lock);
831 sc16is7xx_handle_tx(port);
832 }
833
sc16is7xx_reconf_rs485(struct uart_port * port)834 static void sc16is7xx_reconf_rs485(struct uart_port *port)
835 {
836 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
837 SC16IS7XX_EFCR_RTS_INVERT_BIT;
838 u32 efcr = 0;
839 struct serial_rs485 *rs485 = &port->rs485;
840 unsigned long irqflags;
841
842 uart_port_lock_irqsave(port, &irqflags);
843 if (rs485->flags & SER_RS485_ENABLED) {
844 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
845
846 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
847 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
848 }
849 uart_port_unlock_irqrestore(port, irqflags);
850
851 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
852 }
853
sc16is7xx_reg_proc(struct kthread_work * ws)854 static void sc16is7xx_reg_proc(struct kthread_work *ws)
855 {
856 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, reg_work);
857 struct sc16is7xx_one_config config;
858 unsigned long irqflags;
859
860 uart_port_lock_irqsave(&one->port, &irqflags);
861 config = one->config;
862 memset(&one->config, 0, sizeof(one->config));
863 uart_port_unlock_irqrestore(&one->port, irqflags);
864
865 if (config.flags & SC16IS7XX_RECONF_MD) {
866 u8 mcr = 0;
867
868 /* Device ignores RTS setting when hardware flow is enabled */
869 if (one->port.mctrl & TIOCM_RTS)
870 mcr |= SC16IS7XX_MCR_RTS_BIT;
871
872 if (one->port.mctrl & TIOCM_DTR)
873 mcr |= SC16IS7XX_MCR_DTR_BIT;
874
875 if (one->port.mctrl & TIOCM_LOOP)
876 mcr |= SC16IS7XX_MCR_LOOP_BIT;
877 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
878 SC16IS7XX_MCR_RTS_BIT |
879 SC16IS7XX_MCR_DTR_BIT |
880 SC16IS7XX_MCR_LOOP_BIT,
881 mcr);
882 }
883
884 if (config.flags & SC16IS7XX_RECONF_IER)
885 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
886 config.ier_mask, config.ier_val);
887
888 if (config.flags & SC16IS7XX_RECONF_RS485)
889 sc16is7xx_reconf_rs485(&one->port);
890 }
891
sc16is7xx_ms_proc(struct kthread_work * ws)892 static void sc16is7xx_ms_proc(struct kthread_work *ws)
893 {
894 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, ms_work.work);
895 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
896
897 if (one->port.state) {
898 scoped_guard(mutex, &one->lock)
899 sc16is7xx_update_mlines(one);
900
901 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
902 }
903 }
904
sc16is7xx_enable_ms(struct uart_port * port)905 static void sc16is7xx_enable_ms(struct uart_port *port)
906 {
907 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
908 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
909
910 lockdep_assert_held_once(&port->lock);
911
912 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
913 }
914
sc16is7xx_start_tx(struct uart_port * port)915 static void sc16is7xx_start_tx(struct uart_port *port)
916 {
917 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
918 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
919
920 kthread_queue_work(&s->kworker, &one->tx_work);
921 }
922
sc16is7xx_throttle(struct uart_port * port)923 static void sc16is7xx_throttle(struct uart_port *port)
924 {
925 unsigned long flags;
926
927 /*
928 * Hardware flow control is enabled and thus the device ignores RTS
929 * value set in MCR register. Stop reading data from RX FIFO so the
930 * AutoRTS feature will de-activate RTS output.
931 */
932 uart_port_lock_irqsave(port, &flags);
933 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
934 uart_port_unlock_irqrestore(port, flags);
935 }
936
sc16is7xx_unthrottle(struct uart_port * port)937 static void sc16is7xx_unthrottle(struct uart_port *port)
938 {
939 unsigned long flags;
940
941 uart_port_lock_irqsave(port, &flags);
942 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
943 uart_port_unlock_irqrestore(port, flags);
944 }
945
sc16is7xx_tx_empty(struct uart_port * port)946 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
947 {
948 unsigned int lsr;
949
950 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
951
952 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
953 }
954
sc16is7xx_get_mctrl(struct uart_port * port)955 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
956 {
957 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
958
959 /* Called with port lock taken so we can only return cached value */
960 return one->old_mctrl;
961 }
962
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)963 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
964 {
965 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
966 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
967
968 one->config.flags |= SC16IS7XX_RECONF_MD;
969 kthread_queue_work(&s->kworker, &one->reg_work);
970 }
971
sc16is7xx_break_ctl(struct uart_port * port,int break_state)972 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
973 {
974 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
975 SC16IS7XX_LCR_TXBREAK_BIT,
976 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
977 }
978
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)979 static void sc16is7xx_set_termios(struct uart_port *port,
980 struct ktermios *termios,
981 const struct ktermios *old)
982 {
983 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
984 unsigned int lcr, flow = 0;
985 int baud;
986 unsigned long flags;
987
988 kthread_cancel_delayed_work_sync(&one->ms_work);
989
990 /* Mask termios capabilities we don't support */
991 termios->c_cflag &= ~CMSPAR;
992
993 /* Word size */
994 switch (termios->c_cflag & CSIZE) {
995 case CS5:
996 lcr = SC16IS7XX_LCR_WORD_LEN_5;
997 break;
998 case CS6:
999 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1000 break;
1001 case CS7:
1002 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1003 break;
1004 case CS8:
1005 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1006 break;
1007 default:
1008 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1009 termios->c_cflag &= ~CSIZE;
1010 termios->c_cflag |= CS8;
1011 break;
1012 }
1013
1014 /* Parity */
1015 if (termios->c_cflag & PARENB) {
1016 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1017 if (!(termios->c_cflag & PARODD))
1018 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1019 }
1020
1021 /* Stop bits */
1022 if (termios->c_cflag & CSTOPB)
1023 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1024
1025 /* Set read status mask */
1026 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1027 if (termios->c_iflag & INPCK)
1028 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1029 SC16IS7XX_LSR_FE_BIT;
1030 if (termios->c_iflag & (BRKINT | PARMRK))
1031 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1032
1033 /* Set status ignore mask */
1034 port->ignore_status_mask = 0;
1035 if (termios->c_iflag & IGNBRK)
1036 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1037 if (!(termios->c_cflag & CREAD))
1038 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1039
1040 /* Configure flow control */
1041 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1042 if (termios->c_cflag & CRTSCTS) {
1043 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1044 SC16IS7XX_EFR_AUTORTS_BIT;
1045 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1046 }
1047 if (termios->c_iflag & IXON)
1048 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1049 if (termios->c_iflag & IXOFF)
1050 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1051
1052 /* Update LCR register */
1053 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1054
1055 /* Update EFR registers */
1056 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED);
1057 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1058 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1059 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1060 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1061 sc16is7xx_regs_unlock(port);
1062
1063 /* Get baud rate generator configuration */
1064 baud = uart_get_baud_rate(port, termios, old,
1065 port->uartclk / 16 / 4 / 0xffff,
1066 port->uartclk / 16);
1067
1068 /* Setup baudrate generator */
1069 baud = sc16is7xx_set_baud(port, baud);
1070
1071 uart_port_lock_irqsave(port, &flags);
1072
1073 /* Update timeout according to new baud rate */
1074 uart_update_timeout(port, termios->c_cflag, baud);
1075
1076 if (UART_ENABLE_MS(port, termios->c_cflag))
1077 sc16is7xx_enable_ms(port);
1078
1079 uart_port_unlock_irqrestore(port, flags);
1080 }
1081
sc16is7xx_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1082 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1083 struct serial_rs485 *rs485)
1084 {
1085 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1086 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1087
1088 if (rs485->flags & SER_RS485_ENABLED) {
1089 /*
1090 * RTS signal is handled by HW, it's timing can't be influenced.
1091 * However, it's sometimes useful to delay TX even without RTS
1092 * control therefore we try to handle .delay_rts_before_send.
1093 */
1094 if (rs485->delay_rts_after_send)
1095 return -EINVAL;
1096 }
1097
1098 one->config.flags |= SC16IS7XX_RECONF_RS485;
1099 kthread_queue_work(&s->kworker, &one->reg_work);
1100
1101 return 0;
1102 }
1103
sc16is7xx_startup(struct uart_port * port)1104 static int sc16is7xx_startup(struct uart_port *port)
1105 {
1106 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1107 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1108 unsigned int val;
1109 unsigned long flags;
1110
1111 sc16is7xx_power(port, 1);
1112
1113 /* Reset FIFOs */
1114 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1115 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1116 udelay(5);
1117 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1118 SC16IS7XX_FCR_FIFO_BIT);
1119
1120 /* Enable TCR/TLR */
1121 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1122 SC16IS7XX_MCR_TCRTLR_BIT,
1123 SC16IS7XX_MCR_TCRTLR_BIT);
1124
1125 /* Configure flow control levels */
1126 /* Flow control halt level 48, resume level 24 */
1127 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1128 SC16IS7XX_TCR_RX_RESUME(24) |
1129 SC16IS7XX_TCR_RX_HALT(48));
1130
1131 /* Disable TCR/TLR access */
1132 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, 0);
1133
1134 /* Now, initialize the UART */
1135 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1136
1137 /* Enable IrDA mode if requested in DT */
1138 /* This bit must be written with LCR[7] = 0 */
1139 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1140 SC16IS7XX_MCR_IRDA_BIT,
1141 one->irda_mode ? SC16IS7XX_MCR_IRDA_BIT : 0);
1142
1143 /* Enable the Rx and Tx FIFO */
1144 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1145 SC16IS7XX_EFCR_RXDISABLE_BIT |
1146 SC16IS7XX_EFCR_TXDISABLE_BIT,
1147 0);
1148
1149 /* Enable RX, CTS change and modem lines interrupts */
1150 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1151 SC16IS7XX_IER_MSI_BIT;
1152 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1153
1154 /* Enable modem status polling */
1155 uart_port_lock_irqsave(port, &flags);
1156 sc16is7xx_enable_ms(port);
1157 uart_port_unlock_irqrestore(port, flags);
1158
1159 if (s->polling)
1160 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
1161 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
1162
1163 return 0;
1164 }
1165
sc16is7xx_shutdown(struct uart_port * port)1166 static void sc16is7xx_shutdown(struct uart_port *port)
1167 {
1168 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1169 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1170
1171 kthread_cancel_delayed_work_sync(&one->ms_work);
1172
1173 /* Disable all interrupts */
1174 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1175 /* Disable TX/RX */
1176 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1177 SC16IS7XX_EFCR_RXDISABLE_BIT |
1178 SC16IS7XX_EFCR_TXDISABLE_BIT,
1179 SC16IS7XX_EFCR_RXDISABLE_BIT |
1180 SC16IS7XX_EFCR_TXDISABLE_BIT);
1181
1182 sc16is7xx_power(port, 0);
1183
1184 if (s->polling)
1185 kthread_cancel_delayed_work_sync(&s->poll_work);
1186
1187 kthread_flush_worker(&s->kworker);
1188 }
1189
sc16is7xx_type(struct uart_port * port)1190 static const char *sc16is7xx_type(struct uart_port *port)
1191 {
1192 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1193
1194 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1195 }
1196
sc16is7xx_request_port(struct uart_port * port)1197 static int sc16is7xx_request_port(struct uart_port *port)
1198 {
1199 /* Do nothing */
1200 return 0;
1201 }
1202
sc16is7xx_config_port(struct uart_port * port,int flags)1203 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1204 {
1205 if (flags & UART_CONFIG_TYPE)
1206 port->type = PORT_SC16IS7XX;
1207 }
1208
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1209 static int sc16is7xx_verify_port(struct uart_port *port,
1210 struct serial_struct *s)
1211 {
1212 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1213 return -EINVAL;
1214 if (s->irq != port->irq)
1215 return -EINVAL;
1216
1217 return 0;
1218 }
1219
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1220 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1221 unsigned int oldstate)
1222 {
1223 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1224 }
1225
sc16is7xx_null_void(struct uart_port * port)1226 static void sc16is7xx_null_void(struct uart_port *port)
1227 {
1228 /* Do nothing */
1229 }
1230
1231 static const struct uart_ops sc16is7xx_ops = {
1232 .tx_empty = sc16is7xx_tx_empty,
1233 .set_mctrl = sc16is7xx_set_mctrl,
1234 .get_mctrl = sc16is7xx_get_mctrl,
1235 .stop_tx = sc16is7xx_stop_tx,
1236 .start_tx = sc16is7xx_start_tx,
1237 .throttle = sc16is7xx_throttle,
1238 .unthrottle = sc16is7xx_unthrottle,
1239 .stop_rx = sc16is7xx_stop_rx,
1240 .enable_ms = sc16is7xx_enable_ms,
1241 .break_ctl = sc16is7xx_break_ctl,
1242 .startup = sc16is7xx_startup,
1243 .shutdown = sc16is7xx_shutdown,
1244 .set_termios = sc16is7xx_set_termios,
1245 .type = sc16is7xx_type,
1246 .request_port = sc16is7xx_request_port,
1247 .release_port = sc16is7xx_null_void,
1248 .config_port = sc16is7xx_config_port,
1249 .verify_port = sc16is7xx_verify_port,
1250 .pm = sc16is7xx_pm,
1251 };
1252
1253 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1254 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1255 {
1256 unsigned int val;
1257 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1258 struct uart_port *port = &s->p[0].port;
1259
1260 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1261
1262 return !!(val & BIT(offset));
1263 }
1264
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1265 static int sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
1266 int val)
1267 {
1268 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1269 struct uart_port *port = &s->p[0].port;
1270
1271 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1272 val ? BIT(offset) : 0);
1273
1274 return 0;
1275 }
1276
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1277 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1278 unsigned offset)
1279 {
1280 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1281 struct uart_port *port = &s->p[0].port;
1282
1283 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1284
1285 return 0;
1286 }
1287
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1288 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1289 unsigned offset, int val)
1290 {
1291 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1292 struct uart_port *port = &s->p[0].port;
1293 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1294
1295 if (val)
1296 state |= BIT(offset);
1297 else
1298 state &= ~BIT(offset);
1299
1300 /*
1301 * If we write IOSTATE first, and then IODIR, the output value is not
1302 * transferred to the corresponding I/O pin.
1303 * The datasheet states that each register bit will be transferred to
1304 * the corresponding I/O pin programmed as output when writing to
1305 * IOSTATE. Therefore, configure direction first with IODIR, and then
1306 * set value after with IOSTATE.
1307 */
1308 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1309 BIT(offset));
1310 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1311
1312 return 0;
1313 }
1314
sc16is7xx_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1315 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1316 unsigned long *valid_mask,
1317 unsigned int ngpios)
1318 {
1319 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1320
1321 *valid_mask = s->gpio_valid_mask;
1322
1323 return 0;
1324 }
1325
sc16is7xx_setup_gpio_chip(struct sc16is7xx_port * s)1326 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1327 {
1328 struct device *dev = s->p[0].port.dev;
1329
1330 if (!s->devtype->nr_gpio)
1331 return 0;
1332
1333 switch (s->mctrl_mask) {
1334 case 0:
1335 s->gpio_valid_mask = GENMASK(7, 0);
1336 break;
1337 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1338 s->gpio_valid_mask = GENMASK(3, 0);
1339 break;
1340 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1341 s->gpio_valid_mask = GENMASK(7, 4);
1342 break;
1343 default:
1344 break;
1345 }
1346
1347 if (s->gpio_valid_mask == 0)
1348 return 0;
1349
1350 s->gpio.owner = THIS_MODULE;
1351 s->gpio.parent = dev;
1352 s->gpio.label = dev_name(dev);
1353 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1354 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1355 s->gpio.get = sc16is7xx_gpio_get;
1356 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1357 s->gpio.set = sc16is7xx_gpio_set;
1358 s->gpio.base = -1;
1359 s->gpio.ngpio = s->devtype->nr_gpio;
1360 s->gpio.can_sleep = 1;
1361
1362 return gpiochip_add_data(&s->gpio, s);
1363 }
1364 #endif
1365
sc16is7xx_setup_irda_ports(struct sc16is7xx_port * s)1366 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1367 {
1368 int i;
1369 int ret;
1370 int count;
1371 u32 irda_port[SC16IS7XX_MAX_PORTS];
1372 struct device *dev = s->p[0].port.dev;
1373
1374 count = device_property_count_u32(dev, "irda-mode-ports");
1375 if (count < 0 || count > ARRAY_SIZE(irda_port))
1376 return;
1377
1378 ret = device_property_read_u32_array(dev, "irda-mode-ports",
1379 irda_port, count);
1380 if (ret)
1381 return;
1382
1383 for (i = 0; i < count; i++) {
1384 if (irda_port[i] < s->devtype->nr_uart)
1385 s->p[irda_port[i]].irda_mode = true;
1386 }
1387 }
1388
1389 /*
1390 * Configure ports designated to operate as modem control lines.
1391 */
sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port * s,struct regmap * regmap)1392 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1393 struct regmap *regmap)
1394 {
1395 int i;
1396 int ret;
1397 int count;
1398 u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1399 struct device *dev = s->p[0].port.dev;
1400
1401 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1402 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1403 return 0;
1404
1405 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1406 mctrl_port, count);
1407 if (ret)
1408 return ret;
1409
1410 s->mctrl_mask = 0;
1411
1412 for (i = 0; i < count; i++) {
1413 /* Use GPIO lines as modem control lines */
1414 if (mctrl_port[i] == 0)
1415 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1416 else if (mctrl_port[i] == 1)
1417 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1418 }
1419
1420 if (s->mctrl_mask)
1421 regmap_update_bits(
1422 regmap,
1423 SC16IS7XX_IOCONTROL_REG,
1424 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1425 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1426
1427 return 0;
1428 }
1429
1430 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1431 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1432 .delay_rts_before_send = 1,
1433 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1434 };
1435
1436 /* Reset device, purging any pending irq / data */
sc16is7xx_reset(struct device * dev,struct regmap * regmap)1437 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap)
1438 {
1439 struct gpio_desc *reset_gpio;
1440
1441 /* Assert reset GPIO if defined and valid. */
1442 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1443 if (IS_ERR(reset_gpio))
1444 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n");
1445
1446 if (reset_gpio) {
1447 /* The minimum reset pulse width is 3 us. */
1448 fsleep(5);
1449 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */
1450 } else {
1451 /* Software reset */
1452 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG,
1453 SC16IS7XX_IOCONTROL_SRESET_BIT);
1454 }
1455
1456 return 0;
1457 }
1458
sc16is7xx_setup_channel(struct sc16is7xx_one * one,int i,bool * port_registered)1459 static int sc16is7xx_setup_channel(struct sc16is7xx_one *one, int i,
1460 bool *port_registered)
1461 {
1462 struct uart_port *port = &one->port;
1463 int ret;
1464
1465 ret = ida_alloc_max(&sc16is7xx_lines, SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);
1466 if (ret < 0)
1467 return ret;
1468
1469 port->line = ret;
1470
1471 /* Initialize port data */
1472 port->type = PORT_SC16IS7XX;
1473 port->fifosize = SC16IS7XX_FIFO_SIZE;
1474 port->flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1475 port->iobase = i;
1476 /*
1477 * Use all ones as membase to make sure uart_configure_port() in
1478 * serial_core.c does not abort for SPI/I2C devices where the
1479 * membase address is not applicable.
1480 */
1481 port->membase = (void __iomem *)~0;
1482 port->iotype = UPIO_PORT;
1483 port->rs485_config = sc16is7xx_config_rs485;
1484 port->rs485_supported = sc16is7xx_rs485_supported;
1485 port->ops = &sc16is7xx_ops;
1486 one->old_mctrl = 0;
1487
1488 mutex_init(&one->lock);
1489
1490 ret = uart_get_rs485_mode(port);
1491 if (ret)
1492 return ret;
1493
1494 /* Enable access to general register set */
1495 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 0x00);
1496
1497 /* Disable all interrupts */
1498 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1499 /* Disable TX/RX */
1500 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG,
1501 SC16IS7XX_EFCR_RXDISABLE_BIT |
1502 SC16IS7XX_EFCR_TXDISABLE_BIT);
1503
1504 /* Initialize kthread work structs */
1505 kthread_init_work(&one->tx_work, sc16is7xx_tx_proc);
1506 kthread_init_work(&one->reg_work, sc16is7xx_reg_proc);
1507 kthread_init_delayed_work(&one->ms_work, sc16is7xx_ms_proc);
1508
1509 /* Register port */
1510 ret = uart_add_one_port(&sc16is7xx_uart, port);
1511 if (ret)
1512 return ret;
1513
1514 *port_registered = true;
1515
1516 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED);
1517 /* Enable write access to enhanced features */
1518 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1519 SC16IS7XX_EFR_ENABLE_BIT);
1520 sc16is7xx_regs_unlock(port);
1521
1522 /* Go to suspend mode */
1523 sc16is7xx_power(port, 0);
1524
1525 return 0;
1526 }
1527
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmaps[],int irq)1528 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,
1529 struct regmap *regmaps[], int irq)
1530 {
1531 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1532 unsigned int val;
1533 u32 uartclk = 0;
1534 int i, ret;
1535 struct sc16is7xx_port *s;
1536 bool port_registered[SC16IS7XX_MAX_PORTS];
1537
1538 for (i = 0; i < devtype->nr_uart; i++)
1539 if (IS_ERR(regmaps[i]))
1540 return PTR_ERR(regmaps[i]);
1541
1542 /*
1543 * This device does not have an identification register that would
1544 * tell us if we are really connected to the correct device.
1545 * The best we can do is to check if communication is at all possible.
1546 *
1547 * Note: regmap[0] is used in the probe function to access registers
1548 * common to all channels/ports, as it is guaranteed to be present on
1549 * all variants.
1550 */
1551 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1552 if (ret < 0)
1553 return -EPROBE_DEFER;
1554
1555 /* Alloc port structure */
1556 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1557 if (!s)
1558 return -ENOMEM;
1559
1560 /* Always ask for fixed clock rate from a property. */
1561 device_property_read_u32(dev, "clock-frequency", &uartclk);
1562
1563 s->polling = (irq <= 0);
1564 if (s->polling)
1565 dev_dbg(dev,
1566 "No interrupt pin definition, falling back to polling mode\n");
1567
1568 s->clk = devm_clk_get_optional(dev, NULL);
1569 if (IS_ERR(s->clk))
1570 return PTR_ERR(s->clk);
1571
1572 ret = clk_prepare_enable(s->clk);
1573 if (ret)
1574 return ret;
1575
1576 freq = clk_get_rate(s->clk);
1577 if (freq == 0) {
1578 if (uartclk)
1579 freq = uartclk;
1580 if (pfreq)
1581 freq = *pfreq;
1582 if (freq)
1583 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1584 else
1585 return -EINVAL;
1586 }
1587
1588 s->devtype = devtype;
1589 dev_set_drvdata(dev, s);
1590
1591 kthread_init_worker(&s->kworker);
1592 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1593 "sc16is7xx");
1594 if (IS_ERR(s->kworker_task)) {
1595 ret = PTR_ERR(s->kworker_task);
1596 goto out_clk;
1597 }
1598 sched_set_fifo(s->kworker_task);
1599
1600 ret = sc16is7xx_reset(dev, regmaps[0]);
1601 if (ret)
1602 goto out_kthread;
1603
1604 /* Mark each port line and status as uninitialised. */
1605 for (i = 0; i < devtype->nr_uart; ++i) {
1606 s->p[i].port.line = SC16IS7XX_MAX_DEVS;
1607 port_registered[i] = false;
1608 }
1609
1610 for (i = 0; i < devtype->nr_uart; ++i) {
1611 s->p[i].port.dev = dev;
1612 s->p[i].port.irq = irq;
1613 s->p[i].port.uartclk = freq;
1614 s->p[i].regmap = regmaps[i];
1615
1616 ret = sc16is7xx_setup_channel(&s->p[i], i, &port_registered[i]);
1617 if (ret)
1618 goto out_ports;
1619 }
1620
1621 sc16is7xx_setup_irda_ports(s);
1622
1623 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1624 if (ret)
1625 goto out_ports;
1626
1627 #ifdef CONFIG_GPIOLIB
1628 ret = sc16is7xx_setup_gpio_chip(s);
1629 if (ret)
1630 goto out_ports;
1631 #endif
1632
1633 if (s->polling) {
1634 /* Initialize kernel thread for polling */
1635 kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc);
1636 return 0;
1637 }
1638
1639 /*
1640 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1641 * If that succeeds, we can allow sharing the interrupt as well.
1642 * In case the interrupt controller doesn't support that, we fall
1643 * back to a non-shared falling-edge trigger.
1644 */
1645 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1646 IRQF_TRIGGER_LOW | IRQF_SHARED |
1647 IRQF_ONESHOT,
1648 dev_name(dev), s);
1649 if (!ret)
1650 return 0;
1651
1652 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1653 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1654 dev_name(dev), s);
1655 if (!ret)
1656 return 0;
1657
1658 #ifdef CONFIG_GPIOLIB
1659 if (s->gpio_valid_mask)
1660 gpiochip_remove(&s->gpio);
1661 #endif
1662
1663 out_ports:
1664 for (i = 0; i < devtype->nr_uart; i++) {
1665 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)
1666 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1667 if (port_registered[i])
1668 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1669 }
1670
1671 out_kthread:
1672 kthread_stop(s->kworker_task);
1673
1674 out_clk:
1675 clk_disable_unprepare(s->clk);
1676
1677 return ret;
1678 }
1679 EXPORT_SYMBOL_GPL(sc16is7xx_probe);
1680
sc16is7xx_remove(struct device * dev)1681 void sc16is7xx_remove(struct device *dev)
1682 {
1683 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1684 int i;
1685
1686 #ifdef CONFIG_GPIOLIB
1687 if (s->gpio_valid_mask)
1688 gpiochip_remove(&s->gpio);
1689 #endif
1690
1691 for (i = 0; i < s->devtype->nr_uart; i++) {
1692 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1693 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1694 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1695 sc16is7xx_power(&s->p[i].port, 0);
1696 }
1697
1698 if (s->polling)
1699 kthread_cancel_delayed_work_sync(&s->poll_work);
1700
1701 kthread_flush_worker(&s->kworker);
1702 kthread_stop(s->kworker_task);
1703
1704 clk_disable_unprepare(s->clk);
1705 }
1706 EXPORT_SYMBOL_GPL(sc16is7xx_remove);
1707
1708 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1709 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1710 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1711 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1712 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1713 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1714 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1715 { }
1716 };
1717 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);
1718 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1719
1720 const struct regmap_config sc16is7xx_regcfg = {
1721 .reg_bits = 5,
1722 .pad_bits = 3,
1723 .val_bits = 8,
1724 .cache_type = REGCACHE_MAPLE,
1725 .volatile_reg = sc16is7xx_regmap_volatile,
1726 .precious_reg = sc16is7xx_regmap_precious,
1727 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1728 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1729 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1730 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1731 .max_register = SC16IS7XX_EFCR_REG,
1732 };
1733 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);
1734
sc16is7xx_regmap_name(u8 port_id)1735 const char *sc16is7xx_regmap_name(u8 port_id)
1736 {
1737 switch (port_id) {
1738 case 0: return "port0";
1739 case 1: return "port1";
1740 default:
1741 WARN_ON(true);
1742 return NULL;
1743 }
1744 }
1745 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);
1746
sc16is7xx_regmap_port_mask(unsigned int port_id)1747 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1748 {
1749 /* CH1,CH0 are at bits 2:1. */
1750 return port_id << 1;
1751 }
1752 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);
1753
sc16is7xx_init(void)1754 static int __init sc16is7xx_init(void)
1755 {
1756 return uart_register_driver(&sc16is7xx_uart);
1757 }
1758 module_init(sc16is7xx_init);
1759
sc16is7xx_exit(void)1760 static void __exit sc16is7xx_exit(void)
1761 {
1762 uart_unregister_driver(&sc16is7xx_uart);
1763 }
1764 module_exit(sc16is7xx_exit);
1765
1766 MODULE_LICENSE("GPL");
1767 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1768 MODULE_DESCRIPTION(KBUILD_MODNAME " tty serial core driver");
1769