1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SC16IS7xx tty serial driver - common code
4 *
5 * Copyright (C) 2014 GridPoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
8 */
9
10 #undef DEFAULT_SYMBOL_NAMESPACE
11 #define DEFAULT_SYMBOL_NAMESPACE "SERIAL_NXP_SC16IS7XX"
12
13 #include <linux/bits.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/export.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/idr.h>
21 #include <linux/kthread.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/property.h>
25 #include <linux/regmap.h>
26 #include <linux/sched.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/string.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/uaccess.h>
33 #include <linux/units.h>
34
35 #include "sc16is7xx.h"
36
37 #define SC16IS7XX_MAX_DEVS 8
38
39 /* SC16IS7XX register definitions */
40 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
41 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
42 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
43 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
44 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
45 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
46 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
47 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
48 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
49 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
50 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
52 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
53 * - only on 75x/76x
54 */
55 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
56 * - only on 75x/76x
57 */
58 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
59 * - only on 75x/76x
60 */
61 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
62 * - only on 75x/76x
63 */
64 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
65
66 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
67 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
68 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
69
70 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
71 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
72 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
73
74 /* Enhanced Register set: Only if (LCR == 0xBF) */
75 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
76 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
77 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
78 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
79 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
80
81 /* IER register bits */
82 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
83 #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register
84 * interrupt */
85 #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status
86 * interrupt */
87 #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status
88 * interrupt */
89
90 /* IER register bits - write only if (EFR[4] == 1) */
91 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
92 #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */
93 #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */
94 #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */
95
96 /* FCR register bits */
97 #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */
98 #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */
99 #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */
100 #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */
101 #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */
102
103 /* FCR register bits - write only if (EFR[4] == 1) */
104 #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */
105 #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */
106
107 /* IIR register bits */
108 #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */
109 #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */
110 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
111 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
112 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
114 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
115 * - only on 75x/76x
116 */
117 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
118 * - only on 75x/76x
119 */
120 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
121 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
122 * from active (LOW)
123 * to inactive (HIGH)
124 */
125 /* LCR register bits */
126 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
127 #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1
128 *
129 * Word length bits table:
130 * 00 -> 5 bit words
131 * 01 -> 6 bit words
132 * 10 -> 7 bit words
133 * 11 -> 8 bit words
134 */
135 #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit
136 *
137 * STOP length bit table:
138 * 0 -> 1 stop bit
139 * 1 -> 1-1.5 stop bits if
140 * word length is 5,
141 * 2 stop bits otherwise
142 */
143 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
144 #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */
145 #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */
146 #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */
147 #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */
148 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
149 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
150 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
151 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
152 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
153 * reg set */
154 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
155 * reg set */
156
157 /* MCR register bits */
158 #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement
159 * - only on 75x/76x
160 */
161 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
162 #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */
163 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
164 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
165 * - write enabled
166 * if (EFR[4] == 1)
167 */
168 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
169 * - write enabled
170 * if (EFR[4] == 1)
171 */
172 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
173 * - write enabled
174 * if (EFR[4] == 1)
175 */
176
177 /* LSR register bits */
178 #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */
179 #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */
180 #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */
181 #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */
182 #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */
183 #define SC16IS7XX_LSR_BRK_ERROR_MASK \
184 (SC16IS7XX_LSR_OE_BIT | \
185 SC16IS7XX_LSR_PE_BIT | \
186 SC16IS7XX_LSR_FE_BIT | \
187 SC16IS7XX_LSR_BI_BIT)
188
189 #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */
190 #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */
191 #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */
192
193 /* MSR register bits */
194 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
195 #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready
196 * or (IO4)
197 * - only on 75x/76x
198 */
199 #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator
200 * or (IO7)
201 * - only on 75x/76x
202 */
203 #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect
204 * or (IO6)
205 * - only on 75x/76x
206 */
207 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
208 #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4)
209 * - only on 75x/76x
210 */
211 #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7)
212 * - only on 75x/76x
213 */
214 #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6)
215 * - only on 75x/76x
216 */
217
218 /*
219 * TCR register bits
220 * TCR trigger levels are available from 0 to 60 characters with a granularity
221 * of four.
222 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
223 * no built-in hardware check to make sure this condition is met. Also, the TCR
224 * must be programmed with this condition before auto RTS or software flow
225 * control is enabled to avoid spurious operation of the device.
226 */
227 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
228 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
229
230 /*
231 * TLR register bits
232 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
233 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
234 * trigger levels. Trigger levels from 4 characters to 60 characters are
235 * available with a granularity of four.
236 *
237 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
238 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
239 * the trigger level defined in FCR is discarded. This applies to both transmit
240 * FIFO and receive FIFO trigger level setting.
241 *
242 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
243 * default state, that is, '00'.
244 */
245 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
246 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
247
248 /* IOControl register bits (Only 75x/76x) */
249 #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */
250 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */
251 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */
252 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
253
254 /* EFCR register bits */
255 #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop
256 * mode (RS485) */
257 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
258 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
259 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
260 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
261 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
262 * 0 = rate upto 115.2 kbit/s
263 * - Only 75x/76x
264 * 1 = rate upto 1.152 Mbit/s
265 * - Only 76x
266 */
267
268 /* EFR register bits */
269 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
270 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
271 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
272 #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions
273 * and writing to IER[7:4],
274 * FCR[5:4], MCR[7:5]
275 */
276 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
277 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
278 /*
279 * SWFLOW bits 3 & 2 table:
280 * 00 -> no transmitter flow
281 * control
282 * 01 -> transmitter generates
283 * XON2 and XOFF2
284 * 10 -> transmitter generates
285 * XON1 and XOFF1
286 * 11 -> transmitter generates
287 * XON1, XON2, XOFF1 and
288 * XOFF2
289 */
290 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
291 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
292 /*
293 * SWFLOW bits 1 & 0 table:
294 * 00 -> no received flow
295 * control
296 * 01 -> receiver compares
297 * XON2 and XOFF2
298 * 10 -> receiver compares
299 * XON1 and XOFF1
300 * 11 -> receiver compares
301 * XON1, XON2, XOFF1 and
302 * XOFF2
303 */
304 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
305 SC16IS7XX_EFR_AUTOCTS_BIT | \
306 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
307 SC16IS7XX_EFR_SWFLOW3_BIT | \
308 SC16IS7XX_EFR_SWFLOW2_BIT | \
309 SC16IS7XX_EFR_SWFLOW1_BIT | \
310 SC16IS7XX_EFR_SWFLOW0_BIT)
311
312
313 /* Misc definitions */
314 #define SC16IS7XX_FIFO_SIZE (64)
315 #define SC16IS7XX_GPIOS_PER_BANK 4
316
317 #define SC16IS7XX_POLL_PERIOD_MS 10
318 #define SC16IS7XX_RECONF_MD BIT(0)
319 #define SC16IS7XX_RECONF_IER BIT(1)
320 #define SC16IS7XX_RECONF_RS485 BIT(2)
321
322 struct sc16is7xx_one_config {
323 unsigned int flags;
324 u8 ier_mask;
325 u8 ier_val;
326 };
327
328 struct sc16is7xx_one {
329 struct uart_port port;
330 struct regmap *regmap;
331 struct mutex efr_lock; /* EFR registers access */
332 struct kthread_work tx_work;
333 struct kthread_work reg_work;
334 struct kthread_delayed_work ms_work;
335 struct sc16is7xx_one_config config;
336 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */
337 unsigned int old_mctrl;
338 u8 old_lcr; /* Value before EFR access. */
339 bool irda_mode;
340 };
341
342 struct sc16is7xx_port {
343 const struct sc16is7xx_devtype *devtype;
344 struct clk *clk;
345 #ifdef CONFIG_GPIOLIB
346 struct gpio_chip gpio;
347 unsigned long gpio_valid_mask;
348 #endif
349 u8 mctrl_mask;
350 struct kthread_worker kworker;
351 struct task_struct *kworker_task;
352 struct kthread_delayed_work poll_work;
353 bool polling;
354 struct sc16is7xx_one p[];
355 };
356
357 static DEFINE_IDA(sc16is7xx_lines);
358
359 static struct uart_driver sc16is7xx_uart = {
360 .owner = THIS_MODULE,
361 .driver_name = SC16IS7XX_NAME,
362 .dev_name = "ttySC",
363 .nr = SC16IS7XX_MAX_DEVS,
364 };
365
366 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
367
sc16is7xx_port_read(struct uart_port * port,u8 reg)368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
369 {
370 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
371 unsigned int val = 0;
372
373 regmap_read(one->regmap, reg, &val);
374
375 return val;
376 }
377
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)378 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
379 {
380 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
381
382 regmap_write(one->regmap, reg, val);
383 }
384
sc16is7xx_fifo_read(struct uart_port * port,u8 * rxbuf,unsigned int rxlen)385 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
386 {
387 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
388
389 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
390 }
391
sc16is7xx_fifo_write(struct uart_port * port,u8 * txbuf,u8 to_send)392 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
393 {
394 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
395
396 /*
397 * Don't send zero-length data, at least on SPI it confuses the chip
398 * delivering wrong TXLVL data.
399 */
400 if (unlikely(!to_send))
401 return;
402
403 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
404 }
405
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)406 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
407 u8 mask, u8 val)
408 {
409 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
410
411 regmap_update_bits(one->regmap, reg, mask, val);
412 }
413
sc16is7xx_power(struct uart_port * port,int on)414 static void sc16is7xx_power(struct uart_port *port, int on)
415 {
416 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
417 SC16IS7XX_IER_SLEEP_BIT,
418 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
419 }
420
421 /*
422 * In an amazing feat of design, the Enhanced Features Register (EFR)
423 * shares the address of the Interrupt Identification Register (IIR).
424 * Access to EFR is switched on by writing a magic value (0xbf) to the
425 * Line Control Register (LCR). Any interrupt firing during this time will
426 * see the EFR where it expects the IIR to be, leading to
427 * "Unexpected interrupt" messages.
428 *
429 * Prevent this possibility by claiming a mutex while accessing the EFR,
430 * and claiming the same mutex from within the interrupt handler. This is
431 * similar to disabling the interrupt, but that doesn't work because the
432 * bulk of the interrupt processing is run as a workqueue job in thread
433 * context.
434 */
sc16is7xx_efr_lock(struct uart_port * port)435 static void sc16is7xx_efr_lock(struct uart_port *port)
436 {
437 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
438
439 mutex_lock(&one->efr_lock);
440
441 /* Backup content of LCR. */
442 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
443
444 /* Enable access to Enhanced register set */
445 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B);
446
447 /* Disable cache updates when writing to EFR registers */
448 regcache_cache_bypass(one->regmap, true);
449 }
450
sc16is7xx_efr_unlock(struct uart_port * port)451 static void sc16is7xx_efr_unlock(struct uart_port *port)
452 {
453 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
454
455 /* Re-enable cache updates when writing to normal registers */
456 regcache_cache_bypass(one->regmap, false);
457
458 /* Restore original content of LCR */
459 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
460
461 mutex_unlock(&one->efr_lock);
462 }
463
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)464 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
465 {
466 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
467 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
468
469 lockdep_assert_held_once(&port->lock);
470
471 one->config.flags |= SC16IS7XX_RECONF_IER;
472 one->config.ier_mask |= bit;
473 one->config.ier_val &= ~bit;
474 kthread_queue_work(&s->kworker, &one->reg_work);
475 }
476
sc16is7xx_ier_set(struct uart_port * port,u8 bit)477 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
478 {
479 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
480 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
481
482 lockdep_assert_held_once(&port->lock);
483
484 one->config.flags |= SC16IS7XX_RECONF_IER;
485 one->config.ier_mask |= bit;
486 one->config.ier_val |= bit;
487 kthread_queue_work(&s->kworker, &one->reg_work);
488 }
489
sc16is7xx_stop_tx(struct uart_port * port)490 static void sc16is7xx_stop_tx(struct uart_port *port)
491 {
492 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
493 }
494
sc16is7xx_stop_rx(struct uart_port * port)495 static void sc16is7xx_stop_rx(struct uart_port *port)
496 {
497 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
498 }
499
500 const struct sc16is7xx_devtype sc16is74x_devtype = {
501 .name = "SC16IS74X",
502 .nr_gpio = 0,
503 .nr_uart = 1,
504 };
505 EXPORT_SYMBOL_GPL(sc16is74x_devtype);
506
507 const struct sc16is7xx_devtype sc16is750_devtype = {
508 .name = "SC16IS750",
509 .nr_gpio = 8,
510 .nr_uart = 1,
511 };
512 EXPORT_SYMBOL_GPL(sc16is750_devtype);
513
514 const struct sc16is7xx_devtype sc16is752_devtype = {
515 .name = "SC16IS752",
516 .nr_gpio = 8,
517 .nr_uart = 2,
518 };
519 EXPORT_SYMBOL_GPL(sc16is752_devtype);
520
521 const struct sc16is7xx_devtype sc16is760_devtype = {
522 .name = "SC16IS760",
523 .nr_gpio = 8,
524 .nr_uart = 1,
525 };
526 EXPORT_SYMBOL_GPL(sc16is760_devtype);
527
528 const struct sc16is7xx_devtype sc16is762_devtype = {
529 .name = "SC16IS762",
530 .nr_gpio = 8,
531 .nr_uart = 2,
532 };
533 EXPORT_SYMBOL_GPL(sc16is762_devtype);
534
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)535 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
536 {
537 switch (reg) {
538 case SC16IS7XX_RHR_REG:
539 case SC16IS7XX_IIR_REG:
540 case SC16IS7XX_LSR_REG:
541 case SC16IS7XX_MSR_REG:
542 case SC16IS7XX_TXLVL_REG:
543 case SC16IS7XX_RXLVL_REG:
544 case SC16IS7XX_IOSTATE_REG:
545 case SC16IS7XX_IOCONTROL_REG:
546 return true;
547 default:
548 return false;
549 }
550 }
551
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)552 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
553 {
554 switch (reg) {
555 case SC16IS7XX_RHR_REG:
556 return true;
557 default:
558 return false;
559 }
560 }
561
sc16is7xx_regmap_noinc(struct device * dev,unsigned int reg)562 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
563 {
564 return reg == SC16IS7XX_RHR_REG;
565 }
566
567 /*
568 * Configure programmable baud rate generator (divisor) according to the
569 * desired baud rate.
570 *
571 * From the datasheet, the divisor is computed according to:
572 *
573 * XTAL1 input frequency
574 * -----------------------
575 * prescaler
576 * divisor = ---------------------------
577 * baud-rate x sampling-rate
578 */
sc16is7xx_set_baud(struct uart_port * port,int baud)579 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
580 {
581 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
582 u8 lcr;
583 unsigned int prescaler = 1;
584 unsigned long clk = port->uartclk, div = clk / 16 / baud;
585
586 if (div >= BIT(16)) {
587 prescaler = 4;
588 div /= prescaler;
589 }
590
591 /* Enable enhanced features */
592 sc16is7xx_efr_lock(port);
593 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
594 SC16IS7XX_EFR_ENABLE_BIT,
595 SC16IS7XX_EFR_ENABLE_BIT);
596 sc16is7xx_efr_unlock(port);
597
598 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
599 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
600 SC16IS7XX_MCR_CLKSEL_BIT,
601 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
602
603 mutex_lock(&one->efr_lock);
604
605 /* Backup LCR and access special register set (DLL/DLH) */
606 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
607 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
608 SC16IS7XX_LCR_CONF_MODE_A);
609
610 /* Write the new divisor */
611 regcache_cache_bypass(one->regmap, true);
612 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
613 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
614 regcache_cache_bypass(one->regmap, false);
615
616 /* Restore LCR and access to general register set */
617 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
618
619 mutex_unlock(&one->efr_lock);
620
621 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
622 }
623
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)624 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
625 unsigned int iir)
626 {
627 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
628 unsigned int lsr = 0, bytes_read, i;
629 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
630 u8 ch, flag;
631
632 if (unlikely(rxlen >= sizeof(one->buf))) {
633 dev_warn_ratelimited(port->dev,
634 "ttySC%i: Possible RX FIFO overrun: %d\n",
635 port->line, rxlen);
636 port->icount.buf_overrun++;
637 /* Ensure sanity of RX level */
638 rxlen = sizeof(one->buf);
639 }
640
641 while (rxlen) {
642 /* Only read lsr if there are possible errors in FIFO */
643 if (read_lsr) {
644 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
645 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
646 read_lsr = false; /* No errors left in FIFO */
647 } else
648 lsr = 0;
649
650 if (read_lsr) {
651 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
652 bytes_read = 1;
653 } else {
654 sc16is7xx_fifo_read(port, one->buf, rxlen);
655 bytes_read = rxlen;
656 }
657
658 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
659
660 port->icount.rx++;
661 flag = TTY_NORMAL;
662
663 if (unlikely(lsr)) {
664 if (lsr & SC16IS7XX_LSR_BI_BIT) {
665 port->icount.brk++;
666 if (uart_handle_break(port))
667 continue;
668 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
669 port->icount.parity++;
670 else if (lsr & SC16IS7XX_LSR_FE_BIT)
671 port->icount.frame++;
672 else if (lsr & SC16IS7XX_LSR_OE_BIT)
673 port->icount.overrun++;
674
675 lsr &= port->read_status_mask;
676 if (lsr & SC16IS7XX_LSR_BI_BIT)
677 flag = TTY_BREAK;
678 else if (lsr & SC16IS7XX_LSR_PE_BIT)
679 flag = TTY_PARITY;
680 else if (lsr & SC16IS7XX_LSR_FE_BIT)
681 flag = TTY_FRAME;
682 else if (lsr & SC16IS7XX_LSR_OE_BIT)
683 flag = TTY_OVERRUN;
684 }
685
686 for (i = 0; i < bytes_read; ++i) {
687 ch = one->buf[i];
688 if (uart_handle_sysrq_char(port, ch))
689 continue;
690
691 if (lsr & port->ignore_status_mask)
692 continue;
693
694 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
695 flag);
696 }
697 rxlen -= bytes_read;
698 }
699
700 tty_flip_buffer_push(&port->state->port);
701 }
702
sc16is7xx_handle_tx(struct uart_port * port)703 static void sc16is7xx_handle_tx(struct uart_port *port)
704 {
705 struct tty_port *tport = &port->state->port;
706 unsigned long flags;
707 unsigned int txlen;
708 unsigned char *tail;
709
710 if (unlikely(port->x_char)) {
711 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
712 port->icount.tx++;
713 port->x_char = 0;
714 return;
715 }
716
717 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
718 uart_port_lock_irqsave(port, &flags);
719 sc16is7xx_stop_tx(port);
720 uart_port_unlock_irqrestore(port, flags);
721 return;
722 }
723
724 /* Limit to space available in TX FIFO */
725 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
726 if (txlen > SC16IS7XX_FIFO_SIZE) {
727 dev_err_ratelimited(port->dev,
728 "chip reports %d free bytes in TX fifo, but it only has %d",
729 txlen, SC16IS7XX_FIFO_SIZE);
730 txlen = 0;
731 }
732
733 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);
734 sc16is7xx_fifo_write(port, tail, txlen);
735 uart_xmit_advance(port, txlen);
736
737 uart_port_lock_irqsave(port, &flags);
738 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
739 uart_write_wakeup(port);
740
741 if (kfifo_is_empty(&tport->xmit_fifo))
742 sc16is7xx_stop_tx(port);
743 else
744 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
745 uart_port_unlock_irqrestore(port, flags);
746 }
747
sc16is7xx_get_hwmctrl(struct uart_port * port)748 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
749 {
750 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
751 unsigned int mctrl = 0;
752
753 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
754 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
755 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
756 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
757 return mctrl;
758 }
759
sc16is7xx_update_mlines(struct sc16is7xx_one * one)760 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
761 {
762 struct uart_port *port = &one->port;
763 unsigned long flags;
764 unsigned int status, changed;
765
766 lockdep_assert_held_once(&one->efr_lock);
767
768 status = sc16is7xx_get_hwmctrl(port);
769 changed = status ^ one->old_mctrl;
770
771 if (changed == 0)
772 return;
773
774 one->old_mctrl = status;
775
776 uart_port_lock_irqsave(port, &flags);
777 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
778 port->icount.rng++;
779 if (changed & TIOCM_DSR)
780 port->icount.dsr++;
781 if (changed & TIOCM_CAR)
782 uart_handle_dcd_change(port, status & TIOCM_CAR);
783 if (changed & TIOCM_CTS)
784 uart_handle_cts_change(port, status & TIOCM_CTS);
785
786 wake_up_interruptible(&port->state->port.delta_msr_wait);
787 uart_port_unlock_irqrestore(port, flags);
788 }
789
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)790 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
791 {
792 bool rc = true;
793 unsigned int iir, rxlen;
794 struct uart_port *port = &s->p[portno].port;
795 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
796
797 mutex_lock(&one->efr_lock);
798
799 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
800 if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
801 rc = false;
802 goto out_port_irq;
803 }
804
805 iir &= SC16IS7XX_IIR_ID_MASK;
806
807 switch (iir) {
808 case SC16IS7XX_IIR_RDI_SRC:
809 case SC16IS7XX_IIR_RLSE_SRC:
810 case SC16IS7XX_IIR_RTOI_SRC:
811 case SC16IS7XX_IIR_XOFFI_SRC:
812 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
813
814 /*
815 * There is a silicon bug that makes the chip report a
816 * time-out interrupt but no data in the FIFO. This is
817 * described in errata section 18.1.4.
818 *
819 * When this happens, read one byte from the FIFO to
820 * clear the interrupt.
821 */
822 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
823 rxlen = 1;
824
825 if (rxlen)
826 sc16is7xx_handle_rx(port, rxlen, iir);
827 break;
828 /* CTSRTS interrupt comes only when CTS goes inactive */
829 case SC16IS7XX_IIR_CTSRTS_SRC:
830 case SC16IS7XX_IIR_MSI_SRC:
831 sc16is7xx_update_mlines(one);
832 break;
833 case SC16IS7XX_IIR_THRI_SRC:
834 sc16is7xx_handle_tx(port);
835 break;
836 default:
837 dev_err_ratelimited(port->dev,
838 "ttySC%i: Unexpected interrupt: %x",
839 port->line, iir);
840 break;
841 }
842
843 out_port_irq:
844 mutex_unlock(&one->efr_lock);
845
846 return rc;
847 }
848
sc16is7xx_irq(int irq,void * dev_id)849 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
850 {
851 bool keep_polling;
852
853 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
854
855 do {
856 int i;
857
858 keep_polling = false;
859
860 for (i = 0; i < s->devtype->nr_uart; ++i)
861 keep_polling |= sc16is7xx_port_irq(s, i);
862 } while (keep_polling);
863
864 return IRQ_HANDLED;
865 }
866
sc16is7xx_poll_proc(struct kthread_work * ws)867 static void sc16is7xx_poll_proc(struct kthread_work *ws)
868 {
869 struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work);
870
871 /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */
872 sc16is7xx_irq(0, s);
873
874 /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */
875 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
876 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
877 }
878
sc16is7xx_tx_proc(struct kthread_work * ws)879 static void sc16is7xx_tx_proc(struct kthread_work *ws)
880 {
881 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
882 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
883
884 if ((port->rs485.flags & SER_RS485_ENABLED) &&
885 (port->rs485.delay_rts_before_send > 0))
886 msleep(port->rs485.delay_rts_before_send);
887
888 mutex_lock(&one->efr_lock);
889 sc16is7xx_handle_tx(port);
890 mutex_unlock(&one->efr_lock);
891 }
892
sc16is7xx_reconf_rs485(struct uart_port * port)893 static void sc16is7xx_reconf_rs485(struct uart_port *port)
894 {
895 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
896 SC16IS7XX_EFCR_RTS_INVERT_BIT;
897 u32 efcr = 0;
898 struct serial_rs485 *rs485 = &port->rs485;
899 unsigned long irqflags;
900
901 uart_port_lock_irqsave(port, &irqflags);
902 if (rs485->flags & SER_RS485_ENABLED) {
903 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
904
905 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
906 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
907 }
908 uart_port_unlock_irqrestore(port, irqflags);
909
910 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
911 }
912
sc16is7xx_reg_proc(struct kthread_work * ws)913 static void sc16is7xx_reg_proc(struct kthread_work *ws)
914 {
915 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
916 struct sc16is7xx_one_config config;
917 unsigned long irqflags;
918
919 uart_port_lock_irqsave(&one->port, &irqflags);
920 config = one->config;
921 memset(&one->config, 0, sizeof(one->config));
922 uart_port_unlock_irqrestore(&one->port, irqflags);
923
924 if (config.flags & SC16IS7XX_RECONF_MD) {
925 u8 mcr = 0;
926
927 /* Device ignores RTS setting when hardware flow is enabled */
928 if (one->port.mctrl & TIOCM_RTS)
929 mcr |= SC16IS7XX_MCR_RTS_BIT;
930
931 if (one->port.mctrl & TIOCM_DTR)
932 mcr |= SC16IS7XX_MCR_DTR_BIT;
933
934 if (one->port.mctrl & TIOCM_LOOP)
935 mcr |= SC16IS7XX_MCR_LOOP_BIT;
936 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
937 SC16IS7XX_MCR_RTS_BIT |
938 SC16IS7XX_MCR_DTR_BIT |
939 SC16IS7XX_MCR_LOOP_BIT,
940 mcr);
941 }
942
943 if (config.flags & SC16IS7XX_RECONF_IER)
944 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
945 config.ier_mask, config.ier_val);
946
947 if (config.flags & SC16IS7XX_RECONF_RS485)
948 sc16is7xx_reconf_rs485(&one->port);
949 }
950
sc16is7xx_ms_proc(struct kthread_work * ws)951 static void sc16is7xx_ms_proc(struct kthread_work *ws)
952 {
953 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
954 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
955
956 if (one->port.state) {
957 mutex_lock(&one->efr_lock);
958 sc16is7xx_update_mlines(one);
959 mutex_unlock(&one->efr_lock);
960
961 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
962 }
963 }
964
sc16is7xx_enable_ms(struct uart_port * port)965 static void sc16is7xx_enable_ms(struct uart_port *port)
966 {
967 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
968 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
969
970 lockdep_assert_held_once(&port->lock);
971
972 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
973 }
974
sc16is7xx_start_tx(struct uart_port * port)975 static void sc16is7xx_start_tx(struct uart_port *port)
976 {
977 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
978 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
979
980 kthread_queue_work(&s->kworker, &one->tx_work);
981 }
982
sc16is7xx_throttle(struct uart_port * port)983 static void sc16is7xx_throttle(struct uart_port *port)
984 {
985 unsigned long flags;
986
987 /*
988 * Hardware flow control is enabled and thus the device ignores RTS
989 * value set in MCR register. Stop reading data from RX FIFO so the
990 * AutoRTS feature will de-activate RTS output.
991 */
992 uart_port_lock_irqsave(port, &flags);
993 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
994 uart_port_unlock_irqrestore(port, flags);
995 }
996
sc16is7xx_unthrottle(struct uart_port * port)997 static void sc16is7xx_unthrottle(struct uart_port *port)
998 {
999 unsigned long flags;
1000
1001 uart_port_lock_irqsave(port, &flags);
1002 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
1003 uart_port_unlock_irqrestore(port, flags);
1004 }
1005
sc16is7xx_tx_empty(struct uart_port * port)1006 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
1007 {
1008 unsigned int lsr;
1009
1010 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
1011
1012 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
1013 }
1014
sc16is7xx_get_mctrl(struct uart_port * port)1015 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
1016 {
1017 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1018
1019 /* Called with port lock taken so we can only return cached value */
1020 return one->old_mctrl;
1021 }
1022
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)1023 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
1024 {
1025 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1026 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1027
1028 one->config.flags |= SC16IS7XX_RECONF_MD;
1029 kthread_queue_work(&s->kworker, &one->reg_work);
1030 }
1031
sc16is7xx_break_ctl(struct uart_port * port,int break_state)1032 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1033 {
1034 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1035 SC16IS7XX_LCR_TXBREAK_BIT,
1036 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1037 }
1038
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1039 static void sc16is7xx_set_termios(struct uart_port *port,
1040 struct ktermios *termios,
1041 const struct ktermios *old)
1042 {
1043 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1044 unsigned int lcr, flow = 0;
1045 int baud;
1046 unsigned long flags;
1047
1048 kthread_cancel_delayed_work_sync(&one->ms_work);
1049
1050 /* Mask termios capabilities we don't support */
1051 termios->c_cflag &= ~CMSPAR;
1052
1053 /* Word size */
1054 switch (termios->c_cflag & CSIZE) {
1055 case CS5:
1056 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1057 break;
1058 case CS6:
1059 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1060 break;
1061 case CS7:
1062 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1063 break;
1064 case CS8:
1065 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1066 break;
1067 default:
1068 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1069 termios->c_cflag &= ~CSIZE;
1070 termios->c_cflag |= CS8;
1071 break;
1072 }
1073
1074 /* Parity */
1075 if (termios->c_cflag & PARENB) {
1076 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1077 if (!(termios->c_cflag & PARODD))
1078 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1079 }
1080
1081 /* Stop bits */
1082 if (termios->c_cflag & CSTOPB)
1083 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1084
1085 /* Set read status mask */
1086 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1087 if (termios->c_iflag & INPCK)
1088 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1089 SC16IS7XX_LSR_FE_BIT;
1090 if (termios->c_iflag & (BRKINT | PARMRK))
1091 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1092
1093 /* Set status ignore mask */
1094 port->ignore_status_mask = 0;
1095 if (termios->c_iflag & IGNBRK)
1096 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1097 if (!(termios->c_cflag & CREAD))
1098 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1099
1100 /* Configure flow control */
1101 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1102 if (termios->c_cflag & CRTSCTS) {
1103 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1104 SC16IS7XX_EFR_AUTORTS_BIT;
1105 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1106 }
1107 if (termios->c_iflag & IXON)
1108 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1109 if (termios->c_iflag & IXOFF)
1110 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1111
1112 /* Update LCR register */
1113 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1114
1115 /* Update EFR registers */
1116 sc16is7xx_efr_lock(port);
1117 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1118 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1119 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1120 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1121 sc16is7xx_efr_unlock(port);
1122
1123 /* Get baud rate generator configuration */
1124 baud = uart_get_baud_rate(port, termios, old,
1125 port->uartclk / 16 / 4 / 0xffff,
1126 port->uartclk / 16);
1127
1128 /* Setup baudrate generator */
1129 baud = sc16is7xx_set_baud(port, baud);
1130
1131 uart_port_lock_irqsave(port, &flags);
1132
1133 /* Update timeout according to new baud rate */
1134 uart_update_timeout(port, termios->c_cflag, baud);
1135
1136 if (UART_ENABLE_MS(port, termios->c_cflag))
1137 sc16is7xx_enable_ms(port);
1138
1139 uart_port_unlock_irqrestore(port, flags);
1140 }
1141
sc16is7xx_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1142 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1143 struct serial_rs485 *rs485)
1144 {
1145 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1146 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1147
1148 if (rs485->flags & SER_RS485_ENABLED) {
1149 /*
1150 * RTS signal is handled by HW, it's timing can't be influenced.
1151 * However, it's sometimes useful to delay TX even without RTS
1152 * control therefore we try to handle .delay_rts_before_send.
1153 */
1154 if (rs485->delay_rts_after_send)
1155 return -EINVAL;
1156 }
1157
1158 one->config.flags |= SC16IS7XX_RECONF_RS485;
1159 kthread_queue_work(&s->kworker, &one->reg_work);
1160
1161 return 0;
1162 }
1163
sc16is7xx_startup(struct uart_port * port)1164 static int sc16is7xx_startup(struct uart_port *port)
1165 {
1166 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1167 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1168 unsigned int val;
1169 unsigned long flags;
1170
1171 sc16is7xx_power(port, 1);
1172
1173 /* Reset FIFOs*/
1174 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1175 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1176 udelay(5);
1177 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1178 SC16IS7XX_FCR_FIFO_BIT);
1179
1180 /* Enable EFR */
1181 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1182 SC16IS7XX_LCR_CONF_MODE_B);
1183
1184 regcache_cache_bypass(one->regmap, true);
1185
1186 /* Enable write access to enhanced features and internal clock div */
1187 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1188 SC16IS7XX_EFR_ENABLE_BIT,
1189 SC16IS7XX_EFR_ENABLE_BIT);
1190
1191 /* Enable TCR/TLR */
1192 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1193 SC16IS7XX_MCR_TCRTLR_BIT,
1194 SC16IS7XX_MCR_TCRTLR_BIT);
1195
1196 /* Configure flow control levels */
1197 /* Flow control halt level 48, resume level 24 */
1198 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1199 SC16IS7XX_TCR_RX_RESUME(24) |
1200 SC16IS7XX_TCR_RX_HALT(48));
1201
1202 regcache_cache_bypass(one->regmap, false);
1203
1204 /* Now, initialize the UART */
1205 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1206
1207 /* Enable IrDA mode if requested in DT */
1208 /* This bit must be written with LCR[7] = 0 */
1209 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1210 SC16IS7XX_MCR_IRDA_BIT,
1211 one->irda_mode ?
1212 SC16IS7XX_MCR_IRDA_BIT : 0);
1213
1214 /* Enable the Rx and Tx FIFO */
1215 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1216 SC16IS7XX_EFCR_RXDISABLE_BIT |
1217 SC16IS7XX_EFCR_TXDISABLE_BIT,
1218 0);
1219
1220 /* Enable RX, CTS change and modem lines interrupts */
1221 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1222 SC16IS7XX_IER_MSI_BIT;
1223 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1224
1225 /* Enable modem status polling */
1226 uart_port_lock_irqsave(port, &flags);
1227 sc16is7xx_enable_ms(port);
1228 uart_port_unlock_irqrestore(port, flags);
1229
1230 if (s->polling)
1231 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
1232 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
1233
1234 return 0;
1235 }
1236
sc16is7xx_shutdown(struct uart_port * port)1237 static void sc16is7xx_shutdown(struct uart_port *port)
1238 {
1239 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1240 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1241
1242 kthread_cancel_delayed_work_sync(&one->ms_work);
1243
1244 /* Disable all interrupts */
1245 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1246 /* Disable TX/RX */
1247 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1248 SC16IS7XX_EFCR_RXDISABLE_BIT |
1249 SC16IS7XX_EFCR_TXDISABLE_BIT,
1250 SC16IS7XX_EFCR_RXDISABLE_BIT |
1251 SC16IS7XX_EFCR_TXDISABLE_BIT);
1252
1253 sc16is7xx_power(port, 0);
1254
1255 if (s->polling)
1256 kthread_cancel_delayed_work_sync(&s->poll_work);
1257
1258 kthread_flush_worker(&s->kworker);
1259 }
1260
sc16is7xx_type(struct uart_port * port)1261 static const char *sc16is7xx_type(struct uart_port *port)
1262 {
1263 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1264
1265 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1266 }
1267
sc16is7xx_request_port(struct uart_port * port)1268 static int sc16is7xx_request_port(struct uart_port *port)
1269 {
1270 /* Do nothing */
1271 return 0;
1272 }
1273
sc16is7xx_config_port(struct uart_port * port,int flags)1274 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1275 {
1276 if (flags & UART_CONFIG_TYPE)
1277 port->type = PORT_SC16IS7XX;
1278 }
1279
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1280 static int sc16is7xx_verify_port(struct uart_port *port,
1281 struct serial_struct *s)
1282 {
1283 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1284 return -EINVAL;
1285 if (s->irq != port->irq)
1286 return -EINVAL;
1287
1288 return 0;
1289 }
1290
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1291 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1292 unsigned int oldstate)
1293 {
1294 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1295 }
1296
sc16is7xx_null_void(struct uart_port * port)1297 static void sc16is7xx_null_void(struct uart_port *port)
1298 {
1299 /* Do nothing */
1300 }
1301
1302 static const struct uart_ops sc16is7xx_ops = {
1303 .tx_empty = sc16is7xx_tx_empty,
1304 .set_mctrl = sc16is7xx_set_mctrl,
1305 .get_mctrl = sc16is7xx_get_mctrl,
1306 .stop_tx = sc16is7xx_stop_tx,
1307 .start_tx = sc16is7xx_start_tx,
1308 .throttle = sc16is7xx_throttle,
1309 .unthrottle = sc16is7xx_unthrottle,
1310 .stop_rx = sc16is7xx_stop_rx,
1311 .enable_ms = sc16is7xx_enable_ms,
1312 .break_ctl = sc16is7xx_break_ctl,
1313 .startup = sc16is7xx_startup,
1314 .shutdown = sc16is7xx_shutdown,
1315 .set_termios = sc16is7xx_set_termios,
1316 .type = sc16is7xx_type,
1317 .request_port = sc16is7xx_request_port,
1318 .release_port = sc16is7xx_null_void,
1319 .config_port = sc16is7xx_config_port,
1320 .verify_port = sc16is7xx_verify_port,
1321 .pm = sc16is7xx_pm,
1322 };
1323
1324 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1325 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1326 {
1327 unsigned int val;
1328 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1329 struct uart_port *port = &s->p[0].port;
1330
1331 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1332
1333 return !!(val & BIT(offset));
1334 }
1335
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned offset,int val)1336 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1337 {
1338 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1339 struct uart_port *port = &s->p[0].port;
1340
1341 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1342 val ? BIT(offset) : 0);
1343 }
1344
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1345 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1346 unsigned offset)
1347 {
1348 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1349 struct uart_port *port = &s->p[0].port;
1350
1351 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1352
1353 return 0;
1354 }
1355
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1356 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1357 unsigned offset, int val)
1358 {
1359 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1360 struct uart_port *port = &s->p[0].port;
1361 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1362
1363 if (val)
1364 state |= BIT(offset);
1365 else
1366 state &= ~BIT(offset);
1367
1368 /*
1369 * If we write IOSTATE first, and then IODIR, the output value is not
1370 * transferred to the corresponding I/O pin.
1371 * The datasheet states that each register bit will be transferred to
1372 * the corresponding I/O pin programmed as output when writing to
1373 * IOSTATE. Therefore, configure direction first with IODIR, and then
1374 * set value after with IOSTATE.
1375 */
1376 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1377 BIT(offset));
1378 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1379
1380 return 0;
1381 }
1382
sc16is7xx_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1383 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1384 unsigned long *valid_mask,
1385 unsigned int ngpios)
1386 {
1387 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1388
1389 *valid_mask = s->gpio_valid_mask;
1390
1391 return 0;
1392 }
1393
sc16is7xx_setup_gpio_chip(struct sc16is7xx_port * s)1394 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1395 {
1396 struct device *dev = s->p[0].port.dev;
1397
1398 if (!s->devtype->nr_gpio)
1399 return 0;
1400
1401 switch (s->mctrl_mask) {
1402 case 0:
1403 s->gpio_valid_mask = GENMASK(7, 0);
1404 break;
1405 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1406 s->gpio_valid_mask = GENMASK(3, 0);
1407 break;
1408 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1409 s->gpio_valid_mask = GENMASK(7, 4);
1410 break;
1411 default:
1412 break;
1413 }
1414
1415 if (s->gpio_valid_mask == 0)
1416 return 0;
1417
1418 s->gpio.owner = THIS_MODULE;
1419 s->gpio.parent = dev;
1420 s->gpio.label = dev_name(dev);
1421 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1422 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1423 s->gpio.get = sc16is7xx_gpio_get;
1424 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1425 s->gpio.set = sc16is7xx_gpio_set;
1426 s->gpio.base = -1;
1427 s->gpio.ngpio = s->devtype->nr_gpio;
1428 s->gpio.can_sleep = 1;
1429
1430 return gpiochip_add_data(&s->gpio, s);
1431 }
1432 #endif
1433
sc16is7xx_setup_irda_ports(struct sc16is7xx_port * s)1434 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1435 {
1436 int i;
1437 int ret;
1438 int count;
1439 u32 irda_port[SC16IS7XX_MAX_PORTS];
1440 struct device *dev = s->p[0].port.dev;
1441
1442 count = device_property_count_u32(dev, "irda-mode-ports");
1443 if (count < 0 || count > ARRAY_SIZE(irda_port))
1444 return;
1445
1446 ret = device_property_read_u32_array(dev, "irda-mode-ports",
1447 irda_port, count);
1448 if (ret)
1449 return;
1450
1451 for (i = 0; i < count; i++) {
1452 if (irda_port[i] < s->devtype->nr_uart)
1453 s->p[irda_port[i]].irda_mode = true;
1454 }
1455 }
1456
1457 /*
1458 * Configure ports designated to operate as modem control lines.
1459 */
sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port * s,struct regmap * regmap)1460 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1461 struct regmap *regmap)
1462 {
1463 int i;
1464 int ret;
1465 int count;
1466 u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1467 struct device *dev = s->p[0].port.dev;
1468
1469 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1470 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1471 return 0;
1472
1473 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1474 mctrl_port, count);
1475 if (ret)
1476 return ret;
1477
1478 s->mctrl_mask = 0;
1479
1480 for (i = 0; i < count; i++) {
1481 /* Use GPIO lines as modem control lines */
1482 if (mctrl_port[i] == 0)
1483 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1484 else if (mctrl_port[i] == 1)
1485 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1486 }
1487
1488 if (s->mctrl_mask)
1489 regmap_update_bits(
1490 regmap,
1491 SC16IS7XX_IOCONTROL_REG,
1492 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1493 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1494
1495 return 0;
1496 }
1497
1498 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1499 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1500 .delay_rts_before_send = 1,
1501 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1502 };
1503
1504 /* Reset device, purging any pending irq / data */
sc16is7xx_reset(struct device * dev,struct regmap * regmap)1505 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap)
1506 {
1507 struct gpio_desc *reset_gpio;
1508
1509 /* Assert reset GPIO if defined and valid. */
1510 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1511 if (IS_ERR(reset_gpio))
1512 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n");
1513
1514 if (reset_gpio) {
1515 /* The minimum reset pulse width is 3 us. */
1516 fsleep(5);
1517 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */
1518 } else {
1519 /* Software reset */
1520 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG,
1521 SC16IS7XX_IOCONTROL_SRESET_BIT);
1522 }
1523
1524 return 0;
1525 }
1526
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmaps[],int irq)1527 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,
1528 struct regmap *regmaps[], int irq)
1529 {
1530 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1531 unsigned int val;
1532 u32 uartclk = 0;
1533 int i, ret;
1534 struct sc16is7xx_port *s;
1535 bool port_registered[SC16IS7XX_MAX_PORTS];
1536
1537 for (i = 0; i < devtype->nr_uart; i++)
1538 if (IS_ERR(regmaps[i]))
1539 return PTR_ERR(regmaps[i]);
1540
1541 /*
1542 * This device does not have an identification register that would
1543 * tell us if we are really connected to the correct device.
1544 * The best we can do is to check if communication is at all possible.
1545 *
1546 * Note: regmap[0] is used in the probe function to access registers
1547 * common to all channels/ports, as it is guaranteed to be present on
1548 * all variants.
1549 */
1550 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1551 if (ret < 0)
1552 return -EPROBE_DEFER;
1553
1554 /* Alloc port structure */
1555 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1556 if (!s) {
1557 dev_err(dev, "Error allocating port structure\n");
1558 return -ENOMEM;
1559 }
1560
1561 /* Always ask for fixed clock rate from a property. */
1562 device_property_read_u32(dev, "clock-frequency", &uartclk);
1563
1564 s->polling = (irq <= 0);
1565 if (s->polling)
1566 dev_dbg(dev,
1567 "No interrupt pin definition, falling back to polling mode\n");
1568
1569 s->clk = devm_clk_get_optional(dev, NULL);
1570 if (IS_ERR(s->clk))
1571 return PTR_ERR(s->clk);
1572
1573 ret = clk_prepare_enable(s->clk);
1574 if (ret)
1575 return ret;
1576
1577 freq = clk_get_rate(s->clk);
1578 if (freq == 0) {
1579 if (uartclk)
1580 freq = uartclk;
1581 if (pfreq)
1582 freq = *pfreq;
1583 if (freq)
1584 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1585 else
1586 return -EINVAL;
1587 }
1588
1589 s->devtype = devtype;
1590 dev_set_drvdata(dev, s);
1591
1592 kthread_init_worker(&s->kworker);
1593 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1594 "sc16is7xx");
1595 if (IS_ERR(s->kworker_task)) {
1596 ret = PTR_ERR(s->kworker_task);
1597 goto out_clk;
1598 }
1599 sched_set_fifo(s->kworker_task);
1600
1601 ret = sc16is7xx_reset(dev, regmaps[0]);
1602 if (ret)
1603 goto out_kthread;
1604
1605 /* Mark each port line and status as uninitialised. */
1606 for (i = 0; i < devtype->nr_uart; ++i) {
1607 s->p[i].port.line = SC16IS7XX_MAX_DEVS;
1608 port_registered[i] = false;
1609 }
1610
1611 for (i = 0; i < devtype->nr_uart; ++i) {
1612 ret = ida_alloc_max(&sc16is7xx_lines,
1613 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);
1614 if (ret < 0)
1615 goto out_ports;
1616
1617 s->p[i].port.line = ret;
1618
1619 /* Initialize port data */
1620 s->p[i].port.dev = dev;
1621 s->p[i].port.irq = irq;
1622 s->p[i].port.type = PORT_SC16IS7XX;
1623 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1624 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1625 s->p[i].port.iobase = i;
1626 /*
1627 * Use all ones as membase to make sure uart_configure_port() in
1628 * serial_core.c does not abort for SPI/I2C devices where the
1629 * membase address is not applicable.
1630 */
1631 s->p[i].port.membase = (void __iomem *)~0;
1632 s->p[i].port.iotype = UPIO_PORT;
1633 s->p[i].port.uartclk = freq;
1634 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1635 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1636 s->p[i].port.ops = &sc16is7xx_ops;
1637 s->p[i].old_mctrl = 0;
1638 s->p[i].regmap = regmaps[i];
1639
1640 mutex_init(&s->p[i].efr_lock);
1641
1642 ret = uart_get_rs485_mode(&s->p[i].port);
1643 if (ret)
1644 goto out_ports;
1645
1646 /* Disable all interrupts */
1647 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1648 /* Disable TX/RX */
1649 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1650 SC16IS7XX_EFCR_RXDISABLE_BIT |
1651 SC16IS7XX_EFCR_TXDISABLE_BIT);
1652
1653 /* Initialize kthread work structs */
1654 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1655 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1656 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1657
1658 /* Register port */
1659 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1660 if (ret)
1661 goto out_ports;
1662
1663 port_registered[i] = true;
1664
1665 /* Enable EFR */
1666 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1667 SC16IS7XX_LCR_CONF_MODE_B);
1668
1669 regcache_cache_bypass(regmaps[i], true);
1670
1671 /* Enable write access to enhanced features */
1672 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1673 SC16IS7XX_EFR_ENABLE_BIT);
1674
1675 regcache_cache_bypass(regmaps[i], false);
1676
1677 /* Restore access to general registers */
1678 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1679
1680 /* Go to suspend mode */
1681 sc16is7xx_power(&s->p[i].port, 0);
1682 }
1683
1684 sc16is7xx_setup_irda_ports(s);
1685
1686 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1687 if (ret)
1688 goto out_ports;
1689
1690 #ifdef CONFIG_GPIOLIB
1691 ret = sc16is7xx_setup_gpio_chip(s);
1692 if (ret)
1693 goto out_ports;
1694 #endif
1695
1696 if (s->polling) {
1697 /* Initialize kernel thread for polling */
1698 kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc);
1699 return 0;
1700 }
1701
1702 /*
1703 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1704 * If that succeeds, we can allow sharing the interrupt as well.
1705 * In case the interrupt controller doesn't support that, we fall
1706 * back to a non-shared falling-edge trigger.
1707 */
1708 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1709 IRQF_TRIGGER_LOW | IRQF_SHARED |
1710 IRQF_ONESHOT,
1711 dev_name(dev), s);
1712 if (!ret)
1713 return 0;
1714
1715 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1716 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1717 dev_name(dev), s);
1718 if (!ret)
1719 return 0;
1720
1721 #ifdef CONFIG_GPIOLIB
1722 if (s->gpio_valid_mask)
1723 gpiochip_remove(&s->gpio);
1724 #endif
1725
1726 out_ports:
1727 for (i = 0; i < devtype->nr_uart; i++) {
1728 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)
1729 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1730 if (port_registered[i])
1731 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1732 }
1733
1734 out_kthread:
1735 kthread_stop(s->kworker_task);
1736
1737 out_clk:
1738 clk_disable_unprepare(s->clk);
1739
1740 return ret;
1741 }
1742 EXPORT_SYMBOL_GPL(sc16is7xx_probe);
1743
sc16is7xx_remove(struct device * dev)1744 void sc16is7xx_remove(struct device *dev)
1745 {
1746 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1747 int i;
1748
1749 #ifdef CONFIG_GPIOLIB
1750 if (s->gpio_valid_mask)
1751 gpiochip_remove(&s->gpio);
1752 #endif
1753
1754 for (i = 0; i < s->devtype->nr_uart; i++) {
1755 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1756 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1757 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1758 sc16is7xx_power(&s->p[i].port, 0);
1759 }
1760
1761 if (s->polling)
1762 kthread_cancel_delayed_work_sync(&s->poll_work);
1763
1764 kthread_flush_worker(&s->kworker);
1765 kthread_stop(s->kworker_task);
1766
1767 clk_disable_unprepare(s->clk);
1768 }
1769 EXPORT_SYMBOL_GPL(sc16is7xx_remove);
1770
1771 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1772 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1773 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1774 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1775 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1776 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1777 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1778 { }
1779 };
1780 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);
1781 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1782
1783 const struct regmap_config sc16is7xx_regcfg = {
1784 .reg_bits = 5,
1785 .pad_bits = 3,
1786 .val_bits = 8,
1787 .cache_type = REGCACHE_MAPLE,
1788 .volatile_reg = sc16is7xx_regmap_volatile,
1789 .precious_reg = sc16is7xx_regmap_precious,
1790 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1791 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1792 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1793 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1794 .max_register = SC16IS7XX_EFCR_REG,
1795 };
1796 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);
1797
sc16is7xx_regmap_name(u8 port_id)1798 const char *sc16is7xx_regmap_name(u8 port_id)
1799 {
1800 switch (port_id) {
1801 case 0: return "port0";
1802 case 1: return "port1";
1803 default:
1804 WARN_ON(true);
1805 return NULL;
1806 }
1807 }
1808 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);
1809
sc16is7xx_regmap_port_mask(unsigned int port_id)1810 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1811 {
1812 /* CH1,CH0 are at bits 2:1. */
1813 return port_id << 1;
1814 }
1815 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);
1816
sc16is7xx_init(void)1817 static int __init sc16is7xx_init(void)
1818 {
1819 return uart_register_driver(&sc16is7xx_uart);
1820 }
1821 module_init(sc16is7xx_init);
1822
sc16is7xx_exit(void)1823 static void __exit sc16is7xx_exit(void)
1824 {
1825 uart_unregister_driver(&sc16is7xx_uart);
1826 }
1827 module_exit(sc16is7xx_exit);
1828
1829 MODULE_LICENSE("GPL");
1830 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1831 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver");
1832