1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of MARVELL nor the names of contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #ifndef _MVREG_H_ 35 #define _MVREG_H_ 36 37 #include <arm/mv/mvwin.h> 38 39 #define IRQ_CAUSE 0x0 40 #define IRQ_MASK 0x4 41 #define FIQ_MASK 0x8 42 #define ENDPOINT_IRQ_MASK(n) 0xC 43 #define IRQ_CAUSE_HI 0x10 44 #define IRQ_MASK_HI 0x14 45 #define FIQ_MASK_HI 0x18 46 #define ENDPOINT_IRQ_MASK_HI(n) 0x1C 47 #define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 48 #define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 49 #define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 50 51 #define MAIN_IRQ_NUM 116 52 #define ERR_IRQ_NUM 32 53 #define ERR_IRQ (MAIN_IRQ_NUM) 54 #define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM) 55 56 #define MSI_IRQ_NUM 32 57 58 #define IRQ_CPU_SELF 0x00000001 59 #define BRIDGE_IRQ_CAUSE_ARMADAXP 0x68 60 #define IRQ_TIMER0_ARMADAXP 0x00000001 61 #define IRQ_TIMER1_ARMADAXP 0x00000002 62 #define IRQ_TIMER_WD_ARMADAXP 0x00000004 63 64 #define BRIDGE_IRQ_CAUSE 0x10 65 #define IRQ_CPU_SELF 0x00000001 66 #define IRQ_TIMER0 0x00000002 67 #define IRQ_TIMER1 0x00000004 68 #define IRQ_TIMER_WD 0x00000008 69 70 #define BRIDGE_IRQ_MASK 0x14 71 #define IRQ_CPU_MASK 0x00000001 72 #define IRQ_TIMER0_MASK 0x00000002 73 #define IRQ_TIMER1_MASK 0x00000004 74 #define IRQ_TIMER_WD_MASK 0x00000008 75 76 #define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 77 #define IRQ_TIMER0_CLR (~IRQ_TIMER0) 78 #define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 79 80 #define IRQ_TIMER0_CLR_ARMADAXP (~IRQ_TIMER0_ARMADAXP) 81 #define IRQ_TIMER_WD_CLR_ARMADAXP (~IRQ_TIMER_WD_ARMADAXP) 82 83 /* 84 * System reset 85 */ 86 #define RSTOUTn_MASK_ARMV7 0x60 87 #define SYSTEM_SOFT_RESET_ARMV7 0x64 88 #define SOFT_RST_OUT_EN_ARMV7 0x00000001 89 #define SYS_SOFT_RST_ARMV7 0x00000001 90 91 #define RSTOUTn_MASK 0x8 92 #define SOFT_RST_OUT_EN 0x00000004 93 #define SYSTEM_SOFT_RESET 0xc 94 #define SYS_SOFT_RST 0x00000001 95 #define RSTOUTn_MASK_WD 0x400 96 #define WD_RSTOUTn_MASK 0x4 97 #define WD_GLOBAL_MASK 0x00000100 98 #define WD_CPU0_MASK 0x00000001 99 #define WD_RST_OUT_EN 0x00000002 100 101 /* 102 * Power Control 103 */ 104 #define CPU_PM_CTRL 0x1C 105 #define CPU_PM_CTRL_NONE 0 106 #define CPU_PM_CTRL_ALL ~0x0 107 108 #define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 109 #define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 110 #define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 111 #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 112 #define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 113 #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 114 115 /* 116 * Timers 117 */ 118 #define CPU_TIMERS_BASE 0x300 119 #define CPU_TIMER_CONTROL 0x0 120 #define CPU_TIMER0_EN 0x00000001 121 #define CPU_TIMER0_AUTO 0x00000002 122 #define CPU_TIMER1_EN 0x00000004 123 #define CPU_TIMER1_AUTO 0x00000008 124 #define CPU_TIMER2_EN 0x00000010 125 #define CPU_TIMER2_AUTO 0x00000020 126 #define CPU_TIMER_WD_EN 0x00000100 127 #define CPU_TIMER_WD_AUTO 0x00000200 128 /* 25MHz mode is Armada XP - specific */ 129 #define CPU_TIMER_WD_25MHZ_EN 0x00000400 130 #define CPU_TIMER0_25MHZ_EN 0x00000800 131 #define CPU_TIMER1_25MHZ_EN 0x00001000 132 #define CPU_TIMER0_REL 0x10 133 #define CPU_TIMER0 0x14 134 135 /* 136 * SATA 137 */ 138 #define SATA_CHAN_NUM 2 139 140 #define EDMA_REGISTERS_OFFSET 0x2000 141 #define EDMA_REGISTERS_SIZE 0x2000 142 #define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 143 ((ch) * EDMA_REGISTERS_SIZE)) 144 145 /* SATAHC registers */ 146 #define SATA_CR 0x000 /* Configuration Reg. */ 147 #define SATA_CR_NODMABS (1 << 8) 148 #define SATA_CR_NOEDMABS (1 << 9) 149 #define SATA_CR_NOPRDPBS (1 << 10) 150 #define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 151 152 /* Interrupt Coalescing Threshold Reg. */ 153 #define SATA_ICTR 0x00C 154 #define SATA_ICTR_MAX ((1 << 8) - 1) 155 156 /* Interrupt Time Threshold Reg. */ 157 #define SATA_ITTR 0x010 158 #define SATA_ITTR_MAX ((1 << 24) - 1) 159 160 #define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 161 #define SATA_ICR_DMADONE(ch) (1 << (ch)) 162 #define SATA_ICR_COAL (1 << 4) 163 #define SATA_ICR_DEV(ch) (1 << (8 + ch)) 164 165 #define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 166 #define SATA_MICR_ERR(ch) (1 << (2 * ch)) 167 #define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 168 #define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 169 #define SATA_MICR_COAL (1 << 8) 170 171 #define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 172 173 /* Shadow registers */ 174 #define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 175 #define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 176 177 /* SATA registers */ 178 #define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 179 #define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 180 #define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 181 #define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 182 183 /* EDMA registers */ 184 #define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 185 #define SATA_EDMA_CFG_QL128 (1 << 19) 186 #define SATA_EDMA_CFG_HQCACHE (1 << 22) 187 188 #define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 189 190 #define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 191 #define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 192 #define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 193 #define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 194 #define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 195 #define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 196 #define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 197 198 #define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 199 #define SATA_EDMA_CMD_ENABLE (1 << 0) 200 #define SATA_EDMA_CMD_DISABLE (1 << 1) 201 #define SATA_EDMA_CMD_RESET (1 << 2) 202 203 #define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 204 #define SATA_EDMA_STATUS_IDLE (1 << 7) 205 206 /* Offset to extract input slot from REQIPR register */ 207 #define SATA_EDMA_REQIS_OFS 5 208 209 /* Offset to extract input slot from RESOPR register */ 210 #define SATA_EDMA_RESOS_OFS 3 211 212 /* 213 * GPIO 214 */ 215 #define GPIO_DATA_OUT 0x00 216 #define GPIO_DATA_OUT_EN_CTRL 0x04 217 #define GPIO_BLINK_EN 0x08 218 #define GPIO_DATA_IN_POLAR 0x0c 219 #define GPIO_DATA_IN 0x10 220 #define GPIO_INT_CAUSE 0x14 221 #define GPIO_INT_EDGE_MASK 0x18 222 #define GPIO_INT_LEV_MASK 0x1c 223 224 #define GPIO(n) (1 << (n)) 225 #define MV_GPIO_MAX_NPINS 64 226 227 #define MV_GPIO_IN_NONE 0x0 228 #define MV_GPIO_IN_POL_LOW (1 << 16) 229 #define MV_GPIO_IN_IRQ_EDGE (2 << 16) 230 #define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 231 #define MV_GPIO_IN_IRQ_DOUBLE_EDGE (8 << 16) 232 #define MV_GPIO_IN_DEBOUNCE (16 << 16) 233 #define MV_GPIO_OUT_NONE 0x0 234 #define MV_GPIO_OUT_BLINK 0x1 235 #define MV_GPIO_OUT_OPEN_DRAIN 0x2 236 #define MV_GPIO_OUT_OPEN_SRC 0x4 237 238 #define SAMPLE_AT_RESET_ARMADA38X 0x400 239 #define SAMPLE_AT_RESET_LO 0x30 240 #define SAMPLE_AT_RESET_HI 0x34 241 242 /* 243 * Clocks 244 */ 245 246 #define TCLK_MASK_ARMADA38X 0x00008000 247 #define TCLK_SHIFT_ARMADA38X 15 248 249 #define TCLK_100MHZ 100000000 250 #define TCLK_125MHZ 125000000 251 #define TCLK_133MHZ 133333333 252 #define TCLK_150MHZ 150000000 253 #define TCLK_166MHZ 166666667 254 #define TCLK_200MHZ 200000000 255 #define TCLK_250MHZ 250000000 256 #define TCLK_300MHZ 300000000 257 #define TCLK_667MHZ 667000000 258 259 #define A38X_CPU_DDR_CLK_MASK 0x00007c00 260 #define A38X_CPU_DDR_CLK_SHIFT 10 261 262 /* 263 * CPU Cache Configuration 264 */ 265 266 #define CPU_CONFIG 0x00000000 267 #define CPU_CONFIG_IC_PREF 0x00010000 268 #define CPU_CONFIG_DC_PREF 0x00020000 269 #define CPU_CONTROL 0x00000004 270 #define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 271 #define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 272 #define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 273 #define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 274 275 /* 276 * PCI Express port control (CPU Control registers) 277 */ 278 #define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 279 280 /* 281 * Vendor ID 282 */ 283 #define PCI_VENDORID_MRVL 0x11AB 284 #define PCI_VENDORID_MRVL2 0x1B4B 285 286 /* 287 * Chip ID 288 */ 289 #define MV_DEV_88F6828 0x6828 290 #define MV_DEV_88F6820 0x6820 291 #define MV_DEV_88F6810 0x6810 292 #define MV_DEV_MV78230 0x7823 293 #define MV_DEV_MV78260 0x7826 294 #define MV_DEV_MV78460 0x7846 295 296 #define MV_DEV_FAMILY_MASK 0xff00 297 #define MV_DEV_ARMADA38X 0x6800 298 299 /* 300 * Doorbell register control 301 */ 302 #define MV_DRBL_PCIE_TO_CPU 0 303 #define MV_DRBL_CPU_TO_PCIE 1 304 305 #define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 306 #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 307 #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 308 309 /* 310 * SCU 311 */ 312 #define MV_SCU_BASE (MV_BASE + 0xc000) 313 #define MV_SCU_REGS_LEN 0x100 314 #define MV_SCU_REG_CTRL 0x00 315 #define MV_SCU_REG_CONFIG 0x04 316 #define MV_SCU_ENABLE (1 << 0) 317 #define MV_SCU_SL_L2_ENABLE (1 << 3) 318 #define SCU_CFG_REG_NCPU_MASK 0x3 319 320 /* 321 * PMSU 322 */ 323 #define MV_PMSU_BASE (MV_BASE + 0x22000) 324 #define MV_PMSU_REGS_LEN 0x1000 325 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) 326 327 /* 328 * CPU RESET 329 */ 330 #define MV_CPU_RESET_BASE (MV_BASE + 0x20800) 331 #define MV_CPU_RESET_REGS_LEN 0x8 332 #define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) 333 #define CPU_RESET_ASSERT 0x1 334 335 #define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420) 336 #define MV_MBUS_CTRL_REGS_LEN 0x10 337 338 #endif /* _MVREG_H_ */ 339