1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 *
11 * This driver is tested for USB, SGMII, SATA and Display Port currently.
12 * PCIe should also work but that is experimental as of now.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/slab.h>
26
27 #include <dt-bindings/phy/phy.h>
28
29 /*
30 * Lane Registers
31 */
32
33 /* TX De-emphasis parameters */
34 #define L0_TX_ANA_TM_18 0x0048
35 #define L0_TX_ANA_TM_118 0x01d8
36 #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
37
38 /* DN Resistor calibration code parameters */
39 #define L0_TXPMA_ST_3 0x0b0c
40 #define L0_DN_CALIB_CODE 0x3f
41
42 /* PMA control parameters */
43 #define L0_TXPMD_TM_45 0x0cb4
44 #define L0_TXPMD_TM_48 0x0cc0
45 #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
46 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
47 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
48 #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
49 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
50 #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
51
52 /* PCS control parameters */
53 #define L0_TM_DIG_6 0x106c
54 #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
55 #define L0_TX_DIG_61 0x00f4
56 #define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
57
58 /* PLL Test Mode register parameters */
59 #define L0_TM_PLL_DIG_37 0x2094
60 #define L0_TM_COARSE_CODE_LIMIT 0x10
61
62 /* PLL SSC step size offsets */
63 #define L0_PLL_SS_STEPS_0_LSB 0x2368
64 #define L0_PLL_SS_STEPS_1_MSB 0x236c
65 #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
66 #define L0_PLL_SS_STEP_SIZE_1 0x2374
67 #define L0_PLL_SS_STEP_SIZE_2 0x2378
68 #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
69 #define L0_PLL_STATUS_READ_1 0x23e4
70
71 /* SSC step size parameters */
72 #define STEP_SIZE_0_MASK 0xff
73 #define STEP_SIZE_1_MASK 0xff
74 #define STEP_SIZE_2_MASK 0xff
75 #define STEP_SIZE_3_MASK 0x3
76 #define STEP_SIZE_SHIFT 8
77 #define FORCE_STEP_SIZE 0x10
78 #define FORCE_STEPS 0x20
79 #define STEPS_0_MASK 0xff
80 #define STEPS_1_MASK 0x07
81
82 /* Reference clock selection parameters */
83 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
84 #define L0_REF_CLK_LCL_SEL BIT(7)
85 #define L0_REF_CLK_SEL_MASK 0x9f
86
87 /* Calibration digital logic parameters */
88 #define L3_TM_CALIB_DIG19 0xec4c
89 #define L3_CALIB_DONE_STATUS 0xef14
90 #define L3_TM_CALIB_DIG18 0xec48
91 #define L3_TM_CALIB_DIG19_NSW 0x07
92 #define L3_TM_CALIB_DIG18_NSW 0xe0
93 #define L3_TM_OVERRIDE_NSW_CODE 0x20
94 #define L3_CALIB_DONE 0x02
95 #define L3_NSW_SHIFT 5
96 #define L3_NSW_PIPE_SHIFT 4
97 #define L3_NSW_CALIB_SHIFT 3
98
99 #define PHY_REG_OFFSET 0x4000
100
101 /*
102 * Global Registers
103 */
104
105 /* Refclk selection parameters */
106 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
107 #define PLL_FREQ_MASK 0x1f
108 #define PLL_STATUS_LOCKED 0x10
109
110 /* Inter Connect Matrix parameters */
111 #define ICM_CFG0 0x10010
112 #define ICM_CFG1 0x10014
113 #define ICM_CFG0_L0_MASK 0x07
114 #define ICM_CFG0_L1_MASK 0x70
115 #define ICM_CFG1_L2_MASK 0x07
116 #define ICM_CFG2_L3_MASK 0x70
117 #define ICM_CFG_SHIFT 4
118
119 /* Inter Connect Matrix allowed protocols */
120 #define ICM_PROTOCOL_PD 0x0
121 #define ICM_PROTOCOL_PCIE 0x1
122 #define ICM_PROTOCOL_SATA 0x2
123 #define ICM_PROTOCOL_USB 0x3
124 #define ICM_PROTOCOL_DP 0x4
125 #define ICM_PROTOCOL_SGMII 0x5
126
127 static const char *const xpsgtr_icm_str[] = {
128 [ICM_PROTOCOL_PD] = "none",
129 [ICM_PROTOCOL_PCIE] = "PCIe",
130 [ICM_PROTOCOL_SATA] = "SATA",
131 [ICM_PROTOCOL_USB] = "USB",
132 [ICM_PROTOCOL_DP] = "DisplayPort",
133 [ICM_PROTOCOL_SGMII] = "SGMII",
134 };
135
136 /* Test Mode common reset control parameters */
137 #define TM_CMN_RST 0x10018
138 #define TM_CMN_RST_EN 0x1
139 #define TM_CMN_RST_SET 0x2
140 #define TM_CMN_RST_MASK 0x3
141
142 /* Bus width parameters */
143 #define TX_PROT_BUS_WIDTH 0x10040
144 #define RX_PROT_BUS_WIDTH 0x10044
145 #define PROT_BUS_WIDTH_10 0x0
146 #define PROT_BUS_WIDTH_20 0x1
147 #define PROT_BUS_WIDTH_40 0x2
148 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
149 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
150
151 /* Number of GT lanes */
152 #define NUM_LANES 4
153
154 /* SIOU SATA control register */
155 #define SATA_CONTROL_OFFSET 0x0100
156
157 /* Total number of controllers */
158 #define CONTROLLERS_PER_LANE 5
159
160 /* Timeout values */
161 #define TIMEOUT_US 1000
162
163 /* Lane 0/1/2/3 offset */
164 #define DIG_8(n) ((0x4000 * (n)) + 0x1074)
165 #define ILL13(n) ((0x4000 * (n)) + 0x1994)
166 #define DIG_10(n) ((0x4000 * (n)) + 0x107c)
167 #define RST_DLY(n) ((0x4000 * (n)) + 0x19a4)
168 #define BYP_15(n) ((0x4000 * (n)) + 0x1038)
169 #define BYP_12(n) ((0x4000 * (n)) + 0x102c)
170 #define MISC3(n) ((0x4000 * (n)) + 0x19ac)
171 #define EQ11(n) ((0x4000 * (n)) + 0x1978)
172
173 static u32 save_reg_address[] = {
174 /* Lane 0/1/2/3 Register */
175 DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0),
176 DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1),
177 DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2),
178 DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3),
179 };
180
181 struct xpsgtr_dev;
182
183 /**
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * @refclk_rate: PLL reference clock frequency
186 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
188 * @step_size: step size of each step
189 */
190 struct xpsgtr_ssc {
191 u32 refclk_rate;
192 u8 pll_ref_clk;
193 u32 steps;
194 u32 step_size;
195 };
196
197 /**
198 * struct xpsgtr_phy - representation of a lane
199 * @phy: pointer to the kernel PHY device
200 * @instance: instance of the protocol type (such as the lane within a
201 * protocol, or the USB/Ethernet controller)
202 * @lane: lane number
203 * @protocol: protocol in which the lane operates
204 * @skip_phy_init: skip phy_init() if true
205 * @dev: pointer to the xpsgtr_dev instance
206 * @refclk: reference clock index
207 */
208 struct xpsgtr_phy {
209 struct phy *phy;
210 u8 instance;
211 u8 lane;
212 u8 protocol;
213 bool skip_phy_init;
214 struct xpsgtr_dev *dev;
215 unsigned int refclk;
216 };
217
218 /**
219 * struct xpsgtr_dev - representation of a ZynMP GT device
220 * @dev: pointer to device
221 * @serdes: serdes base address
222 * @siou: siou base address
223 * @gtr_mutex: mutex for locking
224 * @phys: PHY lanes
225 * @refclk_sscs: spread spectrum settings for the reference clocks
226 * @clk: reference clocks
227 * @tx_term_fix: fix for GT issue
228 * @saved_icm_cfg0: stored value of ICM CFG0 register
229 * @saved_icm_cfg1: stored value of ICM CFG1 register
230 * @saved_regs: registers to be saved/restored during suspend/resume
231 */
232 struct xpsgtr_dev {
233 struct device *dev;
234 void __iomem *serdes;
235 void __iomem *siou;
236 struct mutex gtr_mutex; /* mutex for locking */
237 struct xpsgtr_phy phys[NUM_LANES];
238 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
239 struct clk *clk[NUM_LANES];
240 bool tx_term_fix;
241 unsigned int saved_icm_cfg0;
242 unsigned int saved_icm_cfg1;
243 u32 *saved_regs;
244 };
245
246 /*
247 * Configuration Data
248 */
249
250 /* lookup table to hold all settings needed for a ref clock frequency */
251 static const struct xpsgtr_ssc ssc_lookup[] = {
252 { 19200000, 0x05, 608, 264020 },
253 { 20000000, 0x06, 634, 243454 },
254 { 24000000, 0x07, 760, 168973 },
255 { 26000000, 0x08, 824, 143860 },
256 { 27000000, 0x09, 856, 86551 },
257 { 38400000, 0x0a, 1218, 65896 },
258 { 40000000, 0x0b, 634, 243454 },
259 { 52000000, 0x0c, 824, 143860 },
260 { 100000000, 0x0d, 1058, 87533 },
261 { 108000000, 0x0e, 856, 86551 },
262 { 125000000, 0x0f, 992, 119497 },
263 { 135000000, 0x10, 1070, 55393 },
264 { 150000000, 0x11, 792, 187091 }
265 };
266
267 /*
268 * I/O Accessors
269 */
270
xpsgtr_read(struct xpsgtr_dev * gtr_dev,u32 reg)271 static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
272 {
273 return readl(gtr_dev->serdes + reg);
274 }
275
xpsgtr_write(struct xpsgtr_dev * gtr_dev,u32 reg,u32 value)276 static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
277 {
278 writel(value, gtr_dev->serdes + reg);
279 }
280
xpsgtr_clr_set(struct xpsgtr_dev * gtr_dev,u32 reg,u32 clr,u32 set)281 static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
282 u32 clr, u32 set)
283 {
284 u32 value = xpsgtr_read(gtr_dev, reg);
285
286 value &= ~clr;
287 value |= set;
288 xpsgtr_write(gtr_dev, reg, value);
289 }
290
xpsgtr_read_phy(struct xpsgtr_phy * gtr_phy,u32 reg)291 static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
292 {
293 void __iomem *addr = gtr_phy->dev->serdes
294 + gtr_phy->lane * PHY_REG_OFFSET + reg;
295
296 return readl(addr);
297 }
298
xpsgtr_write_phy(struct xpsgtr_phy * gtr_phy,u32 reg,u32 value)299 static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
300 u32 reg, u32 value)
301 {
302 void __iomem *addr = gtr_phy->dev->serdes
303 + gtr_phy->lane * PHY_REG_OFFSET + reg;
304
305 writel(value, addr);
306 }
307
xpsgtr_clr_set_phy(struct xpsgtr_phy * gtr_phy,u32 reg,u32 clr,u32 set)308 static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
309 u32 reg, u32 clr, u32 set)
310 {
311 void __iomem *addr = gtr_phy->dev->serdes
312 + gtr_phy->lane * PHY_REG_OFFSET + reg;
313
314 writel((readl(addr) & ~clr) | set, addr);
315 }
316
317 /**
318 * xpsgtr_save_lane_regs - Saves registers on suspend
319 * @gtr_dev: pointer to phy controller context structure
320 */
xpsgtr_save_lane_regs(struct xpsgtr_dev * gtr_dev)321 static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev)
322 {
323 int i;
324
325 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
326 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev,
327 save_reg_address[i]);
328 }
329
330 /**
331 * xpsgtr_restore_lane_regs - Restores registers on resume
332 * @gtr_dev: pointer to phy controller context structure
333 */
xpsgtr_restore_lane_regs(struct xpsgtr_dev * gtr_dev)334 static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev)
335 {
336 int i;
337
338 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++)
339 xpsgtr_write(gtr_dev, save_reg_address[i],
340 gtr_dev->saved_regs[i]);
341 }
342
343 /*
344 * Hardware Configuration
345 */
346
347 /* Wait for the PLL to lock (with a timeout). */
xpsgtr_wait_pll_lock(struct phy * phy)348 static int xpsgtr_wait_pll_lock(struct phy *phy)
349 {
350 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
351 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
352 unsigned int timeout = TIMEOUT_US;
353 u8 protocol = gtr_phy->protocol;
354 int ret;
355
356 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
357
358 /*
359 * For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
360 * so we wait on the right PLL.
361 */
362 if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
363 gtr_phy->instance) {
364 int i;
365
366 for (i = 0; i < NUM_LANES; i++) {
367 gtr_phy = >r_dev->phys[i];
368
369 if (gtr_phy->protocol == protocol && !gtr_phy->instance)
370 goto got_phy;
371 }
372
373 return -EBUSY;
374 }
375
376 got_phy:
377 while (1) {
378 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
379
380 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
381 ret = 0;
382 break;
383 }
384
385 if (--timeout == 0) {
386 ret = -ETIMEDOUT;
387 break;
388 }
389
390 udelay(1);
391 }
392
393 if (ret == -ETIMEDOUT)
394 dev_err(gtr_dev->dev,
395 "lane %u (protocol %u, instance %u): PLL lock timeout\n",
396 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
397
398 return ret;
399 }
400
401 /* Configure PLL and spread-sprectrum clock. */
xpsgtr_configure_pll(struct xpsgtr_phy * gtr_phy)402 static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
403 {
404 const struct xpsgtr_ssc *ssc;
405 u32 step_size;
406
407 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
408 step_size = ssc->step_size;
409
410 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
411 PLL_FREQ_MASK, ssc->pll_ref_clk);
412
413 /* Enable lane clock sharing, if required */
414 if (gtr_phy->refclk == gtr_phy->lane)
415 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
416 L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL);
417 else
418 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
419 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
420
421 /* SSC step size [7:0] */
422 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
423 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
424
425 /* SSC step size [15:8] */
426 step_size >>= STEP_SIZE_SHIFT;
427 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
428 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
429
430 /* SSC step size [23:16] */
431 step_size >>= STEP_SIZE_SHIFT;
432 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
433 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
434
435 /* SSC steps [7:0] */
436 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
437 STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
438
439 /* SSC steps [10:8] */
440 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
441 STEPS_1_MASK,
442 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
443
444 /* SSC step size [24:25] */
445 step_size >>= STEP_SIZE_SHIFT;
446 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
447 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
448 FORCE_STEP_SIZE | FORCE_STEPS);
449 }
450
451 /* Configure the lane protocol. */
xpsgtr_lane_set_protocol(struct xpsgtr_phy * gtr_phy)452 static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
453 {
454 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
455 u8 protocol = gtr_phy->protocol;
456
457 switch (gtr_phy->lane) {
458 case 0:
459 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
460 break;
461 case 1:
462 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
463 protocol << ICM_CFG_SHIFT);
464 break;
465 case 2:
466 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
467 break;
468 case 3:
469 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
470 protocol << ICM_CFG_SHIFT);
471 break;
472 default:
473 /* We already checked 0 <= lane <= 3 */
474 break;
475 }
476 }
477
478 /* Bypass (de)scrambler and 8b/10b decoder and encoder. */
xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy * gtr_phy)479 static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
480 {
481 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
482 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
483 }
484
485 /* DP-specific initialization. */
xpsgtr_phy_init_dp(struct xpsgtr_phy * gtr_phy)486 static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
487 {
488 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
489 L0_TXPMD_TM_45_OVER_DP_MAIN |
490 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
491 L0_TXPMD_TM_45_OVER_DP_POST1 |
492 L0_TXPMD_TM_45_OVER_DP_POST2 |
493 L0_TXPMD_TM_45_ENABLE_DP_POST2);
494 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
495 L0_TX_ANA_TM_118_FORCE_17_0);
496 }
497
498 /* SATA-specific initialization. */
xpsgtr_phy_init_sata(struct xpsgtr_phy * gtr_phy)499 static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
500 {
501 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
502
503 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
504
505 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
506 }
507
508 /* SGMII-specific initialization. */
xpsgtr_phy_init_sgmii(struct xpsgtr_phy * gtr_phy)509 static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
510 {
511 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
512 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
513 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
514
515 /* Set SGMII protocol TX and RX bus width to 10 bits. */
516 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
517 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
518
519 xpsgtr_bypass_scrambler_8b10b(gtr_phy);
520 }
521
522 /* Configure TX de-emphasis and margining for DP. */
xpsgtr_phy_configure_dp(struct xpsgtr_phy * gtr_phy,unsigned int pre,unsigned int voltage)523 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
524 unsigned int voltage)
525 {
526 static const u8 voltage_swing[4][4] = {
527 { 0x2a, 0x27, 0x24, 0x20 },
528 { 0x27, 0x23, 0x20, 0xff },
529 { 0x24, 0x20, 0xff, 0xff },
530 { 0xff, 0xff, 0xff, 0xff }
531 };
532 static const u8 pre_emphasis[4][4] = {
533 { 0x02, 0x02, 0x02, 0x02 },
534 { 0x01, 0x01, 0x01, 0xff },
535 { 0x00, 0x00, 0xff, 0xff },
536 { 0xff, 0xff, 0xff, 0xff }
537 };
538
539 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
540 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
541 }
542
543 /*
544 * PHY Operations
545 */
546
xpsgtr_phy_init_required(struct xpsgtr_phy * gtr_phy)547 static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
548 {
549 /*
550 * As USB may save the snapshot of the states during hibernation, doing
551 * phy_init() will put the USB controller into reset, resulting in the
552 * losing of the saved snapshot. So try to avoid phy_init() for USB
553 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
554 * shutdown during suspend or when gt lane is changed from current one)
555 */
556 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
557 return false;
558 else
559 return true;
560 }
561
562 /*
563 * There is a functional issue in the GT. The TX termination resistance can be
564 * out of spec due to a issue in the calibration logic. This is the workaround
565 * to fix it, required for XCZU9EG silicon.
566 */
xpsgtr_phy_tx_term_fix(struct xpsgtr_phy * gtr_phy)567 static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
568 {
569 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
570 u32 timeout = TIMEOUT_US;
571 u32 nsw;
572
573 /* Enabling Test Mode control for CMN Rest */
574 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
575
576 /* Set Test Mode reset */
577 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
578
579 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
580 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
581
582 /*
583 * As a part of work around sequence for PMOS calibration fix,
584 * we need to configure any lane ICM_CFG to valid protocol. This
585 * will deassert the CMN_Resetn signal.
586 */
587 xpsgtr_lane_set_protocol(gtr_phy);
588
589 /* Clear Test Mode reset */
590 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
591
592 dev_dbg(gtr_dev->dev, "calibrating...\n");
593
594 do {
595 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
596
597 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
598 break;
599
600 if (!--timeout) {
601 dev_err(gtr_dev->dev, "calibration time out\n");
602 return -ETIMEDOUT;
603 }
604
605 udelay(1);
606 } while (timeout > 0);
607
608 dev_dbg(gtr_dev->dev, "calibration done\n");
609
610 /* Reading NMOS Register Code */
611 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
612
613 /* Set Test Mode reset */
614 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
615
616 /* Writing NMOS register values back [5:3] */
617 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
618
619 /* Writing NMOS register value [2:0] */
620 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
621 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
622 (1 << L3_NSW_PIPE_SHIFT));
623
624 /* Clear Test Mode reset */
625 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
626
627 return 0;
628 }
629
xpsgtr_phy_init(struct phy * phy)630 static int xpsgtr_phy_init(struct phy *phy)
631 {
632 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
633 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
634 int ret = 0;
635
636 mutex_lock(>r_dev->gtr_mutex);
637
638 /* Configure and enable the clock when peripheral phy_init call */
639 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]))
640 goto out;
641
642 /* Skip initialization if not required. */
643 if (!xpsgtr_phy_init_required(gtr_phy))
644 goto out;
645
646 if (gtr_dev->tx_term_fix) {
647 ret = xpsgtr_phy_tx_term_fix(gtr_phy);
648 if (ret < 0)
649 goto out;
650
651 gtr_dev->tx_term_fix = false;
652 }
653
654 /* Enable coarse code saturation limiting logic. */
655 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
656
657 /*
658 * Configure the PLL, the lane protocol, and perform protocol-specific
659 * initialization.
660 */
661 xpsgtr_configure_pll(gtr_phy);
662 xpsgtr_lane_set_protocol(gtr_phy);
663
664 switch (gtr_phy->protocol) {
665 case ICM_PROTOCOL_DP:
666 xpsgtr_phy_init_dp(gtr_phy);
667 break;
668
669 case ICM_PROTOCOL_SATA:
670 xpsgtr_phy_init_sata(gtr_phy);
671 break;
672
673 case ICM_PROTOCOL_SGMII:
674 xpsgtr_phy_init_sgmii(gtr_phy);
675 break;
676 }
677
678 out:
679 mutex_unlock(>r_dev->gtr_mutex);
680 return ret;
681 }
682
xpsgtr_phy_exit(struct phy * phy)683 static int xpsgtr_phy_exit(struct phy *phy)
684 {
685 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
686 struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
687
688 gtr_phy->skip_phy_init = false;
689
690 /* Ensure that disable clock only, which configure for lane */
691 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
692
693 return 0;
694 }
695
xpsgtr_phy_power_on(struct phy * phy)696 static int xpsgtr_phy_power_on(struct phy *phy)
697 {
698 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
699 int ret = 0;
700
701 /* Skip initialization if not required. */
702 if (!xpsgtr_phy_init_required(gtr_phy))
703 return ret;
704 return xpsgtr_wait_pll_lock(phy);
705 }
706
xpsgtr_phy_configure(struct phy * phy,union phy_configure_opts * opts)707 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
708 {
709 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
710
711 if (gtr_phy->protocol != ICM_PROTOCOL_DP)
712 return 0;
713
714 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
715
716 return 0;
717 }
718
719 static const struct phy_ops xpsgtr_phyops = {
720 .init = xpsgtr_phy_init,
721 .exit = xpsgtr_phy_exit,
722 .power_on = xpsgtr_phy_power_on,
723 .configure = xpsgtr_phy_configure,
724 .owner = THIS_MODULE,
725 };
726
727 /*
728 * OF Xlate Support
729 */
730
731 /* Set the lane protocol and instance based on the PHY type and instance number. */
xpsgtr_set_lane_type(struct xpsgtr_phy * gtr_phy,u8 phy_type,unsigned int phy_instance)732 static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
733 unsigned int phy_instance)
734 {
735 unsigned int num_phy_types;
736
737 switch (phy_type) {
738 case PHY_TYPE_SATA:
739 num_phy_types = 2;
740 gtr_phy->protocol = ICM_PROTOCOL_SATA;
741 break;
742 case PHY_TYPE_USB3:
743 num_phy_types = 2;
744 gtr_phy->protocol = ICM_PROTOCOL_USB;
745 break;
746 case PHY_TYPE_DP:
747 num_phy_types = 2;
748 gtr_phy->protocol = ICM_PROTOCOL_DP;
749 break;
750 case PHY_TYPE_PCIE:
751 num_phy_types = 4;
752 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
753 break;
754 case PHY_TYPE_SGMII:
755 num_phy_types = 4;
756 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
757 break;
758 default:
759 return -EINVAL;
760 }
761
762 if (phy_instance >= num_phy_types)
763 return -EINVAL;
764
765 gtr_phy->instance = phy_instance;
766 return 0;
767 }
768
769 /*
770 * Valid combinations of controllers and lanes (Interconnect Matrix). Each
771 * "instance" represents one controller for a lane. For PCIe and DP, the
772 * "instance" is the logical lane in the link. For SATA, USB, and SGMII,
773 * the instance is the index of the controller.
774 *
775 * This information is only used to validate the devicetree reference, and is
776 * not used when programming the hardware.
777 */
778 static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
779 /* PCIe, SATA, USB, DP, SGMII */
780 { 0, 0, 0, 1, 0 }, /* Lane 0 */
781 { 1, 1, 0, 0, 1 }, /* Lane 1 */
782 { 2, 0, 0, 1, 2 }, /* Lane 2 */
783 { 3, 1, 1, 0, 3 }, /* Lane 3 */
784 };
785
786 /* Translate OF phandle and args to PHY instance. */
xpsgtr_xlate(struct device * dev,const struct of_phandle_args * args)787 static struct phy *xpsgtr_xlate(struct device *dev,
788 const struct of_phandle_args *args)
789 {
790 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
791 struct xpsgtr_phy *gtr_phy;
792 unsigned int phy_instance;
793 unsigned int phy_lane;
794 unsigned int phy_type;
795 unsigned int refclk;
796 unsigned int i;
797 int ret;
798
799 if (args->args_count != 4) {
800 dev_err(dev, "Invalid number of cells in 'phy' property\n");
801 return ERR_PTR(-EINVAL);
802 }
803
804 /*
805 * Get the PHY parameters from the OF arguments and derive the lane
806 * type.
807 */
808 phy_lane = args->args[0];
809 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
810 dev_err(dev, "Invalid lane number %u\n", phy_lane);
811 return ERR_PTR(-ENODEV);
812 }
813
814 gtr_phy = >r_dev->phys[phy_lane];
815 phy_type = args->args[1];
816 phy_instance = args->args[2];
817
818 guard(mutex)(>r_phy->phy->mutex);
819 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
820 if (ret < 0) {
821 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
822 return ERR_PTR(ret);
823 }
824
825 refclk = args->args[3];
826 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
827 !gtr_dev->refclk_sscs[refclk]) {
828 dev_err(dev, "Invalid reference clock number %u\n", refclk);
829 return ERR_PTR(-EINVAL);
830 }
831
832 gtr_phy->refclk = refclk;
833
834 /*
835 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
836 * is allowed to operate on the lane.
837 */
838 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
839 if (icm_matrix[phy_lane][i] == gtr_phy->instance)
840 return gtr_phy->phy;
841 }
842
843 return ERR_PTR(-EINVAL);
844 }
845
846 /*
847 * DebugFS
848 */
849
xpsgtr_status_read(struct seq_file * seq,void * data)850 static int xpsgtr_status_read(struct seq_file *seq, void *data)
851 {
852 struct device *dev = seq->private;
853 struct xpsgtr_phy *gtr_phy = dev_get_drvdata(dev);
854 struct clk *clk;
855 u32 pll_status;
856
857 mutex_lock(>r_phy->phy->mutex);
858 pll_status = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
859 clk = gtr_phy->dev->clk[gtr_phy->refclk];
860
861 seq_printf(seq, "Lane: %u\n", gtr_phy->lane);
862 seq_printf(seq, "Protocol: %s\n",
863 xpsgtr_icm_str[gtr_phy->protocol]);
864 seq_printf(seq, "Instance: %u\n", gtr_phy->instance);
865 seq_printf(seq, "Reference clock: %u (%pC)\n", gtr_phy->refclk, clk);
866 seq_printf(seq, "Reference rate: %lu\n", clk_get_rate(clk));
867 seq_printf(seq, "PLL locked: %s\n",
868 pll_status & PLL_STATUS_LOCKED ? "yes" : "no");
869
870 mutex_unlock(>r_phy->phy->mutex);
871 return 0;
872 }
873
874 /*
875 * Power Management
876 */
877
xpsgtr_runtime_suspend(struct device * dev)878 static int xpsgtr_runtime_suspend(struct device *dev)
879 {
880 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
881
882 /* Save the snapshot ICM_CFG registers. */
883 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
884 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
885
886 xpsgtr_save_lane_regs(gtr_dev);
887
888 return 0;
889 }
890
xpsgtr_runtime_resume(struct device * dev)891 static int xpsgtr_runtime_resume(struct device *dev)
892 {
893 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
894 unsigned int icm_cfg0, icm_cfg1;
895 unsigned int i;
896 bool skip_phy_init;
897
898 xpsgtr_restore_lane_regs(gtr_dev);
899
900 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
901 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
902
903 /* Return if no GT lanes got configured before suspend. */
904 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
905 return 0;
906
907 /* Check if the ICM configurations changed after suspend. */
908 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
909 icm_cfg1 == gtr_dev->saved_icm_cfg1)
910 skip_phy_init = true;
911 else
912 skip_phy_init = false;
913
914 /* Update the skip_phy_init for all gtr_phy instances. */
915 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
916 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
917
918 return 0;
919 }
920
921 static DEFINE_RUNTIME_DEV_PM_OPS(xpsgtr_pm_ops, xpsgtr_runtime_suspend,
922 xpsgtr_runtime_resume, NULL);
923 /*
924 * Probe & Platform Driver
925 */
926
xpsgtr_get_ref_clocks(struct xpsgtr_dev * gtr_dev)927 static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
928 {
929 unsigned int refclk;
930
931 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
932 unsigned long rate;
933 unsigned int i;
934 struct clk *clk;
935 char name[8];
936
937 snprintf(name, sizeof(name), "ref%u", refclk);
938 clk = devm_clk_get_optional(gtr_dev->dev, name);
939 if (IS_ERR(clk)) {
940 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
941 "Failed to get ref clock %u\n",
942 refclk);
943 }
944
945 if (!clk)
946 continue;
947
948 gtr_dev->clk[refclk] = clk;
949
950 /*
951 * Get the spread spectrum (SSC) settings for the reference
952 * clock rate.
953 */
954 rate = clk_get_rate(clk);
955
956 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
957 /* Allow an error of 100 ppm */
958 unsigned long error = ssc_lookup[i].refclk_rate / 10000;
959
960 if (abs(rate - ssc_lookup[i].refclk_rate) < error) {
961 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
962 break;
963 }
964 }
965
966 if (i == ARRAY_SIZE(ssc_lookup)) {
967 dev_err(gtr_dev->dev,
968 "Invalid rate %lu for reference clock %u\n",
969 rate, refclk);
970 return -EINVAL;
971 }
972 }
973
974 return 0;
975 }
976
xpsgtr_probe(struct platform_device * pdev)977 static int xpsgtr_probe(struct platform_device *pdev)
978 {
979 struct device_node *np = pdev->dev.of_node;
980 struct xpsgtr_dev *gtr_dev;
981 struct phy_provider *provider;
982 unsigned int port;
983 int ret;
984
985 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
986 if (!gtr_dev)
987 return -ENOMEM;
988
989 gtr_dev->dev = &pdev->dev;
990 platform_set_drvdata(pdev, gtr_dev);
991
992 mutex_init(>r_dev->gtr_mutex);
993
994 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
995 gtr_dev->tx_term_fix =
996 of_property_read_bool(np, "xlnx,tx-termination-fix");
997
998 /* Acquire resources. */
999 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
1000 if (IS_ERR(gtr_dev->serdes))
1001 return PTR_ERR(gtr_dev->serdes);
1002
1003 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
1004 if (IS_ERR(gtr_dev->siou))
1005 return PTR_ERR(gtr_dev->siou);
1006
1007 ret = xpsgtr_get_ref_clocks(gtr_dev);
1008 if (ret)
1009 return ret;
1010
1011 /* Create PHYs. */
1012 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
1013 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port];
1014 struct phy *phy;
1015
1016 gtr_phy->lane = port;
1017 gtr_phy->dev = gtr_dev;
1018
1019 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
1020 if (IS_ERR(phy)) {
1021 dev_err(&pdev->dev, "failed to create PHY\n");
1022 return PTR_ERR(phy);
1023 }
1024
1025 gtr_phy->phy = phy;
1026 phy_set_drvdata(phy, gtr_phy);
1027 debugfs_create_devm_seqfile(&phy->dev, "status", phy->debugfs,
1028 xpsgtr_status_read);
1029 }
1030
1031 /* Register the PHY provider. */
1032 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
1033 if (IS_ERR(provider)) {
1034 dev_err(&pdev->dev, "registering provider failed\n");
1035 return PTR_ERR(provider);
1036 }
1037
1038 pm_runtime_set_active(gtr_dev->dev);
1039 pm_runtime_enable(gtr_dev->dev);
1040
1041 ret = pm_runtime_resume_and_get(gtr_dev->dev);
1042 if (ret < 0) {
1043 pm_runtime_disable(gtr_dev->dev);
1044 return ret;
1045 }
1046
1047 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev,
1048 sizeof(save_reg_address),
1049 GFP_KERNEL);
1050 if (!gtr_dev->saved_regs)
1051 return -ENOMEM;
1052
1053 return 0;
1054 }
1055
xpsgtr_remove(struct platform_device * pdev)1056 static void xpsgtr_remove(struct platform_device *pdev)
1057 {
1058 struct xpsgtr_dev *gtr_dev = platform_get_drvdata(pdev);
1059
1060 pm_runtime_disable(gtr_dev->dev);
1061 pm_runtime_put_noidle(gtr_dev->dev);
1062 pm_runtime_set_suspended(gtr_dev->dev);
1063 }
1064
1065 static const struct of_device_id xpsgtr_of_match[] = {
1066 { .compatible = "xlnx,zynqmp-psgtr", },
1067 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1068 {},
1069 };
1070 MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
1071
1072 static struct platform_driver xpsgtr_driver = {
1073 .probe = xpsgtr_probe,
1074 .remove_new = xpsgtr_remove,
1075 .driver = {
1076 .name = "xilinx-psgtr",
1077 .of_match_table = xpsgtr_of_match,
1078 .pm = pm_ptr(&xpsgtr_pm_ops),
1079 },
1080 };
1081
1082 module_platform_driver(xpsgtr_driver);
1083
1084 MODULE_AUTHOR("Xilinx Inc.");
1085 MODULE_LICENSE("GPL v2");
1086 MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");
1087