1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sata_mv.c - Marvell SATA support 4 * 5 * Copyright 2008-2009: Marvell Corporation, all rights reserved. 6 * Copyright 2005: EMC Corporation, all rights reserved. 7 * Copyright 2005 Red Hat, Inc. All rights reserved. 8 * 9 * Originally written by Brett Russ. 10 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 11 * 12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 13 */ 14 15 /* 16 * sata_mv TODO list: 17 * 18 * --> Develop a low-power-consumption strategy, and implement it. 19 * 20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 21 * 22 * --> [Experiment, Marvell value added] Is it possible to use target 23 * mode to cross-connect two Linux boxes with Marvell cards? If so, 24 * creating LibATA target mode support would be very interesting. 25 * 26 * Target mode, for those without docs, is the ability to directly 27 * connect two SATA ports. 28 */ 29 30 /* 31 * 80x1-B2 errata PCI#11: 32 * 33 * Users of the 6041/6081 Rev.B2 chips (current is C0) 34 * should be careful to insert those cards only onto PCI-X bus #0, 35 * and only in device slots 0..7, not higher. The chips may not 36 * work correctly otherwise (note: this is a pretty rare condition). 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/pci.h> 42 #include <linux/init.h> 43 #include <linux/blkdev.h> 44 #include <linux/delay.h> 45 #include <linux/interrupt.h> 46 #include <linux/dmapool.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/device.h> 49 #include <linux/clk.h> 50 #include <linux/phy/phy.h> 51 #include <linux/platform_device.h> 52 #include <linux/ata_platform.h> 53 #include <linux/mbus.h> 54 #include <linux/bitops.h> 55 #include <linux/gfp.h> 56 #include <linux/of.h> 57 #include <linux/of_irq.h> 58 #include <scsi/scsi_host.h> 59 #include <scsi/scsi_cmnd.h> 60 #include <scsi/scsi_device.h> 61 #include <linux/libata.h> 62 63 #define DRV_NAME "sata_mv" 64 #define DRV_VERSION "1.28" 65 66 /* 67 * module options 68 */ 69 70 #ifdef CONFIG_PCI 71 static int msi; 72 module_param(msi, int, S_IRUGO); 73 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 74 #endif 75 76 static int irq_coalescing_io_count; 77 module_param(irq_coalescing_io_count, int, S_IRUGO); 78 MODULE_PARM_DESC(irq_coalescing_io_count, 79 "IRQ coalescing I/O count threshold (0..255)"); 80 81 static int irq_coalescing_usecs; 82 module_param(irq_coalescing_usecs, int, S_IRUGO); 83 MODULE_PARM_DESC(irq_coalescing_usecs, 84 "IRQ coalescing time threshold in usecs"); 85 86 enum { 87 /* BAR's are enumerated in terms of pci_resource_start() terms */ 88 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 89 MV_IO_BAR = 2, /* offset 0x18: IO space */ 90 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 91 92 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 93 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 94 95 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 96 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 97 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 98 MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 99 100 MV_PCI_REG_BASE = 0, 101 102 /* 103 * Per-chip ("all ports") interrupt coalescing feature. 104 * This is only for GEN_II / GEN_IIE hardware. 105 * 106 * Coalescing defers the interrupt until either the IO_THRESHOLD 107 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 108 */ 109 COAL_REG_BASE = 0x18000, 110 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 111 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 112 113 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 114 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 115 116 /* 117 * Registers for the (unused here) transaction coalescing feature: 118 */ 119 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 120 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 121 122 SATAHC0_REG_BASE = 0x20000, 123 FLASH_CTL = 0x1046c, 124 GPIO_PORT_CTL = 0x104f0, 125 RESET_CFG = 0x180d8, 126 127 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 128 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 129 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 130 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 131 132 MV_MAX_Q_DEPTH = 32, 133 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 134 135 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 136 * CRPB needs alignment on a 256B boundary. Size == 256B 137 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 138 */ 139 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 140 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 141 MV_MAX_SG_CT = 256, 142 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 143 144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 145 MV_PORT_HC_SHIFT = 2, 146 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 148 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 149 150 /* Host Flags */ 151 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 152 153 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING, 154 155 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 156 157 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 158 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 159 160 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 161 162 CRQB_FLAG_READ = (1 << 0), 163 CRQB_TAG_SHIFT = 1, 164 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 165 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 166 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 167 CRQB_CMD_ADDR_SHIFT = 8, 168 CRQB_CMD_CS = (0x2 << 11), 169 CRQB_CMD_LAST = (1 << 15), 170 171 CRPB_FLAG_STATUS_SHIFT = 8, 172 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 173 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 174 175 EPRD_FLAG_END_OF_TBL = (1 << 31), 176 177 /* PCI interface registers */ 178 179 MV_PCI_COMMAND = 0xc00, 180 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 181 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 182 183 PCI_MAIN_CMD_STS = 0xd30, 184 STOP_PCI_MASTER = (1 << 2), 185 PCI_MASTER_EMPTY = (1 << 3), 186 GLOB_SFT_RST = (1 << 4), 187 188 MV_PCI_MODE = 0xd00, 189 MV_PCI_MODE_MASK = 0x30, 190 191 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 192 MV_PCI_DISC_TIMER = 0xd04, 193 MV_PCI_MSI_TRIGGER = 0xc38, 194 MV_PCI_SERR_MASK = 0xc28, 195 MV_PCI_XBAR_TMOUT = 0x1d04, 196 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 197 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 198 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 199 MV_PCI_ERR_COMMAND = 0x1d50, 200 201 PCI_IRQ_CAUSE = 0x1d58, 202 PCI_IRQ_MASK = 0x1d5c, 203 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 204 205 PCIE_IRQ_CAUSE = 0x1900, 206 PCIE_IRQ_MASK = 0x1910, 207 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 208 209 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 210 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 211 PCI_HC_MAIN_IRQ_MASK = 0x1d64, 212 SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 213 SOC_HC_MAIN_IRQ_MASK = 0x20024, 214 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 215 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 216 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 217 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 218 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 219 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 220 PCI_ERR = (1 << 18), 221 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 222 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 223 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 224 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 225 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 226 GPIO_INT = (1 << 22), 227 SELF_INT = (1 << 23), 228 TWSI_INT = (1 << 24), 229 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 230 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 231 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 232 233 /* SATAHC registers */ 234 HC_CFG = 0x00, 235 236 HC_IRQ_CAUSE = 0x14, 237 DMA_IRQ = (1 << 0), /* shift by port # */ 238 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 239 DEV_IRQ = (1 << 8), /* shift by port # */ 240 241 /* 242 * Per-HC (Host-Controller) interrupt coalescing feature. 243 * This is present on all chip generations. 244 * 245 * Coalescing defers the interrupt until either the IO_THRESHOLD 246 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 247 */ 248 HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 249 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 250 251 SOC_LED_CTRL = 0x2c, 252 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 253 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 254 /* with dev activity LED */ 255 SOC_LED_CTRL_ENABLE = (1 << 3), /* Enable SATA LED control */ 256 257 /* Shadow block registers */ 258 SHD_BLK = 0x100, 259 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 260 261 /* SATA registers */ 262 SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 263 SATA_ACTIVE = 0x350, 264 FIS_IRQ_CAUSE = 0x364, 265 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 266 267 LTMODE = 0x30c, /* requires read-after-write */ 268 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 269 270 PHY_MODE2 = 0x330, 271 PHY_MODE3 = 0x310, 272 273 PHY_MODE4 = 0x314, /* requires read-after-write */ 274 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 275 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 276 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 277 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 278 279 SATA_IFCTL = 0x344, 280 SATA_TESTCTL = 0x348, 281 SATA_IFSTAT = 0x34c, 282 VENDOR_UNIQUE_FIS = 0x35c, 283 284 FISCFG = 0x360, 285 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 286 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 287 288 PHY_MODE9_GEN2 = 0x398, 289 PHY_MODE9_GEN1 = 0x39c, 290 PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 291 292 MV5_PHY_MODE = 0x74, 293 MV5_LTMODE = 0x30, 294 MV5_PHY_CTL = 0x0C, 295 SATA_IFCFG = 0x050, 296 LP_PHY_CTL = 0x058, 297 LP_PHY_CTL_PIN_PU_PLL = (1 << 0), 298 LP_PHY_CTL_PIN_PU_RX = (1 << 1), 299 LP_PHY_CTL_PIN_PU_TX = (1 << 2), 300 LP_PHY_CTL_GEN_TX_3G = (1 << 5), 301 LP_PHY_CTL_GEN_RX_3G = (1 << 9), 302 303 MV_M2_PREAMP_MASK = 0x7e0, 304 305 /* Port registers */ 306 EDMA_CFG = 0, 307 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 308 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 309 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 310 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 311 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 312 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 313 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 314 315 EDMA_ERR_IRQ_CAUSE = 0x8, 316 EDMA_ERR_IRQ_MASK = 0xc, 317 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 318 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 319 EDMA_ERR_DEV = (1 << 2), /* device error */ 320 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 321 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 322 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 323 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 324 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 325 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 326 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 327 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 328 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 329 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 330 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 331 332 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 333 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 334 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 335 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 336 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 337 338 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 339 340 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 341 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 342 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 343 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 344 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 345 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 346 347 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 348 349 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 350 EDMA_ERR_OVERRUN_5 = (1 << 5), 351 EDMA_ERR_UNDERRUN_5 = (1 << 6), 352 353 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 354 EDMA_ERR_LNK_CTRL_RX_1 | 355 EDMA_ERR_LNK_CTRL_RX_3 | 356 EDMA_ERR_LNK_CTRL_TX, 357 358 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 359 EDMA_ERR_PRD_PAR | 360 EDMA_ERR_DEV_DCON | 361 EDMA_ERR_DEV_CON | 362 EDMA_ERR_SERR | 363 EDMA_ERR_SELF_DIS | 364 EDMA_ERR_CRQB_PAR | 365 EDMA_ERR_CRPB_PAR | 366 EDMA_ERR_INTRL_PAR | 367 EDMA_ERR_IORDY | 368 EDMA_ERR_LNK_CTRL_RX_2 | 369 EDMA_ERR_LNK_DATA_RX | 370 EDMA_ERR_LNK_DATA_TX | 371 EDMA_ERR_TRANS_PROTO, 372 373 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 374 EDMA_ERR_PRD_PAR | 375 EDMA_ERR_DEV_DCON | 376 EDMA_ERR_DEV_CON | 377 EDMA_ERR_OVERRUN_5 | 378 EDMA_ERR_UNDERRUN_5 | 379 EDMA_ERR_SELF_DIS_5 | 380 EDMA_ERR_CRQB_PAR | 381 EDMA_ERR_CRPB_PAR | 382 EDMA_ERR_INTRL_PAR | 383 EDMA_ERR_IORDY, 384 385 EDMA_REQ_Q_BASE_HI = 0x10, 386 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 387 388 EDMA_REQ_Q_OUT_PTR = 0x18, 389 EDMA_REQ_Q_PTR_SHIFT = 5, 390 391 EDMA_RSP_Q_BASE_HI = 0x1c, 392 EDMA_RSP_Q_IN_PTR = 0x20, 393 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 394 EDMA_RSP_Q_PTR_SHIFT = 3, 395 396 EDMA_CMD = 0x28, /* EDMA command register */ 397 EDMA_EN = (1 << 0), /* enable EDMA */ 398 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 399 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 400 401 EDMA_STATUS = 0x30, /* EDMA engine status */ 402 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 403 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 404 405 EDMA_IORDY_TMOUT = 0x34, 406 EDMA_ARB_CFG = 0x38, 407 408 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 409 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 410 411 BMDMA_CMD = 0x224, /* bmdma command register */ 412 BMDMA_STATUS = 0x228, /* bmdma status register */ 413 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 414 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 415 416 /* Host private flags (hp_flags) */ 417 MV_HP_FLAG_MSI = (1 << 0), 418 MV_HP_ERRATA_50XXB0 = (1 << 1), 419 MV_HP_ERRATA_50XXB2 = (1 << 2), 420 MV_HP_ERRATA_60X1B2 = (1 << 3), 421 MV_HP_ERRATA_60X1C0 = (1 << 4), 422 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 423 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 424 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 425 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 426 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 427 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 428 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 429 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */ 430 431 /* Port private flags (pp_flags) */ 432 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 433 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 434 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 435 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 436 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 437 }; 438 439 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 440 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 441 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 442 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 443 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 444 445 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 446 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 447 448 enum { 449 /* DMA boundary 0xffff is required by the s/g splitting 450 * we need on /length/ in mv_fill-sg(). 451 */ 452 MV_DMA_BOUNDARY = 0xffffU, 453 454 /* mask of register bits containing lower 32 bits 455 * of EDMA request queue DMA address 456 */ 457 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 458 459 /* ditto, for response queue */ 460 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 461 }; 462 463 enum chip_type { 464 chip_504x, 465 chip_508x, 466 chip_5080, 467 chip_604x, 468 chip_608x, 469 chip_6042, 470 chip_7042, 471 chip_soc, 472 }; 473 474 /* Command ReQuest Block: 32B */ 475 struct mv_crqb { 476 __le32 sg_addr; 477 __le32 sg_addr_hi; 478 __le16 ctrl_flags; 479 __le16 ata_cmd[11]; 480 }; 481 482 struct mv_crqb_iie { 483 __le32 addr; 484 __le32 addr_hi; 485 __le32 flags; 486 __le32 len; 487 __le32 ata_cmd[4]; 488 }; 489 490 /* Command ResPonse Block: 8B */ 491 struct mv_crpb { 492 __le16 id; 493 __le16 flags; 494 __le32 tmstmp; 495 }; 496 497 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 498 struct mv_sg { 499 __le32 addr; 500 __le32 flags_size; 501 __le32 addr_hi; 502 __le32 reserved; 503 }; 504 505 /* 506 * We keep a local cache of a few frequently accessed port 507 * registers here, to avoid having to read them (very slow) 508 * when switching between EDMA and non-EDMA modes. 509 */ 510 struct mv_cached_regs { 511 u32 fiscfg; 512 u32 ltmode; 513 u32 haltcond; 514 u32 unknown_rsvd; 515 }; 516 517 struct mv_port_priv { 518 struct mv_crqb *crqb; 519 dma_addr_t crqb_dma; 520 struct mv_crpb *crpb; 521 dma_addr_t crpb_dma; 522 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 523 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 524 525 unsigned int req_idx; 526 unsigned int resp_idx; 527 528 u32 pp_flags; 529 struct mv_cached_regs cached; 530 unsigned int delayed_eh_pmp_map; 531 }; 532 533 struct mv_port_signal { 534 u32 amps; 535 u32 pre; 536 }; 537 538 struct mv_host_priv { 539 u32 hp_flags; 540 unsigned int board_idx; 541 u32 main_irq_mask; 542 struct mv_port_signal signal[8]; 543 const struct mv_hw_ops *ops; 544 int n_ports; 545 void __iomem *base; 546 void __iomem *main_irq_cause_addr; 547 void __iomem *main_irq_mask_addr; 548 u32 irq_cause_offset; 549 u32 irq_mask_offset; 550 u32 unmask_all_irqs; 551 552 /* 553 * Needed on some devices that require their clocks to be enabled. 554 * These are optional: if the platform device does not have any 555 * clocks, they won't be used. Also, if the underlying hardware 556 * does not support the common clock framework (CONFIG_HAVE_CLK=n), 557 * all the clock operations become no-ops (see clk.h). 558 */ 559 struct clk *clk; 560 struct clk **port_clks; 561 /* 562 * Some devices have a SATA PHY which can be enabled/disabled 563 * in order to save power. These are optional: if the platform 564 * devices does not have any phy, they won't be used. 565 */ 566 struct phy **port_phys; 567 /* 568 * These consistent DMA memory pools give us guaranteed 569 * alignment for hardware-accessed data structures, 570 * and less memory waste in accomplishing the alignment. 571 */ 572 struct dma_pool *crqb_pool; 573 struct dma_pool *crpb_pool; 574 struct dma_pool *sg_tbl_pool; 575 }; 576 577 struct mv_hw_ops { 578 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 579 unsigned int port); 580 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 581 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 582 void __iomem *mmio); 583 int (*reset_hc)(struct ata_host *host, void __iomem *mmio, 584 unsigned int n_hc); 585 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 586 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 587 }; 588 589 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 590 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 591 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 592 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 593 static int mv_port_start(struct ata_port *ap); 594 static void mv_port_stop(struct ata_port *ap); 595 static int mv_qc_defer(struct ata_queued_cmd *qc); 596 static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc); 597 static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc); 598 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 599 static int mv_hardreset(struct ata_link *link, unsigned int *class, 600 unsigned long deadline); 601 static void mv_eh_freeze(struct ata_port *ap); 602 static void mv_eh_thaw(struct ata_port *ap); 603 static void mv6_dev_config(struct ata_device *dev); 604 605 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 606 unsigned int port); 607 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 608 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 609 void __iomem *mmio); 610 static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio, 611 unsigned int n_hc); 612 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 613 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 614 615 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 616 unsigned int port); 617 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 618 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 619 void __iomem *mmio); 620 static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio, 621 unsigned int n_hc); 622 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 623 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 624 void __iomem *mmio); 625 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 626 void __iomem *mmio); 627 static int mv_soc_reset_hc(struct ata_host *host, 628 void __iomem *mmio, unsigned int n_hc); 629 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 630 void __iomem *mmio); 631 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 632 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 633 void __iomem *mmio, unsigned int port); 634 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 635 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 636 unsigned int port_no); 637 static int mv_stop_edma(struct ata_port *ap); 638 static int mv_stop_edma_engine(void __iomem *port_mmio); 639 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 640 641 static void mv_pmp_select(struct ata_port *ap, int pmp); 642 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 643 unsigned long deadline); 644 static int mv_softreset(struct ata_link *link, unsigned int *class, 645 unsigned long deadline); 646 static void mv_pmp_error_handler(struct ata_port *ap); 647 static void mv_process_crpb_entries(struct ata_port *ap, 648 struct mv_port_priv *pp); 649 650 static void mv_sff_irq_clear(struct ata_port *ap); 651 static int mv_check_atapi_dma(struct ata_queued_cmd *qc); 652 static void mv_bmdma_setup(struct ata_queued_cmd *qc); 653 static void mv_bmdma_start(struct ata_queued_cmd *qc); 654 static void mv_bmdma_stop(struct ata_queued_cmd *qc); 655 static u8 mv_bmdma_status(struct ata_port *ap); 656 static u8 mv_sff_check_status(struct ata_port *ap); 657 658 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 659 * because we have to allow room for worst case splitting of 660 * PRDs for 64K boundaries in mv_fill_sg(). 661 */ 662 #ifdef CONFIG_PCI 663 static const struct scsi_host_template mv5_sht = { 664 ATA_BASE_SHT(DRV_NAME), 665 .sg_tablesize = MV_MAX_SG_CT / 2, 666 .dma_boundary = MV_DMA_BOUNDARY, 667 }; 668 #endif 669 static const struct scsi_host_template mv6_sht = { 670 __ATA_BASE_SHT(DRV_NAME), 671 .can_queue = MV_MAX_Q_DEPTH - 1, 672 .sg_tablesize = MV_MAX_SG_CT / 2, 673 .dma_boundary = MV_DMA_BOUNDARY, 674 .sdev_groups = ata_ncq_sdev_groups, 675 .change_queue_depth = ata_scsi_change_queue_depth, 676 .tag_alloc_policy_rr = true, 677 .sdev_configure = ata_scsi_sdev_configure 678 }; 679 680 static struct ata_port_operations mv5_ops = { 681 .inherits = &ata_sff_port_ops, 682 683 .lost_interrupt = ATA_OP_NULL, 684 685 .qc_defer = mv_qc_defer, 686 .qc_prep = mv_qc_prep, 687 .qc_issue = mv_qc_issue, 688 689 .freeze = mv_eh_freeze, 690 .thaw = mv_eh_thaw, 691 .reset.hardreset = mv_hardreset, 692 693 .scr_read = mv5_scr_read, 694 .scr_write = mv5_scr_write, 695 696 .port_start = mv_port_start, 697 .port_stop = mv_port_stop, 698 }; 699 700 static struct ata_port_operations mv6_ops = { 701 .inherits = &ata_bmdma_port_ops, 702 703 .lost_interrupt = ATA_OP_NULL, 704 705 .qc_defer = mv_qc_defer, 706 .qc_prep = mv_qc_prep, 707 .qc_issue = mv_qc_issue, 708 709 .dev_config = mv6_dev_config, 710 711 .freeze = mv_eh_freeze, 712 .thaw = mv_eh_thaw, 713 .reset.hardreset = mv_hardreset, 714 .reset.softreset = mv_softreset, 715 .pmp_reset.hardreset = mv_pmp_hardreset, 716 .pmp_reset.softreset = mv_softreset, 717 .error_handler = mv_pmp_error_handler, 718 719 .scr_read = mv_scr_read, 720 .scr_write = mv_scr_write, 721 722 .sff_check_status = mv_sff_check_status, 723 .sff_irq_clear = mv_sff_irq_clear, 724 .check_atapi_dma = mv_check_atapi_dma, 725 .bmdma_setup = mv_bmdma_setup, 726 .bmdma_start = mv_bmdma_start, 727 .bmdma_stop = mv_bmdma_stop, 728 .bmdma_status = mv_bmdma_status, 729 730 .port_start = mv_port_start, 731 .port_stop = mv_port_stop, 732 }; 733 734 static struct ata_port_operations mv_iie_ops = { 735 .inherits = &mv6_ops, 736 .dev_config = ATA_OP_NULL, 737 .qc_prep = mv_qc_prep_iie, 738 }; 739 740 static const struct ata_port_info mv_port_info[] = { 741 { /* chip_504x */ 742 .flags = MV_GEN_I_FLAGS, 743 .pio_mask = ATA_PIO4, 744 .udma_mask = ATA_UDMA6, 745 .port_ops = &mv5_ops, 746 }, 747 { /* chip_508x */ 748 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 749 .pio_mask = ATA_PIO4, 750 .udma_mask = ATA_UDMA6, 751 .port_ops = &mv5_ops, 752 }, 753 { /* chip_5080 */ 754 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 755 .pio_mask = ATA_PIO4, 756 .udma_mask = ATA_UDMA6, 757 .port_ops = &mv5_ops, 758 }, 759 { /* chip_604x */ 760 .flags = MV_GEN_II_FLAGS, 761 .pio_mask = ATA_PIO4, 762 .udma_mask = ATA_UDMA6, 763 .port_ops = &mv6_ops, 764 }, 765 { /* chip_608x */ 766 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 767 .pio_mask = ATA_PIO4, 768 .udma_mask = ATA_UDMA6, 769 .port_ops = &mv6_ops, 770 }, 771 { /* chip_6042 */ 772 .flags = MV_GEN_IIE_FLAGS, 773 .pio_mask = ATA_PIO4, 774 .udma_mask = ATA_UDMA6, 775 .port_ops = &mv_iie_ops, 776 }, 777 { /* chip_7042 */ 778 .flags = MV_GEN_IIE_FLAGS, 779 .pio_mask = ATA_PIO4, 780 .udma_mask = ATA_UDMA6, 781 .port_ops = &mv_iie_ops, 782 }, 783 { /* chip_soc */ 784 .flags = MV_GEN_IIE_FLAGS, 785 .pio_mask = ATA_PIO4, 786 .udma_mask = ATA_UDMA6, 787 .port_ops = &mv_iie_ops, 788 }, 789 }; 790 791 static const struct mv_hw_ops mv5xxx_ops = { 792 .phy_errata = mv5_phy_errata, 793 .enable_leds = mv5_enable_leds, 794 .read_preamp = mv5_read_preamp, 795 .reset_hc = mv5_reset_hc, 796 .reset_flash = mv5_reset_flash, 797 .reset_bus = mv5_reset_bus, 798 }; 799 800 static const struct mv_hw_ops mv6xxx_ops = { 801 .phy_errata = mv6_phy_errata, 802 .enable_leds = mv6_enable_leds, 803 .read_preamp = mv6_read_preamp, 804 .reset_hc = mv6_reset_hc, 805 .reset_flash = mv6_reset_flash, 806 .reset_bus = mv_reset_pci_bus, 807 }; 808 809 static const struct mv_hw_ops mv_soc_ops = { 810 .phy_errata = mv6_phy_errata, 811 .enable_leds = mv_soc_enable_leds, 812 .read_preamp = mv_soc_read_preamp, 813 .reset_hc = mv_soc_reset_hc, 814 .reset_flash = mv_soc_reset_flash, 815 .reset_bus = mv_soc_reset_bus, 816 }; 817 818 static const struct mv_hw_ops mv_soc_65n_ops = { 819 .phy_errata = mv_soc_65n_phy_errata, 820 .enable_leds = mv_soc_enable_leds, 821 .reset_hc = mv_soc_reset_hc, 822 .reset_flash = mv_soc_reset_flash, 823 .reset_bus = mv_soc_reset_bus, 824 }; 825 826 /* 827 * Functions 828 */ 829 830 static inline void writelfl(unsigned long data, void __iomem *addr) 831 { 832 writel(data, addr); 833 (void) readl(addr); /* flush to avoid PCI posted write */ 834 } 835 836 static inline unsigned int mv_hc_from_port(unsigned int port) 837 { 838 return port >> MV_PORT_HC_SHIFT; 839 } 840 841 static inline unsigned int mv_hardport_from_port(unsigned int port) 842 { 843 return port & MV_PORT_MASK; 844 } 845 846 /* 847 * Consolidate some rather tricky bit shift calculations. 848 * This is hot-path stuff, so not a function. 849 * Simple code, with two return values, so macro rather than inline. 850 * 851 * port is the sole input, in range 0..7. 852 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 853 * hardport is the other output, in range 0..3. 854 * 855 * Note that port and hardport may be the same variable in some cases. 856 */ 857 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 858 { \ 859 shift = mv_hc_from_port(port) * HC_SHIFT; \ 860 hardport = mv_hardport_from_port(port); \ 861 shift += hardport * 2; \ 862 } 863 864 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 865 { 866 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 867 } 868 869 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 870 unsigned int port) 871 { 872 return mv_hc_base(base, mv_hc_from_port(port)); 873 } 874 875 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 876 { 877 return mv_hc_base_from_port(base, port) + 878 MV_SATAHC_ARBTR_REG_SZ + 879 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 880 } 881 882 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 883 { 884 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 885 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 886 887 return hc_mmio + ofs; 888 } 889 890 static inline void __iomem *mv_host_base(struct ata_host *host) 891 { 892 struct mv_host_priv *hpriv = host->private_data; 893 return hpriv->base; 894 } 895 896 static inline void __iomem *mv_ap_base(struct ata_port *ap) 897 { 898 return mv_port_base(mv_host_base(ap->host), ap->port_no); 899 } 900 901 static inline int mv_get_hc_count(unsigned long port_flags) 902 { 903 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 904 } 905 906 /** 907 * mv_save_cached_regs - (re-)initialize cached port registers 908 * @ap: the port whose registers we are caching 909 * 910 * Initialize the local cache of port registers, 911 * so that reading them over and over again can 912 * be avoided on the hotter paths of this driver. 913 * This saves a few microseconds each time we switch 914 * to/from EDMA mode to perform (eg.) a drive cache flush. 915 */ 916 static void mv_save_cached_regs(struct ata_port *ap) 917 { 918 void __iomem *port_mmio = mv_ap_base(ap); 919 struct mv_port_priv *pp = ap->private_data; 920 921 pp->cached.fiscfg = readl(port_mmio + FISCFG); 922 pp->cached.ltmode = readl(port_mmio + LTMODE); 923 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 924 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 925 } 926 927 /** 928 * mv_write_cached_reg - write to a cached port register 929 * @addr: hardware address of the register 930 * @old: pointer to cached value of the register 931 * @new: new value for the register 932 * 933 * Write a new value to a cached register, 934 * but only if the value is different from before. 935 */ 936 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 937 { 938 if (new != *old) { 939 unsigned long laddr; 940 *old = new; 941 /* 942 * Workaround for 88SX60x1-B2 FEr SATA#13: 943 * Read-after-write is needed to prevent generating 64-bit 944 * write cycles on the PCI bus for SATA interface registers 945 * at offsets ending in 0x4 or 0xc. 946 * 947 * Looks like a lot of fuss, but it avoids an unnecessary 948 * +1 usec read-after-write delay for unaffected registers. 949 */ 950 laddr = (unsigned long)addr & 0xffff; 951 if (laddr >= 0x300 && laddr <= 0x33c) { 952 laddr &= 0x000f; 953 if (laddr == 0x4 || laddr == 0xc) { 954 writelfl(new, addr); /* read after write */ 955 return; 956 } 957 } 958 writel(new, addr); /* unaffected by the errata */ 959 } 960 } 961 962 static void mv_set_edma_ptrs(void __iomem *port_mmio, 963 struct mv_host_priv *hpriv, 964 struct mv_port_priv *pp) 965 { 966 u32 index; 967 968 /* 969 * initialize request queue 970 */ 971 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 972 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 973 974 WARN_ON(pp->crqb_dma & 0x3ff); 975 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 976 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 977 port_mmio + EDMA_REQ_Q_IN_PTR); 978 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 979 980 /* 981 * initialize response queue 982 */ 983 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 984 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 985 986 WARN_ON(pp->crpb_dma & 0xff); 987 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 988 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 989 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 990 port_mmio + EDMA_RSP_Q_OUT_PTR); 991 } 992 993 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 994 { 995 /* 996 * When writing to the main_irq_mask in hardware, 997 * we must ensure exclusivity between the interrupt coalescing bits 998 * and the corresponding individual port DONE_IRQ bits. 999 * 1000 * Note that this register is really an "IRQ enable" register, 1001 * not an "IRQ mask" register as Marvell's naming might suggest. 1002 */ 1003 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 1004 mask &= ~DONE_IRQ_0_3; 1005 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 1006 mask &= ~DONE_IRQ_4_7; 1007 writelfl(mask, hpriv->main_irq_mask_addr); 1008 } 1009 1010 static void mv_set_main_irq_mask(struct ata_host *host, 1011 u32 disable_bits, u32 enable_bits) 1012 { 1013 struct mv_host_priv *hpriv = host->private_data; 1014 u32 old_mask, new_mask; 1015 1016 old_mask = hpriv->main_irq_mask; 1017 new_mask = (old_mask & ~disable_bits) | enable_bits; 1018 if (new_mask != old_mask) { 1019 hpriv->main_irq_mask = new_mask; 1020 mv_write_main_irq_mask(new_mask, hpriv); 1021 } 1022 } 1023 1024 static void mv_enable_port_irqs(struct ata_port *ap, 1025 unsigned int port_bits) 1026 { 1027 unsigned int shift, hardport, port = ap->port_no; 1028 u32 disable_bits, enable_bits; 1029 1030 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1031 1032 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1033 enable_bits = port_bits << shift; 1034 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1035 } 1036 1037 static void mv_clear_and_enable_port_irqs(struct ata_port *ap, 1038 void __iomem *port_mmio, 1039 unsigned int port_irqs) 1040 { 1041 struct mv_host_priv *hpriv = ap->host->private_data; 1042 int hardport = mv_hardport_from_port(ap->port_no); 1043 void __iomem *hc_mmio = mv_hc_base_from_port( 1044 mv_host_base(ap->host), ap->port_no); 1045 u32 hc_irq_cause; 1046 1047 /* clear EDMA event indicators, if any */ 1048 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 1049 1050 /* clear pending irq events */ 1051 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1052 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 1053 1054 /* clear FIS IRQ Cause */ 1055 if (IS_GEN_IIE(hpriv)) 1056 writelfl(0, port_mmio + FIS_IRQ_CAUSE); 1057 1058 mv_enable_port_irqs(ap, port_irqs); 1059 } 1060 1061 static void mv_set_irq_coalescing(struct ata_host *host, 1062 unsigned int count, unsigned int usecs) 1063 { 1064 struct mv_host_priv *hpriv = host->private_data; 1065 void __iomem *mmio = hpriv->base, *hc_mmio; 1066 u32 coal_enable = 0; 1067 unsigned long flags; 1068 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 1069 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 1070 ALL_PORTS_COAL_DONE; 1071 1072 /* Disable IRQ coalescing if either threshold is zero */ 1073 if (!usecs || !count) { 1074 clks = count = 0; 1075 } else { 1076 /* Respect maximum limits of the hardware */ 1077 clks = usecs * COAL_CLOCKS_PER_USEC; 1078 if (clks > MAX_COAL_TIME_THRESHOLD) 1079 clks = MAX_COAL_TIME_THRESHOLD; 1080 if (count > MAX_COAL_IO_COUNT) 1081 count = MAX_COAL_IO_COUNT; 1082 } 1083 1084 spin_lock_irqsave(&host->lock, flags); 1085 mv_set_main_irq_mask(host, coal_disable, 0); 1086 1087 if (is_dual_hc && !IS_GEN_I(hpriv)) { 1088 /* 1089 * GEN_II/GEN_IIE with dual host controllers: 1090 * one set of global thresholds for the entire chip. 1091 */ 1092 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1093 writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 1094 /* clear leftover coal IRQ bit */ 1095 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 1096 if (count) 1097 coal_enable = ALL_PORTS_COAL_DONE; 1098 clks = count = 0; /* force clearing of regular regs below */ 1099 } 1100 1101 /* 1102 * All chips: independent thresholds for each HC on the chip. 1103 */ 1104 hc_mmio = mv_hc_base_from_port(mmio, 0); 1105 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1106 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1107 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1108 if (count) 1109 coal_enable |= PORTS_0_3_COAL_DONE; 1110 if (is_dual_hc) { 1111 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1112 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1113 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1114 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1115 if (count) 1116 coal_enable |= PORTS_4_7_COAL_DONE; 1117 } 1118 1119 mv_set_main_irq_mask(host, 0, coal_enable); 1120 spin_unlock_irqrestore(&host->lock, flags); 1121 } 1122 1123 /* 1124 * mv_start_edma - Enable eDMA engine 1125 * @pp: port private data 1126 * 1127 * Verify the local cache of the eDMA state is accurate with a 1128 * WARN_ON. 1129 * 1130 * LOCKING: 1131 * Inherited from caller. 1132 */ 1133 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1134 struct mv_port_priv *pp, u8 protocol) 1135 { 1136 int want_ncq = (protocol == ATA_PROT_NCQ); 1137 1138 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1139 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1140 if (want_ncq != using_ncq) 1141 mv_stop_edma(ap); 1142 } 1143 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 1144 struct mv_host_priv *hpriv = ap->host->private_data; 1145 1146 mv_edma_cfg(ap, want_ncq, 1); 1147 1148 mv_set_edma_ptrs(port_mmio, hpriv, pp); 1149 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1150 1151 writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1152 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1153 } 1154 } 1155 1156 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 1157 { 1158 void __iomem *port_mmio = mv_ap_base(ap); 1159 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 1160 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 1161 int i; 1162 1163 /* 1164 * Wait for the EDMA engine to finish transactions in progress. 1165 * No idea what a good "timeout" value might be, but measurements 1166 * indicate that it often requires hundreds of microseconds 1167 * with two drives in-use. So we use the 15msec value above 1168 * as a rough guess at what even more drives might require. 1169 */ 1170 for (i = 0; i < timeout; ++i) { 1171 u32 edma_stat = readl(port_mmio + EDMA_STATUS); 1172 if ((edma_stat & empty_idle) == empty_idle) 1173 break; 1174 udelay(per_loop); 1175 } 1176 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */ 1177 } 1178 1179 /** 1180 * mv_stop_edma_engine - Disable eDMA engine 1181 * @port_mmio: io base address 1182 * 1183 * LOCKING: 1184 * Inherited from caller. 1185 */ 1186 static int mv_stop_edma_engine(void __iomem *port_mmio) 1187 { 1188 int i; 1189 1190 /* Disable eDMA. The disable bit auto clears. */ 1191 writelfl(EDMA_DS, port_mmio + EDMA_CMD); 1192 1193 /* Wait for the chip to confirm eDMA is off. */ 1194 for (i = 10000; i > 0; i--) { 1195 u32 reg = readl(port_mmio + EDMA_CMD); 1196 if (!(reg & EDMA_EN)) 1197 return 0; 1198 udelay(10); 1199 } 1200 return -EIO; 1201 } 1202 1203 static int mv_stop_edma(struct ata_port *ap) 1204 { 1205 void __iomem *port_mmio = mv_ap_base(ap); 1206 struct mv_port_priv *pp = ap->private_data; 1207 int err = 0; 1208 1209 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1210 return 0; 1211 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1212 mv_wait_for_edma_empty_idle(ap); 1213 if (mv_stop_edma_engine(port_mmio)) { 1214 ata_port_err(ap, "Unable to stop eDMA\n"); 1215 err = -EIO; 1216 } 1217 mv_edma_cfg(ap, 0, 0); 1218 return err; 1219 } 1220 1221 static void mv_dump_mem(struct device *dev, void __iomem *start, unsigned bytes) 1222 { 1223 int b, w, o; 1224 unsigned char linebuf[38]; 1225 1226 for (b = 0; b < bytes; ) { 1227 for (w = 0, o = 0; b < bytes && w < 4; w++) { 1228 o += scnprintf(linebuf + o, sizeof(linebuf) - o, 1229 "%08x ", readl(start + b)); 1230 b += sizeof(u32); 1231 } 1232 dev_dbg(dev, "%s: %p: %s\n", 1233 __func__, start + b, linebuf); 1234 } 1235 } 1236 1237 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 1238 { 1239 int b, w, o; 1240 u32 dw = 0; 1241 unsigned char linebuf[38]; 1242 1243 for (b = 0; b < bytes; ) { 1244 for (w = 0, o = 0; b < bytes && w < 4; w++) { 1245 (void) pci_read_config_dword(pdev, b, &dw); 1246 o += snprintf(linebuf + o, sizeof(linebuf) - o, 1247 "%08x ", dw); 1248 b += sizeof(u32); 1249 } 1250 dev_dbg(&pdev->dev, "%s: %02x: %s\n", 1251 __func__, b, linebuf); 1252 } 1253 } 1254 1255 static void mv_dump_all_regs(void __iomem *mmio_base, 1256 struct pci_dev *pdev) 1257 { 1258 void __iomem *hc_base; 1259 void __iomem *port_base; 1260 int start_port, num_ports, p, start_hc, num_hcs, hc; 1261 1262 start_hc = start_port = 0; 1263 num_ports = 8; /* should be benign for 4 port devs */ 1264 num_hcs = 2; 1265 dev_dbg(&pdev->dev, 1266 "%s: All registers for port(s) %u-%u:\n", __func__, 1267 start_port, num_ports > 1 ? num_ports - 1 : start_port); 1268 1269 dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); 1270 mv_dump_pci_cfg(pdev, 0x68); 1271 1272 dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); 1273 mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); 1274 mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); 1275 mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); 1276 mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); 1277 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1278 hc_base = mv_hc_base(mmio_base, hc); 1279 dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); 1280 mv_dump_mem(&pdev->dev, hc_base, 0x1c); 1281 } 1282 for (p = start_port; p < start_port + num_ports; p++) { 1283 port_base = mv_port_base(mmio_base, p); 1284 dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); 1285 mv_dump_mem(&pdev->dev, port_base, 0x54); 1286 dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); 1287 mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); 1288 } 1289 } 1290 1291 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1292 { 1293 unsigned int ofs; 1294 1295 switch (sc_reg_in) { 1296 case SCR_STATUS: 1297 case SCR_CONTROL: 1298 case SCR_ERROR: 1299 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 1300 break; 1301 case SCR_ACTIVE: 1302 ofs = SATA_ACTIVE; /* active is not with the others */ 1303 break; 1304 default: 1305 ofs = 0xffffffffU; 1306 break; 1307 } 1308 return ofs; 1309 } 1310 1311 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 1312 { 1313 unsigned int ofs = mv_scr_offset(sc_reg_in); 1314 1315 if (ofs != 0xffffffffU) { 1316 *val = readl(mv_ap_base(link->ap) + ofs); 1317 return 0; 1318 } else 1319 return -EINVAL; 1320 } 1321 1322 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 1323 { 1324 unsigned int ofs = mv_scr_offset(sc_reg_in); 1325 1326 if (ofs != 0xffffffffU) { 1327 void __iomem *addr = mv_ap_base(link->ap) + ofs; 1328 struct mv_host_priv *hpriv = link->ap->host->private_data; 1329 if (sc_reg_in == SCR_CONTROL) { 1330 /* 1331 * Workaround for 88SX60x1 FEr SATA#26: 1332 * 1333 * COMRESETs have to take care not to accidentally 1334 * put the drive to sleep when writing SCR_CONTROL. 1335 * Setting bits 12..15 prevents this problem. 1336 * 1337 * So if we see an outbound COMMRESET, set those bits. 1338 * Ditto for the followup write that clears the reset. 1339 * 1340 * The proprietary driver does this for 1341 * all chip versions, and so do we. 1342 */ 1343 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 1344 val |= 0xf000; 1345 1346 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { 1347 void __iomem *lp_phy_addr = 1348 mv_ap_base(link->ap) + LP_PHY_CTL; 1349 /* 1350 * Set PHY speed according to SControl speed. 1351 */ 1352 u32 lp_phy_val = 1353 LP_PHY_CTL_PIN_PU_PLL | 1354 LP_PHY_CTL_PIN_PU_RX | 1355 LP_PHY_CTL_PIN_PU_TX; 1356 1357 if ((val & 0xf0) != 0x10) 1358 lp_phy_val |= 1359 LP_PHY_CTL_GEN_TX_3G | 1360 LP_PHY_CTL_GEN_RX_3G; 1361 1362 writelfl(lp_phy_val, lp_phy_addr); 1363 } 1364 } 1365 writelfl(val, addr); 1366 return 0; 1367 } else 1368 return -EINVAL; 1369 } 1370 1371 static void mv6_dev_config(struct ata_device *adev) 1372 { 1373 /* 1374 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1375 * 1376 * Gen-II does not support NCQ over a port multiplier 1377 * (no FIS-based switching). 1378 */ 1379 if (adev->flags & ATA_DFLAG_NCQ) { 1380 if (sata_pmp_attached(adev->link->ap)) { 1381 adev->flags &= ~ATA_DFLAG_NCQ; 1382 ata_dev_info(adev, 1383 "NCQ disabled for command-based switching\n"); 1384 } 1385 } 1386 } 1387 1388 static int mv_qc_defer(struct ata_queued_cmd *qc) 1389 { 1390 struct ata_link *link = qc->dev->link; 1391 struct ata_port *ap = link->ap; 1392 struct mv_port_priv *pp = ap->private_data; 1393 1394 /* 1395 * Don't allow new commands if we're in a delayed EH state 1396 * for NCQ and/or FIS-based switching. 1397 */ 1398 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1399 return ATA_DEFER_PORT; 1400 1401 /* PIO commands need exclusive link: no other commands [DMA or PIO] 1402 * can run concurrently. 1403 * set excl_link when we want to send a PIO command in DMA mode 1404 * or a non-NCQ command in NCQ mode. 1405 * When we receive a command from that link, and there are no 1406 * outstanding commands, mark a flag to clear excl_link and let 1407 * the command go through. 1408 */ 1409 if (unlikely(ap->excl_link)) { 1410 if (link == ap->excl_link) { 1411 if (ap->nr_active_links) 1412 return ATA_DEFER_PORT; 1413 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1414 return 0; 1415 } else 1416 return ATA_DEFER_PORT; 1417 } 1418 1419 /* 1420 * If the port is completely idle, then allow the new qc. 1421 */ 1422 if (ap->nr_active_links == 0) 1423 return 0; 1424 1425 /* 1426 * The port is operating in host queuing mode (EDMA) with NCQ 1427 * enabled, allow multiple NCQ commands. EDMA also allows 1428 * queueing multiple DMA commands but libata core currently 1429 * doesn't allow it. 1430 */ 1431 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1432 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1433 if (ata_is_ncq(qc->tf.protocol)) 1434 return 0; 1435 else { 1436 ap->excl_link = link; 1437 return ATA_DEFER_PORT; 1438 } 1439 } 1440 1441 return ATA_DEFER_PORT; 1442 } 1443 1444 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1445 { 1446 struct mv_port_priv *pp = ap->private_data; 1447 void __iomem *port_mmio; 1448 1449 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 1450 u32 ltmode, *old_ltmode = &pp->cached.ltmode; 1451 u32 haltcond, *old_haltcond = &pp->cached.haltcond; 1452 1453 ltmode = *old_ltmode & ~LTMODE_BIT8; 1454 haltcond = *old_haltcond | EDMA_ERR_DEV; 1455 1456 if (want_fbs) { 1457 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 1458 ltmode = *old_ltmode | LTMODE_BIT8; 1459 if (want_ncq) 1460 haltcond &= ~EDMA_ERR_DEV; 1461 else 1462 fiscfg |= FISCFG_WAIT_DEV_ERR; 1463 } else { 1464 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1465 } 1466 1467 port_mmio = mv_ap_base(ap); 1468 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1469 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1470 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1471 } 1472 1473 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1474 { 1475 struct mv_host_priv *hpriv = ap->host->private_data; 1476 u32 old, new; 1477 1478 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1479 old = readl(hpriv->base + GPIO_PORT_CTL); 1480 if (want_ncq) 1481 new = old | (1 << 22); 1482 else 1483 new = old & ~(1 << 22); 1484 if (new != old) 1485 writel(new, hpriv->base + GPIO_PORT_CTL); 1486 } 1487 1488 /* 1489 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 1490 * @ap: Port being initialized 1491 * 1492 * There are two DMA modes on these chips: basic DMA, and EDMA. 1493 * 1494 * Bit-0 of the "EDMA RESERVED" register enables/disables use 1495 * of basic DMA on the GEN_IIE versions of the chips. 1496 * 1497 * This bit survives EDMA resets, and must be set for basic DMA 1498 * to function, and should be cleared when EDMA is active. 1499 */ 1500 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1501 { 1502 struct mv_port_priv *pp = ap->private_data; 1503 u32 new, *old = &pp->cached.unknown_rsvd; 1504 1505 if (enable_bmdma) 1506 new = *old | 1; 1507 else 1508 new = *old & ~1; 1509 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1510 } 1511 1512 /* 1513 * SOC chips have an issue whereby the HDD LEDs don't always blink 1514 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1515 * of the SOC takes care of it, generating a steady blink rate when 1516 * any drive on the chip is active. 1517 * 1518 * Unfortunately, the blink mode is a global hardware setting for the SOC, 1519 * so we must use it whenever at least one port on the SOC has NCQ enabled. 1520 * 1521 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1522 * LED operation works then, and provides better (more accurate) feedback. 1523 * 1524 * Note that this code assumes that an SOC never has more than one HC onboard. 1525 */ 1526 static void mv_soc_led_blink_enable(struct ata_port *ap) 1527 { 1528 struct ata_host *host = ap->host; 1529 struct mv_host_priv *hpriv = host->private_data; 1530 void __iomem *hc_mmio; 1531 u32 led_ctrl; 1532 1533 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1534 return; 1535 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1536 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1537 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1538 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1539 } 1540 1541 static void mv_soc_led_blink_disable(struct ata_port *ap) 1542 { 1543 struct ata_host *host = ap->host; 1544 struct mv_host_priv *hpriv = host->private_data; 1545 void __iomem *hc_mmio; 1546 u32 led_ctrl; 1547 unsigned int port; 1548 1549 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1550 return; 1551 1552 /* disable led-blink only if no ports are using NCQ */ 1553 for (port = 0; port < hpriv->n_ports; port++) { 1554 struct ata_port *this_ap = host->ports[port]; 1555 struct mv_port_priv *pp = this_ap->private_data; 1556 1557 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1558 return; 1559 } 1560 1561 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1562 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1563 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1564 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1565 } 1566 1567 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1568 { 1569 u32 cfg; 1570 struct mv_port_priv *pp = ap->private_data; 1571 struct mv_host_priv *hpriv = ap->host->private_data; 1572 void __iomem *port_mmio = mv_ap_base(ap); 1573 1574 /* set up non-NCQ EDMA configuration */ 1575 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1576 pp->pp_flags &= 1577 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1578 1579 if (IS_GEN_I(hpriv)) 1580 cfg |= (1 << 8); /* enab config burst size mask */ 1581 1582 else if (IS_GEN_II(hpriv)) { 1583 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1584 mv_60x1_errata_sata25(ap, want_ncq); 1585 1586 } else if (IS_GEN_IIE(hpriv)) { 1587 int want_fbs = sata_pmp_attached(ap); 1588 /* 1589 * Possible future enhancement: 1590 * 1591 * The chip can use FBS with non-NCQ, if we allow it, 1592 * But first we need to have the error handling in place 1593 * for this mode (datasheet section 7.3.15.4.2.3). 1594 * So disallow non-NCQ FBS for now. 1595 */ 1596 want_fbs &= want_ncq; 1597 1598 mv_config_fbs(ap, want_ncq, want_fbs); 1599 1600 if (want_fbs) { 1601 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1602 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1603 } 1604 1605 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1606 if (want_edma) { 1607 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1608 if (!IS_SOC(hpriv)) 1609 cfg |= (1 << 18); /* enab early completion */ 1610 } 1611 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1612 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1613 mv_bmdma_enable_iie(ap, !want_edma); 1614 1615 if (IS_SOC(hpriv)) { 1616 if (want_ncq) 1617 mv_soc_led_blink_enable(ap); 1618 else 1619 mv_soc_led_blink_disable(ap); 1620 } 1621 } 1622 1623 if (want_ncq) { 1624 cfg |= EDMA_CFG_NCQ; 1625 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1626 } 1627 1628 writelfl(cfg, port_mmio + EDMA_CFG); 1629 } 1630 1631 static void mv_port_free_dma_mem(struct ata_port *ap) 1632 { 1633 struct mv_host_priv *hpriv = ap->host->private_data; 1634 struct mv_port_priv *pp = ap->private_data; 1635 int tag; 1636 1637 if (pp->crqb) { 1638 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1639 pp->crqb = NULL; 1640 } 1641 if (pp->crpb) { 1642 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1643 pp->crpb = NULL; 1644 } 1645 /* 1646 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1647 * For later hardware, we have one unique sg_tbl per NCQ tag. 1648 */ 1649 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1650 if (pp->sg_tbl[tag]) { 1651 if (tag == 0 || !IS_GEN_I(hpriv)) 1652 dma_pool_free(hpriv->sg_tbl_pool, 1653 pp->sg_tbl[tag], 1654 pp->sg_tbl_dma[tag]); 1655 pp->sg_tbl[tag] = NULL; 1656 } 1657 } 1658 } 1659 1660 /** 1661 * mv_port_start - Port specific init/start routine. 1662 * @ap: ATA channel to manipulate 1663 * 1664 * Allocate and point to DMA memory, init port private memory, 1665 * zero indices. 1666 * 1667 * LOCKING: 1668 * Inherited from caller. 1669 */ 1670 static int mv_port_start(struct ata_port *ap) 1671 { 1672 struct device *dev = ap->host->dev; 1673 struct mv_host_priv *hpriv = ap->host->private_data; 1674 struct mv_port_priv *pp; 1675 unsigned long flags; 1676 int tag; 1677 1678 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1679 if (!pp) 1680 return -ENOMEM; 1681 ap->private_data = pp; 1682 1683 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1684 if (!pp->crqb) 1685 return -ENOMEM; 1686 1687 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1688 if (!pp->crpb) 1689 goto out_port_free_dma_mem; 1690 1691 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1692 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1693 ap->flags |= ATA_FLAG_AN; 1694 /* 1695 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1696 * For later hardware, we need one unique sg_tbl per NCQ tag. 1697 */ 1698 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1699 if (tag == 0 || !IS_GEN_I(hpriv)) { 1700 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1701 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1702 if (!pp->sg_tbl[tag]) 1703 goto out_port_free_dma_mem; 1704 } else { 1705 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1706 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1707 } 1708 } 1709 1710 spin_lock_irqsave(ap->lock, flags); 1711 mv_save_cached_regs(ap); 1712 mv_edma_cfg(ap, 0, 0); 1713 spin_unlock_irqrestore(ap->lock, flags); 1714 1715 return 0; 1716 1717 out_port_free_dma_mem: 1718 mv_port_free_dma_mem(ap); 1719 return -ENOMEM; 1720 } 1721 1722 /** 1723 * mv_port_stop - Port specific cleanup/stop routine. 1724 * @ap: ATA channel to manipulate 1725 * 1726 * Stop DMA, cleanup port memory. 1727 * 1728 * LOCKING: 1729 * This routine uses the host lock to protect the DMA stop. 1730 */ 1731 static void mv_port_stop(struct ata_port *ap) 1732 { 1733 unsigned long flags; 1734 1735 spin_lock_irqsave(ap->lock, flags); 1736 mv_stop_edma(ap); 1737 mv_enable_port_irqs(ap, 0); 1738 spin_unlock_irqrestore(ap->lock, flags); 1739 mv_port_free_dma_mem(ap); 1740 } 1741 1742 /** 1743 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1744 * @qc: queued command whose SG list to source from 1745 * 1746 * Populate the SG list and mark the last entry. 1747 * 1748 * LOCKING: 1749 * Inherited from caller. 1750 */ 1751 static void mv_fill_sg(struct ata_queued_cmd *qc) 1752 { 1753 struct mv_port_priv *pp = qc->ap->private_data; 1754 struct scatterlist *sg; 1755 struct mv_sg *mv_sg, *last_sg = NULL; 1756 unsigned int si; 1757 1758 mv_sg = pp->sg_tbl[qc->hw_tag]; 1759 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1760 dma_addr_t addr = sg_dma_address(sg); 1761 u32 sg_len = sg_dma_len(sg); 1762 1763 while (sg_len) { 1764 u32 offset = addr & 0xffff; 1765 u32 len = sg_len; 1766 1767 if (offset + len > 0x10000) 1768 len = 0x10000 - offset; 1769 1770 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1771 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1772 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1773 mv_sg->reserved = 0; 1774 1775 sg_len -= len; 1776 addr += len; 1777 1778 last_sg = mv_sg; 1779 mv_sg++; 1780 } 1781 } 1782 1783 if (likely(last_sg)) 1784 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1785 mb(); /* ensure data structure is visible to the chipset */ 1786 } 1787 1788 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1789 { 1790 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1791 (last ? CRQB_CMD_LAST : 0); 1792 *cmdw = cpu_to_le16(tmp); 1793 } 1794 1795 /** 1796 * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1797 * @ap: Port associated with this ATA transaction. 1798 * 1799 * We need this only for ATAPI bmdma transactions, 1800 * as otherwise we experience spurious interrupts 1801 * after libata-sff handles the bmdma interrupts. 1802 */ 1803 static void mv_sff_irq_clear(struct ata_port *ap) 1804 { 1805 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1806 } 1807 1808 /** 1809 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1810 * @qc: queued command to check for chipset/DMA compatibility. 1811 * 1812 * The bmdma engines cannot handle speculative data sizes 1813 * (bytecount under/over flow). So only allow DMA for 1814 * data transfer commands with known data sizes. 1815 * 1816 * LOCKING: 1817 * Inherited from caller. 1818 */ 1819 static int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1820 { 1821 struct scsi_cmnd *scmd = qc->scsicmd; 1822 1823 if (scmd) { 1824 switch (scmd->cmnd[0]) { 1825 case READ_6: 1826 case READ_10: 1827 case READ_12: 1828 case WRITE_6: 1829 case WRITE_10: 1830 case WRITE_12: 1831 case GPCMD_READ_CD: 1832 case GPCMD_SEND_DVD_STRUCTURE: 1833 case GPCMD_SEND_CUE_SHEET: 1834 return 0; /* DMA is safe */ 1835 } 1836 } 1837 return -EOPNOTSUPP; /* use PIO instead */ 1838 } 1839 1840 /** 1841 * mv_bmdma_setup - Set up BMDMA transaction 1842 * @qc: queued command to prepare DMA for. 1843 * 1844 * LOCKING: 1845 * Inherited from caller. 1846 */ 1847 static void mv_bmdma_setup(struct ata_queued_cmd *qc) 1848 { 1849 struct ata_port *ap = qc->ap; 1850 void __iomem *port_mmio = mv_ap_base(ap); 1851 struct mv_port_priv *pp = ap->private_data; 1852 1853 mv_fill_sg(qc); 1854 1855 /* clear all DMA cmd bits */ 1856 writel(0, port_mmio + BMDMA_CMD); 1857 1858 /* load PRD table addr. */ 1859 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, 1860 port_mmio + BMDMA_PRD_HIGH); 1861 writelfl(pp->sg_tbl_dma[qc->hw_tag], 1862 port_mmio + BMDMA_PRD_LOW); 1863 1864 /* issue r/w command */ 1865 ap->ops->sff_exec_command(ap, &qc->tf); 1866 } 1867 1868 /** 1869 * mv_bmdma_start - Start a BMDMA transaction 1870 * @qc: queued command to start DMA on. 1871 * 1872 * LOCKING: 1873 * Inherited from caller. 1874 */ 1875 static void mv_bmdma_start(struct ata_queued_cmd *qc) 1876 { 1877 struct ata_port *ap = qc->ap; 1878 void __iomem *port_mmio = mv_ap_base(ap); 1879 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1880 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1881 1882 /* start host DMA transaction */ 1883 writelfl(cmd, port_mmio + BMDMA_CMD); 1884 } 1885 1886 /** 1887 * mv_bmdma_stop_ap - Stop BMDMA transfer 1888 * @ap: port to stop 1889 * 1890 * Clears the ATA_DMA_START flag in the bmdma control register 1891 * 1892 * LOCKING: 1893 * Inherited from caller. 1894 */ 1895 static void mv_bmdma_stop_ap(struct ata_port *ap) 1896 { 1897 void __iomem *port_mmio = mv_ap_base(ap); 1898 u32 cmd; 1899 1900 /* clear start/stop bit */ 1901 cmd = readl(port_mmio + BMDMA_CMD); 1902 if (cmd & ATA_DMA_START) { 1903 cmd &= ~ATA_DMA_START; 1904 writelfl(cmd, port_mmio + BMDMA_CMD); 1905 1906 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1907 ata_sff_dma_pause(ap); 1908 } 1909 } 1910 1911 static void mv_bmdma_stop(struct ata_queued_cmd *qc) 1912 { 1913 mv_bmdma_stop_ap(qc->ap); 1914 } 1915 1916 /** 1917 * mv_bmdma_status - Read BMDMA status 1918 * @ap: port for which to retrieve DMA status. 1919 * 1920 * Read and return equivalent of the sff BMDMA status register. 1921 * 1922 * LOCKING: 1923 * Inherited from caller. 1924 */ 1925 static u8 mv_bmdma_status(struct ata_port *ap) 1926 { 1927 void __iomem *port_mmio = mv_ap_base(ap); 1928 u32 reg, status; 1929 1930 /* 1931 * Other bits are valid only if ATA_DMA_ACTIVE==0, 1932 * and the ATA_DMA_INTR bit doesn't exist. 1933 */ 1934 reg = readl(port_mmio + BMDMA_STATUS); 1935 if (reg & ATA_DMA_ACTIVE) 1936 status = ATA_DMA_ACTIVE; 1937 else if (reg & ATA_DMA_ERR) 1938 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1939 else { 1940 /* 1941 * Just because DMA_ACTIVE is 0 (DMA completed), 1942 * this does _not_ mean the device is "done". 1943 * So we should not yet be signalling ATA_DMA_INTR 1944 * in some cases. Eg. DSM/TRIM, and perhaps others. 1945 */ 1946 mv_bmdma_stop_ap(ap); 1947 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) 1948 status = 0; 1949 else 1950 status = ATA_DMA_INTR; 1951 } 1952 return status; 1953 } 1954 1955 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1956 { 1957 struct ata_taskfile *tf = &qc->tf; 1958 /* 1959 * Workaround for 88SX60x1 FEr SATA#24. 1960 * 1961 * Chip may corrupt WRITEs if multi_count >= 4kB. 1962 * Note that READs are unaffected. 1963 * 1964 * It's not clear if this errata really means "4K bytes", 1965 * or if it always happens for multi_count > 7 1966 * regardless of device sector_size. 1967 * 1968 * So, for safety, any write with multi_count > 7 1969 * gets converted here into a regular PIO write instead: 1970 */ 1971 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 1972 if (qc->dev->multi_count > 7) { 1973 switch (tf->command) { 1974 case ATA_CMD_WRITE_MULTI: 1975 tf->command = ATA_CMD_PIO_WRITE; 1976 break; 1977 case ATA_CMD_WRITE_MULTI_FUA_EXT: 1978 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 1979 fallthrough; 1980 case ATA_CMD_WRITE_MULTI_EXT: 1981 tf->command = ATA_CMD_PIO_WRITE_EXT; 1982 break; 1983 } 1984 } 1985 } 1986 } 1987 1988 /** 1989 * mv_qc_prep - Host specific command preparation. 1990 * @qc: queued command to prepare 1991 * 1992 * This routine simply redirects to the general purpose routine 1993 * if command is not DMA. Else, it handles prep of the CRQB 1994 * (command request block), does some sanity checking, and calls 1995 * the SG load routine. 1996 * 1997 * LOCKING: 1998 * Inherited from caller. 1999 */ 2000 static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc) 2001 { 2002 struct ata_port *ap = qc->ap; 2003 struct mv_port_priv *pp = ap->private_data; 2004 __le16 *cw; 2005 struct ata_taskfile *tf = &qc->tf; 2006 u16 flags = 0; 2007 unsigned in_index; 2008 2009 switch (tf->protocol) { 2010 case ATA_PROT_DMA: 2011 if (tf->command == ATA_CMD_DSM) 2012 return AC_ERR_OK; 2013 fallthrough; 2014 case ATA_PROT_NCQ: 2015 break; /* continue below */ 2016 case ATA_PROT_PIO: 2017 mv_rw_multi_errata_sata24(qc); 2018 return AC_ERR_OK; 2019 default: 2020 return AC_ERR_OK; 2021 } 2022 2023 /* Fill in command request block 2024 */ 2025 if (!(tf->flags & ATA_TFLAG_WRITE)) 2026 flags |= CRQB_FLAG_READ; 2027 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); 2028 flags |= qc->hw_tag << CRQB_TAG_SHIFT; 2029 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2030 2031 /* get current queue index from software */ 2032 in_index = pp->req_idx; 2033 2034 pp->crqb[in_index].sg_addr = 2035 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); 2036 pp->crqb[in_index].sg_addr_hi = 2037 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); 2038 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 2039 2040 cw = &pp->crqb[in_index].ata_cmd[0]; 2041 2042 /* Sadly, the CRQB cannot accommodate all registers--there are 2043 * only 11 bytes...so we must pick and choose required 2044 * registers based on the command. So, we drop feature and 2045 * hob_feature for [RW] DMA commands, but they are needed for 2046 * NCQ. NCQ will drop hob_nsect, which is not needed there 2047 * (nsect is used only for the tag; feat/hob_feat hold true nsect). 2048 */ 2049 switch (tf->command) { 2050 case ATA_CMD_READ: 2051 case ATA_CMD_READ_EXT: 2052 case ATA_CMD_WRITE: 2053 case ATA_CMD_WRITE_EXT: 2054 case ATA_CMD_WRITE_FUA_EXT: 2055 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 2056 break; 2057 case ATA_CMD_FPDMA_READ: 2058 case ATA_CMD_FPDMA_WRITE: 2059 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 2060 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 2061 break; 2062 default: 2063 /* The only other commands EDMA supports in non-queued and 2064 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 2065 * of which are defined/used by Linux. If we get here, this 2066 * driver needs work. 2067 */ 2068 ata_port_err(ap, "%s: unsupported command: %.2x\n", __func__, 2069 tf->command); 2070 return AC_ERR_INVALID; 2071 } 2072 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 2073 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 2074 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 2075 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 2076 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 2077 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 2078 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 2079 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 2080 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 2081 2082 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2083 return AC_ERR_OK; 2084 mv_fill_sg(qc); 2085 2086 return AC_ERR_OK; 2087 } 2088 2089 /** 2090 * mv_qc_prep_iie - Host specific command preparation. 2091 * @qc: queued command to prepare 2092 * 2093 * This routine simply redirects to the general purpose routine 2094 * if command is not DMA. Else, it handles prep of the CRQB 2095 * (command request block), does some sanity checking, and calls 2096 * the SG load routine. 2097 * 2098 * LOCKING: 2099 * Inherited from caller. 2100 */ 2101 static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc) 2102 { 2103 struct ata_port *ap = qc->ap; 2104 struct mv_port_priv *pp = ap->private_data; 2105 struct mv_crqb_iie *crqb; 2106 struct ata_taskfile *tf = &qc->tf; 2107 unsigned in_index; 2108 u32 flags = 0; 2109 2110 if ((tf->protocol != ATA_PROT_DMA) && 2111 (tf->protocol != ATA_PROT_NCQ)) 2112 return AC_ERR_OK; 2113 if (tf->command == ATA_CMD_DSM) 2114 return AC_ERR_OK; /* use bmdma for this */ 2115 2116 /* Fill in Gen IIE command request block */ 2117 if (!(tf->flags & ATA_TFLAG_WRITE)) 2118 flags |= CRQB_FLAG_READ; 2119 2120 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); 2121 flags |= qc->hw_tag << CRQB_TAG_SHIFT; 2122 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; 2123 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2124 2125 /* get current queue index from software */ 2126 in_index = pp->req_idx; 2127 2128 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2129 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); 2130 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); 2131 crqb->flags = cpu_to_le32(flags); 2132 2133 crqb->ata_cmd[0] = cpu_to_le32( 2134 (tf->command << 16) | 2135 (tf->feature << 24) 2136 ); 2137 crqb->ata_cmd[1] = cpu_to_le32( 2138 (tf->lbal << 0) | 2139 (tf->lbam << 8) | 2140 (tf->lbah << 16) | 2141 (tf->device << 24) 2142 ); 2143 crqb->ata_cmd[2] = cpu_to_le32( 2144 (tf->hob_lbal << 0) | 2145 (tf->hob_lbam << 8) | 2146 (tf->hob_lbah << 16) | 2147 (tf->hob_feature << 24) 2148 ); 2149 crqb->ata_cmd[3] = cpu_to_le32( 2150 (tf->nsect << 0) | 2151 (tf->hob_nsect << 8) 2152 ); 2153 2154 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2155 return AC_ERR_OK; 2156 mv_fill_sg(qc); 2157 2158 return AC_ERR_OK; 2159 } 2160 2161 /** 2162 * mv_sff_check_status - fetch device status, if valid 2163 * @ap: ATA port to fetch status from 2164 * 2165 * When using command issue via mv_qc_issue_fis(), 2166 * the initial ATA_BUSY state does not show up in the 2167 * ATA status (shadow) register. This can confuse libata! 2168 * 2169 * So we have a hook here to fake ATA_BUSY for that situation, 2170 * until the first time a BUSY, DRQ, or ERR bit is seen. 2171 * 2172 * The rest of the time, it simply returns the ATA status register. 2173 */ 2174 static u8 mv_sff_check_status(struct ata_port *ap) 2175 { 2176 u8 stat = ioread8(ap->ioaddr.status_addr); 2177 struct mv_port_priv *pp = ap->private_data; 2178 2179 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2180 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2181 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2182 else 2183 stat = ATA_BUSY; 2184 } 2185 return stat; 2186 } 2187 2188 /** 2189 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 2190 * @ap: ATA port to send a FIS 2191 * @fis: fis to be sent 2192 * @nwords: number of 32-bit words in the fis 2193 */ 2194 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 2195 { 2196 void __iomem *port_mmio = mv_ap_base(ap); 2197 u32 ifctl, old_ifctl, ifstat; 2198 int i, timeout = 200, final_word = nwords - 1; 2199 2200 /* Initiate FIS transmission mode */ 2201 old_ifctl = readl(port_mmio + SATA_IFCTL); 2202 ifctl = 0x100 | (old_ifctl & 0xf); 2203 writelfl(ifctl, port_mmio + SATA_IFCTL); 2204 2205 /* Send all words of the FIS except for the final word */ 2206 for (i = 0; i < final_word; ++i) 2207 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 2208 2209 /* Flag end-of-transmission, and then send the final word */ 2210 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2211 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 2212 2213 /* 2214 * Wait for FIS transmission to complete. 2215 * This typically takes just a single iteration. 2216 */ 2217 do { 2218 ifstat = readl(port_mmio + SATA_IFSTAT); 2219 } while (!(ifstat & 0x1000) && --timeout); 2220 2221 /* Restore original port configuration */ 2222 writelfl(old_ifctl, port_mmio + SATA_IFCTL); 2223 2224 /* See if it worked */ 2225 if ((ifstat & 0x3000) != 0x1000) { 2226 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n", 2227 __func__, ifstat); 2228 return AC_ERR_OTHER; 2229 } 2230 return 0; 2231 } 2232 2233 /** 2234 * mv_qc_issue_fis - Issue a command directly as a FIS 2235 * @qc: queued command to start 2236 * 2237 * Note that the ATA shadow registers are not updated 2238 * after command issue, so the device will appear "READY" 2239 * if polled, even while it is BUSY processing the command. 2240 * 2241 * So we use a status hook to fake ATA_BUSY until the drive changes state. 2242 * 2243 * Note: we don't get updated shadow regs on *completion* 2244 * of non-data commands. So avoid sending them via this function, 2245 * as they will appear to have completed immediately. 2246 * 2247 * GEN_IIE has special registers that we could get the result tf from, 2248 * but earlier chipsets do not. For now, we ignore those registers. 2249 */ 2250 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 2251 { 2252 struct ata_port *ap = qc->ap; 2253 struct mv_port_priv *pp = ap->private_data; 2254 struct ata_link *link = qc->dev->link; 2255 u32 fis[5]; 2256 int err = 0; 2257 2258 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 2259 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 2260 if (err) 2261 return err; 2262 2263 switch (qc->tf.protocol) { 2264 case ATAPI_PROT_PIO: 2265 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2266 fallthrough; 2267 case ATAPI_PROT_NODATA: 2268 ap->hsm_task_state = HSM_ST_FIRST; 2269 break; 2270 case ATA_PROT_PIO: 2271 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2272 if (qc->tf.flags & ATA_TFLAG_WRITE) 2273 ap->hsm_task_state = HSM_ST_FIRST; 2274 else 2275 ap->hsm_task_state = HSM_ST; 2276 break; 2277 default: 2278 ap->hsm_task_state = HSM_ST_LAST; 2279 break; 2280 } 2281 2282 if (qc->tf.flags & ATA_TFLAG_POLLING) 2283 ata_sff_queue_pio_task(link, 0); 2284 return 0; 2285 } 2286 2287 /** 2288 * mv_qc_issue - Initiate a command to the host 2289 * @qc: queued command to start 2290 * 2291 * This routine simply redirects to the general purpose routine 2292 * if command is not DMA. Else, it sanity checks our local 2293 * caches of the request producer/consumer indices then enables 2294 * DMA and bumps the request producer index. 2295 * 2296 * LOCKING: 2297 * Inherited from caller. 2298 */ 2299 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 2300 { 2301 static int limit_warnings = 10; 2302 struct ata_port *ap = qc->ap; 2303 void __iomem *port_mmio = mv_ap_base(ap); 2304 struct mv_port_priv *pp = ap->private_data; 2305 u32 in_index; 2306 unsigned int port_irqs; 2307 2308 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2309 2310 switch (qc->tf.protocol) { 2311 case ATA_PROT_DMA: 2312 if (qc->tf.command == ATA_CMD_DSM) { 2313 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ 2314 return AC_ERR_OTHER; 2315 break; /* use bmdma for this */ 2316 } 2317 fallthrough; 2318 case ATA_PROT_NCQ: 2319 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2320 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2321 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2322 2323 /* Write the request in pointer to kick the EDMA to life */ 2324 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2325 port_mmio + EDMA_REQ_Q_IN_PTR); 2326 return 0; 2327 2328 case ATA_PROT_PIO: 2329 /* 2330 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2331 * 2332 * Someday, we might implement special polling workarounds 2333 * for these, but it all seems rather unnecessary since we 2334 * normally use only DMA for commands which transfer more 2335 * than a single block of data. 2336 * 2337 * Much of the time, this could just work regardless. 2338 * So for now, just log the incident, and allow the attempt. 2339 */ 2340 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2341 --limit_warnings; 2342 ata_link_warn(qc->dev->link, DRV_NAME 2343 ": attempting PIO w/multiple DRQ: " 2344 "this may fail due to h/w errata\n"); 2345 } 2346 fallthrough; 2347 case ATA_PROT_NODATA: 2348 case ATAPI_PROT_PIO: 2349 case ATAPI_PROT_NODATA: 2350 if (ap->flags & ATA_FLAG_PIO_POLLING) 2351 qc->tf.flags |= ATA_TFLAG_POLLING; 2352 break; 2353 } 2354 2355 if (qc->tf.flags & ATA_TFLAG_POLLING) 2356 port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 2357 else 2358 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 2359 2360 /* 2361 * We're about to send a non-EDMA capable command to the 2362 * port. Turn off EDMA so there won't be problems accessing 2363 * shadow block, etc registers. 2364 */ 2365 mv_stop_edma(ap); 2366 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 2367 mv_pmp_select(ap, qc->dev->link->pmp); 2368 2369 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 2370 struct mv_host_priv *hpriv = ap->host->private_data; 2371 /* 2372 * Workaround for 88SX60x1 FEr SATA#25 (part 2). 2373 * 2374 * After any NCQ error, the READ_LOG_EXT command 2375 * from libata-eh *must* use mv_qc_issue_fis(). 2376 * Otherwise it might fail, due to chip errata. 2377 * 2378 * Rather than special-case it, we'll just *always* 2379 * use this method here for READ_LOG_EXT, making for 2380 * easier testing. 2381 */ 2382 if (IS_GEN_II(hpriv)) 2383 return mv_qc_issue_fis(qc); 2384 } 2385 return ata_bmdma_qc_issue(qc); 2386 } 2387 2388 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 2389 { 2390 struct mv_port_priv *pp = ap->private_data; 2391 struct ata_queued_cmd *qc; 2392 2393 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 2394 return NULL; 2395 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2396 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 2397 return qc; 2398 return NULL; 2399 } 2400 2401 static void mv_pmp_error_handler(struct ata_port *ap) 2402 __must_hold(&ap->host->eh_mutex) 2403 { 2404 unsigned int pmp, pmp_map; 2405 struct mv_port_priv *pp = ap->private_data; 2406 2407 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 2408 /* 2409 * Perform NCQ error analysis on failed PMPs 2410 * before we freeze the port entirely. 2411 * 2412 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 2413 */ 2414 pmp_map = pp->delayed_eh_pmp_map; 2415 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 2416 for (pmp = 0; pmp_map != 0; pmp++) { 2417 unsigned int this_pmp = (1 << pmp); 2418 if (pmp_map & this_pmp) { 2419 struct ata_link *link = &ap->pmp_link[pmp]; 2420 pmp_map &= ~this_pmp; 2421 ata_eh_analyze_ncq_error(link); 2422 } 2423 } 2424 ata_port_freeze(ap); 2425 } 2426 sata_pmp_error_handler(ap); 2427 } 2428 2429 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 2430 { 2431 void __iomem *port_mmio = mv_ap_base(ap); 2432 2433 return readl(port_mmio + SATA_TESTCTL) >> 16; 2434 } 2435 2436 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 2437 { 2438 unsigned int pmp; 2439 2440 /* 2441 * Initialize EH info for PMPs which saw device errors 2442 */ 2443 for (pmp = 0; pmp_map != 0; pmp++) { 2444 unsigned int this_pmp = (1 << pmp); 2445 if (pmp_map & this_pmp) { 2446 struct ata_link *link = &ap->pmp_link[pmp]; 2447 struct ata_eh_info *ehi = &link->eh_info; 2448 2449 pmp_map &= ~this_pmp; 2450 ata_ehi_clear_desc(ehi); 2451 ata_ehi_push_desc(ehi, "dev err"); 2452 ehi->err_mask |= AC_ERR_DEV; 2453 ehi->action |= ATA_EH_RESET; 2454 ata_link_abort(link); 2455 } 2456 } 2457 } 2458 2459 static int mv_req_q_empty(struct ata_port *ap) 2460 { 2461 void __iomem *port_mmio = mv_ap_base(ap); 2462 u32 in_ptr, out_ptr; 2463 2464 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 2465 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2466 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 2467 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2468 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 2469 } 2470 2471 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 2472 { 2473 struct mv_port_priv *pp = ap->private_data; 2474 int failed_links; 2475 unsigned int old_map, new_map; 2476 2477 /* 2478 * Device error during FBS+NCQ operation: 2479 * 2480 * Set a port flag to prevent further I/O being enqueued. 2481 * Leave the EDMA running to drain outstanding commands from this port. 2482 * Perform the post-mortem/EH only when all responses are complete. 2483 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 2484 */ 2485 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 2486 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 2487 pp->delayed_eh_pmp_map = 0; 2488 } 2489 old_map = pp->delayed_eh_pmp_map; 2490 new_map = old_map | mv_get_err_pmp_map(ap); 2491 2492 if (old_map != new_map) { 2493 pp->delayed_eh_pmp_map = new_map; 2494 mv_pmp_eh_prep(ap, new_map & ~old_map); 2495 } 2496 failed_links = hweight16(new_map); 2497 2498 ata_port_info(ap, 2499 "%s: pmp_map=%04x qc_map=%04llx failed_links=%d nr_active_links=%d\n", 2500 __func__, pp->delayed_eh_pmp_map, 2501 ap->qc_active, failed_links, 2502 ap->nr_active_links); 2503 2504 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 2505 mv_process_crpb_entries(ap, pp); 2506 mv_stop_edma(ap); 2507 mv_eh_freeze(ap); 2508 ata_port_info(ap, "%s: done\n", __func__); 2509 return 1; /* handled */ 2510 } 2511 ata_port_info(ap, "%s: waiting\n", __func__); 2512 return 1; /* handled */ 2513 } 2514 2515 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 2516 { 2517 /* 2518 * Possible future enhancement: 2519 * 2520 * FBS+non-NCQ operation is not yet implemented. 2521 * See related notes in mv_edma_cfg(). 2522 * 2523 * Device error during FBS+non-NCQ operation: 2524 * 2525 * We need to snapshot the shadow registers for each failed command. 2526 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 2527 */ 2528 return 0; /* not handled */ 2529 } 2530 2531 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 2532 { 2533 struct mv_port_priv *pp = ap->private_data; 2534 2535 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 2536 return 0; /* EDMA was not active: not handled */ 2537 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 2538 return 0; /* FBS was not active: not handled */ 2539 2540 if (!(edma_err_cause & EDMA_ERR_DEV)) 2541 return 0; /* non DEV error: not handled */ 2542 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 2543 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 2544 return 0; /* other problems: not handled */ 2545 2546 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 2547 /* 2548 * EDMA should NOT have self-disabled for this case. 2549 * If it did, then something is wrong elsewhere, 2550 * and we cannot handle it here. 2551 */ 2552 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2553 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2554 __func__, edma_err_cause, pp->pp_flags); 2555 return 0; /* not handled */ 2556 } 2557 return mv_handle_fbs_ncq_dev_err(ap); 2558 } else { 2559 /* 2560 * EDMA should have self-disabled for this case. 2561 * If it did not, then something is wrong elsewhere, 2562 * and we cannot handle it here. 2563 */ 2564 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 2565 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2566 __func__, edma_err_cause, pp->pp_flags); 2567 return 0; /* not handled */ 2568 } 2569 return mv_handle_fbs_non_ncq_dev_err(ap); 2570 } 2571 return 0; /* not handled */ 2572 } 2573 2574 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 2575 { 2576 struct ata_eh_info *ehi = &ap->link.eh_info; 2577 char *when = "idle"; 2578 2579 ata_ehi_clear_desc(ehi); 2580 if (edma_was_enabled) { 2581 when = "EDMA enabled"; 2582 } else { 2583 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 2584 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2585 when = "polling"; 2586 } 2587 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 2588 ehi->err_mask |= AC_ERR_OTHER; 2589 ehi->action |= ATA_EH_RESET; 2590 ata_port_freeze(ap); 2591 } 2592 2593 /** 2594 * mv_err_intr - Handle error interrupts on the port 2595 * @ap: ATA channel to manipulate 2596 * 2597 * Most cases require a full reset of the chip's state machine, 2598 * which also performs a COMRESET. 2599 * Also, if the port disabled DMA, update our cached copy to match. 2600 * 2601 * LOCKING: 2602 * Inherited from caller. 2603 */ 2604 static void mv_err_intr(struct ata_port *ap) 2605 { 2606 void __iomem *port_mmio = mv_ap_base(ap); 2607 u32 edma_err_cause, eh_freeze_mask, serr = 0; 2608 u32 fis_cause = 0; 2609 struct mv_port_priv *pp = ap->private_data; 2610 struct mv_host_priv *hpriv = ap->host->private_data; 2611 unsigned int action = 0, err_mask = 0; 2612 struct ata_eh_info *ehi = &ap->link.eh_info; 2613 struct ata_queued_cmd *qc; 2614 int abort = 0; 2615 2616 /* 2617 * Read and clear the SError and err_cause bits. 2618 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2619 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 2620 */ 2621 sata_scr_read(&ap->link, SCR_ERROR, &serr); 2622 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 2623 2624 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2625 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2626 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2627 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2628 } 2629 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2630 2631 if (edma_err_cause & EDMA_ERR_DEV) { 2632 /* 2633 * Device errors during FIS-based switching operation 2634 * require special handling. 2635 */ 2636 if (mv_handle_dev_err(ap, edma_err_cause)) 2637 return; 2638 } 2639 2640 qc = mv_get_active_qc(ap); 2641 ata_ehi_clear_desc(ehi); 2642 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 2643 edma_err_cause, pp->pp_flags); 2644 2645 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2646 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2647 if (fis_cause & FIS_IRQ_CAUSE_AN) { 2648 u32 ec = edma_err_cause & 2649 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2650 sata_async_notification(ap); 2651 if (!ec) 2652 return; /* Just an AN; no need for the nukes */ 2653 ata_ehi_push_desc(ehi, "SDB notify"); 2654 } 2655 } 2656 /* 2657 * All generations share these EDMA error cause bits: 2658 */ 2659 if (edma_err_cause & EDMA_ERR_DEV) { 2660 err_mask |= AC_ERR_DEV; 2661 action |= ATA_EH_RESET; 2662 ata_ehi_push_desc(ehi, "dev error"); 2663 } 2664 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 2665 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2666 EDMA_ERR_INTRL_PAR)) { 2667 err_mask |= AC_ERR_ATA_BUS; 2668 action |= ATA_EH_RESET; 2669 ata_ehi_push_desc(ehi, "parity error"); 2670 } 2671 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2672 ata_ehi_hotplugged(ehi); 2673 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2674 "dev disconnect" : "dev connect"); 2675 action |= ATA_EH_RESET; 2676 } 2677 2678 /* 2679 * Gen-I has a different SELF_DIS bit, 2680 * different FREEZE bits, and no SERR bit: 2681 */ 2682 if (IS_GEN_I(hpriv)) { 2683 eh_freeze_mask = EDMA_EH_FREEZE_5; 2684 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2685 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2686 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2687 } 2688 } else { 2689 eh_freeze_mask = EDMA_EH_FREEZE; 2690 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2691 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2692 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2693 } 2694 if (edma_err_cause & EDMA_ERR_SERR) { 2695 ata_ehi_push_desc(ehi, "SError=%08x", serr); 2696 err_mask |= AC_ERR_ATA_BUS; 2697 action |= ATA_EH_RESET; 2698 } 2699 } 2700 2701 if (!err_mask) { 2702 err_mask = AC_ERR_OTHER; 2703 action |= ATA_EH_RESET; 2704 } 2705 2706 ehi->serror |= serr; 2707 ehi->action |= action; 2708 2709 if (qc) 2710 qc->err_mask |= err_mask; 2711 else 2712 ehi->err_mask |= err_mask; 2713 2714 if (err_mask == AC_ERR_DEV) { 2715 /* 2716 * Cannot do ata_port_freeze() here, 2717 * because it would kill PIO access, 2718 * which is needed for further diagnosis. 2719 */ 2720 mv_eh_freeze(ap); 2721 abort = 1; 2722 } else if (edma_err_cause & eh_freeze_mask) { 2723 /* 2724 * Note to self: ata_port_freeze() calls ata_port_abort() 2725 */ 2726 ata_port_freeze(ap); 2727 } else { 2728 abort = 1; 2729 } 2730 2731 if (abort) { 2732 if (qc) 2733 ata_link_abort(qc->dev->link); 2734 else 2735 ata_port_abort(ap); 2736 } 2737 } 2738 2739 static bool mv_process_crpb_response(struct ata_port *ap, 2740 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2741 { 2742 u8 ata_status; 2743 u16 edma_status = le16_to_cpu(response->flags); 2744 2745 /* 2746 * edma_status from a response queue entry: 2747 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2748 * MSB is saved ATA status from command completion. 2749 */ 2750 if (!ncq_enabled) { 2751 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2752 if (err_cause) { 2753 /* 2754 * Error will be seen/handled by 2755 * mv_err_intr(). So do nothing at all here. 2756 */ 2757 return false; 2758 } 2759 } 2760 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2761 if (!ac_err_mask(ata_status)) 2762 return true; 2763 /* else: leave it for mv_err_intr() */ 2764 return false; 2765 } 2766 2767 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2768 { 2769 void __iomem *port_mmio = mv_ap_base(ap); 2770 struct mv_host_priv *hpriv = ap->host->private_data; 2771 u32 in_index; 2772 bool work_done = false; 2773 u32 done_mask = 0; 2774 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2775 2776 /* Get the hardware queue position index */ 2777 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2778 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2779 2780 /* Process new responses from since the last time we looked */ 2781 while (in_index != pp->resp_idx) { 2782 unsigned int tag; 2783 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2784 2785 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2786 2787 if (IS_GEN_I(hpriv)) { 2788 /* 50xx: no NCQ, only one command active at a time */ 2789 tag = ap->link.active_tag; 2790 } else { 2791 /* Gen II/IIE: get command tag from CRPB entry */ 2792 tag = le16_to_cpu(response->id) & 0x1f; 2793 } 2794 if (mv_process_crpb_response(ap, response, tag, ncq_enabled)) 2795 done_mask |= 1 << tag; 2796 work_done = true; 2797 } 2798 2799 if (work_done) { 2800 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask); 2801 2802 /* Update the software queue position index in hardware */ 2803 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2804 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2805 port_mmio + EDMA_RSP_Q_OUT_PTR); 2806 } 2807 } 2808 2809 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2810 { 2811 struct mv_port_priv *pp; 2812 int edma_was_enabled; 2813 2814 /* 2815 * Grab a snapshot of the EDMA_EN flag setting, 2816 * so that we have a consistent view for this port, 2817 * even if something we call of our routines changes it. 2818 */ 2819 pp = ap->private_data; 2820 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2821 /* 2822 * Process completed CRPB response(s) before other events. 2823 */ 2824 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2825 mv_process_crpb_entries(ap, pp); 2826 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2827 mv_handle_fbs_ncq_dev_err(ap); 2828 } 2829 /* 2830 * Handle chip-reported errors, or continue on to handle PIO. 2831 */ 2832 if (unlikely(port_cause & ERR_IRQ)) { 2833 mv_err_intr(ap); 2834 } else if (!edma_was_enabled) { 2835 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2836 if (qc) 2837 ata_bmdma_port_intr(ap, qc); 2838 else 2839 mv_unexpected_intr(ap, edma_was_enabled); 2840 } 2841 } 2842 2843 /** 2844 * mv_host_intr - Handle all interrupts on the given host controller 2845 * @host: host specific structure 2846 * @main_irq_cause: Main interrupt cause register for the chip. 2847 * 2848 * LOCKING: 2849 * Inherited from caller. 2850 */ 2851 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2852 { 2853 struct mv_host_priv *hpriv = host->private_data; 2854 void __iomem *mmio = hpriv->base, *hc_mmio; 2855 unsigned int handled = 0, port; 2856 2857 /* If asserted, clear the "all ports" IRQ coalescing bit */ 2858 if (main_irq_cause & ALL_PORTS_COAL_DONE) 2859 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 2860 2861 for (port = 0; port < hpriv->n_ports; port++) { 2862 struct ata_port *ap = host->ports[port]; 2863 unsigned int p, shift, hardport, port_cause; 2864 2865 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2866 /* 2867 * Each hc within the host has its own hc_irq_cause register, 2868 * where the interrupting ports bits get ack'd. 2869 */ 2870 if (hardport == 0) { /* first port on this hc ? */ 2871 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2872 u32 port_mask, ack_irqs; 2873 /* 2874 * Skip this entire hc if nothing pending for any ports 2875 */ 2876 if (!hc_cause) { 2877 port += MV_PORTS_PER_HC - 1; 2878 continue; 2879 } 2880 /* 2881 * We don't need/want to read the hc_irq_cause register, 2882 * because doing so hurts performance, and 2883 * main_irq_cause already gives us everything we need. 2884 * 2885 * But we do have to *write* to the hc_irq_cause to ack 2886 * the ports that we are handling this time through. 2887 * 2888 * This requires that we create a bitmap for those 2889 * ports which interrupted us, and use that bitmap 2890 * to ack (only) those ports via hc_irq_cause. 2891 */ 2892 ack_irqs = 0; 2893 if (hc_cause & PORTS_0_3_COAL_DONE) 2894 ack_irqs = HC_COAL_IRQ; 2895 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2896 if ((port + p) >= hpriv->n_ports) 2897 break; 2898 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2899 if (hc_cause & port_mask) 2900 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2901 } 2902 hc_mmio = mv_hc_base_from_port(mmio, port); 2903 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2904 handled = 1; 2905 } 2906 /* 2907 * Handle interrupts signalled for this port: 2908 */ 2909 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2910 if (port_cause) 2911 mv_port_intr(ap, port_cause); 2912 } 2913 return handled; 2914 } 2915 2916 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2917 { 2918 struct mv_host_priv *hpriv = host->private_data; 2919 struct ata_port *ap; 2920 struct ata_queued_cmd *qc; 2921 struct ata_eh_info *ehi; 2922 unsigned int i, err_mask, printed = 0; 2923 u32 err_cause; 2924 2925 err_cause = readl(mmio + hpriv->irq_cause_offset); 2926 2927 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); 2928 2929 dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); 2930 mv_dump_all_regs(mmio, to_pci_dev(host->dev)); 2931 2932 writelfl(0, mmio + hpriv->irq_cause_offset); 2933 2934 for (i = 0; i < host->n_ports; i++) { 2935 ap = host->ports[i]; 2936 if (!ata_link_offline(&ap->link)) { 2937 ehi = &ap->link.eh_info; 2938 ata_ehi_clear_desc(ehi); 2939 if (!printed++) 2940 ata_ehi_push_desc(ehi, 2941 "PCI err cause 0x%08x", err_cause); 2942 err_mask = AC_ERR_HOST_BUS; 2943 ehi->action = ATA_EH_RESET; 2944 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2945 if (qc) 2946 qc->err_mask |= err_mask; 2947 else 2948 ehi->err_mask |= err_mask; 2949 2950 ata_port_freeze(ap); 2951 } 2952 } 2953 return 1; /* handled */ 2954 } 2955 2956 /** 2957 * mv_interrupt - Main interrupt event handler 2958 * @irq: unused 2959 * @dev_instance: private data; in this case the host structure 2960 * 2961 * Read the read only register to determine if any host 2962 * controllers have pending interrupts. If so, call lower level 2963 * routine to handle. Also check for PCI errors which are only 2964 * reported here. 2965 * 2966 * LOCKING: 2967 * This routine holds the host lock while processing pending 2968 * interrupts. 2969 */ 2970 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 2971 { 2972 struct ata_host *host = dev_instance; 2973 struct mv_host_priv *hpriv = host->private_data; 2974 unsigned int handled = 0; 2975 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 2976 u32 main_irq_cause, pending_irqs; 2977 2978 spin_lock(&host->lock); 2979 2980 /* for MSI: block new interrupts while in here */ 2981 if (using_msi) 2982 mv_write_main_irq_mask(0, hpriv); 2983 2984 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2985 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2986 /* 2987 * Deal with cases where we either have nothing pending, or have read 2988 * a bogus register value which can indicate HW removal or PCI fault. 2989 */ 2990 if (pending_irqs && main_irq_cause != 0xffffffffU) { 2991 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2992 handled = mv_pci_error(host, hpriv->base); 2993 else 2994 handled = mv_host_intr(host, pending_irqs); 2995 } 2996 2997 /* for MSI: unmask; interrupt cause bits will retrigger now */ 2998 if (using_msi) 2999 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 3000 3001 spin_unlock(&host->lock); 3002 3003 return IRQ_RETVAL(handled); 3004 } 3005 3006 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 3007 { 3008 unsigned int ofs; 3009 3010 switch (sc_reg_in) { 3011 case SCR_STATUS: 3012 case SCR_ERROR: 3013 case SCR_CONTROL: 3014 ofs = sc_reg_in * sizeof(u32); 3015 break; 3016 default: 3017 ofs = 0xffffffffU; 3018 break; 3019 } 3020 return ofs; 3021 } 3022 3023 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3024 { 3025 struct mv_host_priv *hpriv = link->ap->host->private_data; 3026 void __iomem *mmio = hpriv->base; 3027 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3028 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3029 3030 if (ofs != 0xffffffffU) { 3031 *val = readl(addr + ofs); 3032 return 0; 3033 } else 3034 return -EINVAL; 3035 } 3036 3037 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3038 { 3039 struct mv_host_priv *hpriv = link->ap->host->private_data; 3040 void __iomem *mmio = hpriv->base; 3041 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3042 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3043 3044 if (ofs != 0xffffffffU) { 3045 writelfl(val, addr + ofs); 3046 return 0; 3047 } else 3048 return -EINVAL; 3049 } 3050 3051 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3052 { 3053 struct pci_dev *pdev = to_pci_dev(host->dev); 3054 int early_5080; 3055 3056 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3057 3058 if (!early_5080) { 3059 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3060 tmp |= (1 << 0); 3061 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3062 } 3063 3064 mv_reset_pci_bus(host, mmio); 3065 } 3066 3067 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3068 { 3069 writel(0x0fcfffff, mmio + FLASH_CTL); 3070 } 3071 3072 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3073 void __iomem *mmio) 3074 { 3075 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3076 u32 tmp; 3077 3078 tmp = readl(phy_mmio + MV5_PHY_MODE); 3079 3080 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3081 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3082 } 3083 3084 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3085 { 3086 u32 tmp; 3087 3088 writel(0, mmio + GPIO_PORT_CTL); 3089 3090 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3091 3092 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3093 tmp |= ~(1 << 0); 3094 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3095 } 3096 3097 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3098 unsigned int port) 3099 { 3100 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3101 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3102 u32 tmp; 3103 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3104 3105 if (fix_apm_sq) { 3106 tmp = readl(phy_mmio + MV5_LTMODE); 3107 tmp |= (1 << 19); 3108 writel(tmp, phy_mmio + MV5_LTMODE); 3109 3110 tmp = readl(phy_mmio + MV5_PHY_CTL); 3111 tmp &= ~0x3; 3112 tmp |= 0x1; 3113 writel(tmp, phy_mmio + MV5_PHY_CTL); 3114 } 3115 3116 tmp = readl(phy_mmio + MV5_PHY_MODE); 3117 tmp &= ~mask; 3118 tmp |= hpriv->signal[port].pre; 3119 tmp |= hpriv->signal[port].amps; 3120 writel(tmp, phy_mmio + MV5_PHY_MODE); 3121 } 3122 3123 3124 #undef ZERO 3125 #define ZERO(reg) writel(0, port_mmio + (reg)) 3126 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3127 unsigned int port) 3128 { 3129 void __iomem *port_mmio = mv_port_base(mmio, port); 3130 3131 mv_reset_channel(hpriv, mmio, port); 3132 3133 ZERO(0x028); /* command */ 3134 writel(0x11f, port_mmio + EDMA_CFG); 3135 ZERO(0x004); /* timer */ 3136 ZERO(0x008); /* irq err cause */ 3137 ZERO(0x00c); /* irq err mask */ 3138 ZERO(0x010); /* rq bah */ 3139 ZERO(0x014); /* rq inp */ 3140 ZERO(0x018); /* rq outp */ 3141 ZERO(0x01c); /* respq bah */ 3142 ZERO(0x024); /* respq outp */ 3143 ZERO(0x020); /* respq inp */ 3144 ZERO(0x02c); /* test control */ 3145 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3146 } 3147 #undef ZERO 3148 3149 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3150 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3151 unsigned int hc) 3152 { 3153 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3154 u32 tmp; 3155 3156 ZERO(0x00c); 3157 ZERO(0x010); 3158 ZERO(0x014); 3159 ZERO(0x018); 3160 3161 tmp = readl(hc_mmio + 0x20); 3162 tmp &= 0x1c1c1c1c; 3163 tmp |= 0x03030303; 3164 writel(tmp, hc_mmio + 0x20); 3165 } 3166 #undef ZERO 3167 3168 static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio, 3169 unsigned int n_hc) 3170 { 3171 struct mv_host_priv *hpriv = host->private_data; 3172 unsigned int hc, port; 3173 3174 for (hc = 0; hc < n_hc; hc++) { 3175 for (port = 0; port < MV_PORTS_PER_HC; port++) 3176 mv5_reset_hc_port(hpriv, mmio, 3177 (hc * MV_PORTS_PER_HC) + port); 3178 3179 mv5_reset_one_hc(hpriv, mmio, hc); 3180 } 3181 3182 return 0; 3183 } 3184 3185 #undef ZERO 3186 #define ZERO(reg) writel(0, mmio + (reg)) 3187 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3188 { 3189 struct mv_host_priv *hpriv = host->private_data; 3190 u32 tmp; 3191 3192 tmp = readl(mmio + MV_PCI_MODE); 3193 tmp &= 0xff00ffff; 3194 writel(tmp, mmio + MV_PCI_MODE); 3195 3196 ZERO(MV_PCI_DISC_TIMER); 3197 ZERO(MV_PCI_MSI_TRIGGER); 3198 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3199 ZERO(MV_PCI_SERR_MASK); 3200 ZERO(hpriv->irq_cause_offset); 3201 ZERO(hpriv->irq_mask_offset); 3202 ZERO(MV_PCI_ERR_LOW_ADDRESS); 3203 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3204 ZERO(MV_PCI_ERR_ATTRIBUTE); 3205 ZERO(MV_PCI_ERR_COMMAND); 3206 } 3207 #undef ZERO 3208 3209 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3210 { 3211 u32 tmp; 3212 3213 mv5_reset_flash(hpriv, mmio); 3214 3215 tmp = readl(mmio + GPIO_PORT_CTL); 3216 tmp &= 0x3; 3217 tmp |= (1 << 5) | (1 << 6); 3218 writel(tmp, mmio + GPIO_PORT_CTL); 3219 } 3220 3221 /* 3222 * mv6_reset_hc - Perform the 6xxx global soft reset 3223 * @mmio: base address of the HBA 3224 * 3225 * This routine only applies to 6xxx parts. 3226 * 3227 * LOCKING: 3228 * Inherited from caller. 3229 */ 3230 static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio, 3231 unsigned int n_hc) 3232 { 3233 void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3234 int i, rc = 0; 3235 u32 t; 3236 3237 /* Following procedure defined in PCI "main command and status 3238 * register" table. 3239 */ 3240 t = readl(reg); 3241 writel(t | STOP_PCI_MASTER, reg); 3242 3243 for (i = 0; i < 1000; i++) { 3244 udelay(1); 3245 t = readl(reg); 3246 if (PCI_MASTER_EMPTY & t) 3247 break; 3248 } 3249 if (!(PCI_MASTER_EMPTY & t)) { 3250 dev_err(host->dev, "PCI master won't flush\n"); 3251 rc = 1; 3252 goto done; 3253 } 3254 3255 /* set reset */ 3256 i = 5; 3257 do { 3258 writel(t | GLOB_SFT_RST, reg); 3259 t = readl(reg); 3260 udelay(1); 3261 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3262 3263 if (!(GLOB_SFT_RST & t)) { 3264 dev_err(host->dev, "can't set global reset\n"); 3265 rc = 1; 3266 goto done; 3267 } 3268 3269 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3270 i = 5; 3271 do { 3272 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3273 t = readl(reg); 3274 udelay(1); 3275 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3276 3277 if (GLOB_SFT_RST & t) { 3278 dev_err(host->dev, "can't clear global reset\n"); 3279 rc = 1; 3280 } 3281 done: 3282 return rc; 3283 } 3284 3285 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3286 void __iomem *mmio) 3287 { 3288 void __iomem *port_mmio; 3289 u32 tmp; 3290 3291 tmp = readl(mmio + RESET_CFG); 3292 if ((tmp & (1 << 0)) == 0) { 3293 hpriv->signal[idx].amps = 0x7 << 8; 3294 hpriv->signal[idx].pre = 0x1 << 5; 3295 return; 3296 } 3297 3298 port_mmio = mv_port_base(mmio, idx); 3299 tmp = readl(port_mmio + PHY_MODE2); 3300 3301 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3302 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3303 } 3304 3305 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3306 { 3307 writel(0x00000060, mmio + GPIO_PORT_CTL); 3308 } 3309 3310 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3311 unsigned int port) 3312 { 3313 void __iomem *port_mmio = mv_port_base(mmio, port); 3314 3315 u32 hp_flags = hpriv->hp_flags; 3316 int fix_phy_mode2 = 3317 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3318 int fix_phy_mode4 = 3319 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3320 u32 m2, m3; 3321 3322 if (fix_phy_mode2) { 3323 m2 = readl(port_mmio + PHY_MODE2); 3324 m2 &= ~(1 << 16); 3325 m2 |= (1 << 31); 3326 writel(m2, port_mmio + PHY_MODE2); 3327 3328 udelay(200); 3329 3330 m2 = readl(port_mmio + PHY_MODE2); 3331 m2 &= ~((1 << 16) | (1 << 31)); 3332 writel(m2, port_mmio + PHY_MODE2); 3333 3334 udelay(200); 3335 } 3336 3337 /* 3338 * Gen-II/IIe PHY_MODE3 errata RM#2: 3339 * Achieves better receiver noise performance than the h/w default: 3340 */ 3341 m3 = readl(port_mmio + PHY_MODE3); 3342 m3 = (m3 & 0x1f) | (0x5555601 << 5); 3343 3344 /* Guideline 88F5182 (GL# SATA-S11) */ 3345 if (IS_SOC(hpriv)) 3346 m3 &= ~0x1c; 3347 3348 if (fix_phy_mode4) { 3349 u32 m4 = readl(port_mmio + PHY_MODE4); 3350 /* 3351 * Enforce reserved-bit restrictions on GenIIe devices only. 3352 * For earlier chipsets, force only the internal config field 3353 * (workaround for errata FEr SATA#10 part 1). 3354 */ 3355 if (IS_GEN_IIE(hpriv)) 3356 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3357 else 3358 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 3359 writel(m4, port_mmio + PHY_MODE4); 3360 } 3361 /* 3362 * Workaround for 60x1-B2 errata SATA#13: 3363 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3364 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3365 * Or ensure we use writelfl() when writing PHY_MODE4. 3366 */ 3367 writel(m3, port_mmio + PHY_MODE3); 3368 3369 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3370 m2 = readl(port_mmio + PHY_MODE2); 3371 3372 m2 &= ~MV_M2_PREAMP_MASK; 3373 m2 |= hpriv->signal[port].amps; 3374 m2 |= hpriv->signal[port].pre; 3375 m2 &= ~(1 << 16); 3376 3377 /* according to mvSata 3.6.1, some IIE values are fixed */ 3378 if (IS_GEN_IIE(hpriv)) { 3379 m2 &= ~0xC30FF01F; 3380 m2 |= 0x0000900F; 3381 } 3382 3383 writel(m2, port_mmio + PHY_MODE2); 3384 } 3385 3386 /* 3387 * Enable the SoC SATA LED controller and device presence 3388 * indication on the board's SATA LEDs. 3389 */ 3390 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3391 void __iomem *mmio) 3392 { 3393 writel(SOC_LED_CTRL_ENABLE | SOC_LED_CTRL_ACT_PRESENCE, 3394 mv_hc_base(mmio, 0) + SOC_LED_CTRL); 3395 } 3396 3397 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3398 void __iomem *mmio) 3399 { 3400 void __iomem *port_mmio; 3401 u32 tmp; 3402 3403 port_mmio = mv_port_base(mmio, idx); 3404 tmp = readl(port_mmio + PHY_MODE2); 3405 3406 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3407 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3408 } 3409 3410 #undef ZERO 3411 #define ZERO(reg) writel(0, port_mmio + (reg)) 3412 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3413 void __iomem *mmio, unsigned int port) 3414 { 3415 void __iomem *port_mmio = mv_port_base(mmio, port); 3416 3417 mv_reset_channel(hpriv, mmio, port); 3418 3419 ZERO(0x028); /* command */ 3420 writel(0x101f, port_mmio + EDMA_CFG); 3421 ZERO(0x004); /* timer */ 3422 ZERO(0x008); /* irq err cause */ 3423 ZERO(0x00c); /* irq err mask */ 3424 ZERO(0x010); /* rq bah */ 3425 ZERO(0x014); /* rq inp */ 3426 ZERO(0x018); /* rq outp */ 3427 ZERO(0x01c); /* respq bah */ 3428 ZERO(0x024); /* respq outp */ 3429 ZERO(0x020); /* respq inp */ 3430 ZERO(0x02c); /* test control */ 3431 writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3432 } 3433 3434 #undef ZERO 3435 3436 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3437 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3438 void __iomem *mmio) 3439 { 3440 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3441 3442 ZERO(0x00c); 3443 ZERO(0x010); 3444 ZERO(0x014); 3445 3446 } 3447 3448 #undef ZERO 3449 3450 static int mv_soc_reset_hc(struct ata_host *host, 3451 void __iomem *mmio, unsigned int n_hc) 3452 { 3453 struct mv_host_priv *hpriv = host->private_data; 3454 unsigned int port; 3455 3456 for (port = 0; port < hpriv->n_ports; port++) 3457 mv_soc_reset_hc_port(hpriv, mmio, port); 3458 3459 mv_soc_reset_one_hc(hpriv, mmio); 3460 3461 return 0; 3462 } 3463 3464 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3465 void __iomem *mmio) 3466 { 3467 return; 3468 } 3469 3470 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3471 { 3472 return; 3473 } 3474 3475 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 3476 void __iomem *mmio, unsigned int port) 3477 { 3478 void __iomem *port_mmio = mv_port_base(mmio, port); 3479 u32 reg; 3480 3481 reg = readl(port_mmio + PHY_MODE3); 3482 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 3483 reg |= (0x1 << 27); 3484 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 3485 reg |= (0x1 << 29); 3486 writel(reg, port_mmio + PHY_MODE3); 3487 3488 reg = readl(port_mmio + PHY_MODE4); 3489 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 3490 reg |= (0x1 << 16); 3491 writel(reg, port_mmio + PHY_MODE4); 3492 3493 reg = readl(port_mmio + PHY_MODE9_GEN2); 3494 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3495 reg |= 0x8; 3496 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3497 writel(reg, port_mmio + PHY_MODE9_GEN2); 3498 3499 reg = readl(port_mmio + PHY_MODE9_GEN1); 3500 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3501 reg |= 0x8; 3502 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3503 writel(reg, port_mmio + PHY_MODE9_GEN1); 3504 } 3505 3506 /* 3507 * soc_is_65 - check if the soc is 65 nano device 3508 * 3509 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 3510 * register, this register should contain non-zero value and it exists only 3511 * in the 65 nano devices, when reading it from older devices we get 0. 3512 */ 3513 static bool soc_is_65n(struct mv_host_priv *hpriv) 3514 { 3515 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 3516 3517 if (readl(port0_mmio + PHYCFG_OFS)) 3518 return true; 3519 return false; 3520 } 3521 3522 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3523 { 3524 u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3525 3526 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3527 if (want_gen2i) 3528 ifcfg |= (1 << 7); /* enable gen2i speed */ 3529 writelfl(ifcfg, port_mmio + SATA_IFCFG); 3530 } 3531 3532 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3533 unsigned int port_no) 3534 { 3535 void __iomem *port_mmio = mv_port_base(mmio, port_no); 3536 3537 /* 3538 * The datasheet warns against setting EDMA_RESET when EDMA is active 3539 * (but doesn't say what the problem might be). So we first try 3540 * to disable the EDMA engine before doing the EDMA_RESET operation. 3541 */ 3542 mv_stop_edma_engine(port_mmio); 3543 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3544 3545 if (!IS_GEN_I(hpriv)) { 3546 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 3547 mv_setup_ifcfg(port_mmio, 1); 3548 } 3549 /* 3550 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3551 * link, and physical layers. It resets all SATA interface registers 3552 * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3553 */ 3554 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3555 udelay(25); /* allow reset propagation */ 3556 writelfl(0, port_mmio + EDMA_CMD); 3557 3558 hpriv->ops->phy_errata(hpriv, mmio, port_no); 3559 3560 if (IS_GEN_I(hpriv)) 3561 usleep_range(500, 1000); 3562 } 3563 3564 static void mv_pmp_select(struct ata_port *ap, int pmp) 3565 { 3566 if (sata_pmp_supported(ap)) { 3567 void __iomem *port_mmio = mv_ap_base(ap); 3568 u32 reg = readl(port_mmio + SATA_IFCTL); 3569 int old = reg & 0xf; 3570 3571 if (old != pmp) { 3572 reg = (reg & ~0xf) | pmp; 3573 writelfl(reg, port_mmio + SATA_IFCTL); 3574 } 3575 } 3576 } 3577 3578 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3579 unsigned long deadline) 3580 { 3581 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3582 return sata_std_hardreset(link, class, deadline); 3583 } 3584 3585 static int mv_softreset(struct ata_link *link, unsigned int *class, 3586 unsigned long deadline) 3587 { 3588 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3589 return ata_sff_softreset(link, class, deadline); 3590 } 3591 3592 static int mv_hardreset(struct ata_link *link, unsigned int *class, 3593 unsigned long deadline) 3594 { 3595 struct ata_port *ap = link->ap; 3596 struct mv_host_priv *hpriv = ap->host->private_data; 3597 struct mv_port_priv *pp = ap->private_data; 3598 void __iomem *mmio = hpriv->base; 3599 int rc, attempts = 0, extra = 0; 3600 u32 sstatus; 3601 bool online; 3602 3603 mv_reset_channel(hpriv, mmio, ap->port_no); 3604 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3605 pp->pp_flags &= 3606 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3607 3608 /* Workaround for errata FEr SATA#10 (part 2) */ 3609 do { 3610 const unsigned int *timing = 3611 sata_ehc_deb_timing(&link->eh_context); 3612 3613 rc = sata_link_hardreset(link, timing, deadline + extra, 3614 &online, NULL); 3615 rc = online ? -EAGAIN : rc; 3616 if (rc) 3617 return rc; 3618 sata_scr_read(link, SCR_STATUS, &sstatus); 3619 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 3620 /* Force 1.5gb/s link speed and try again */ 3621 mv_setup_ifcfg(mv_ap_base(ap), 0); 3622 if (time_after(jiffies + HZ, deadline)) 3623 extra = HZ; /* only extend it once, max */ 3624 } 3625 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 3626 mv_save_cached_regs(ap); 3627 mv_edma_cfg(ap, 0, 0); 3628 3629 return rc; 3630 } 3631 3632 static void mv_eh_freeze(struct ata_port *ap) 3633 { 3634 mv_stop_edma(ap); 3635 mv_enable_port_irqs(ap, 0); 3636 } 3637 3638 static void mv_eh_thaw(struct ata_port *ap) 3639 { 3640 struct mv_host_priv *hpriv = ap->host->private_data; 3641 unsigned int port = ap->port_no; 3642 unsigned int hardport = mv_hardport_from_port(port); 3643 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3644 void __iomem *port_mmio = mv_ap_base(ap); 3645 u32 hc_irq_cause; 3646 3647 /* clear EDMA errors on this port */ 3648 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3649 3650 /* clear pending irq events */ 3651 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3652 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3653 3654 mv_enable_port_irqs(ap, ERR_IRQ); 3655 } 3656 3657 /** 3658 * mv_port_init - Perform some early initialization on a single port. 3659 * @port: libata data structure storing shadow register addresses 3660 * @port_mmio: base address of the port 3661 * 3662 * Initialize shadow register mmio addresses, clear outstanding 3663 * interrupts on the port, and unmask interrupts for the future 3664 * start of the port. 3665 * 3666 * LOCKING: 3667 * Inherited from caller. 3668 */ 3669 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 3670 { 3671 void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 3672 3673 /* PIO related setup 3674 */ 3675 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 3676 port->error_addr = 3677 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 3678 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 3679 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 3680 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 3681 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 3682 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 3683 port->status_addr = 3684 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 3685 /* special case: control/altstatus doesn't have ATA_REG_ address */ 3686 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 3687 3688 /* Clear any currently outstanding port interrupt conditions */ 3689 serr = port_mmio + mv_scr_offset(SCR_ERROR); 3690 writelfl(readl(serr), serr); 3691 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3692 3693 /* unmask all non-transient EDMA error interrupts */ 3694 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 3695 } 3696 3697 static unsigned int mv_in_pcix_mode(struct ata_host *host) 3698 { 3699 struct mv_host_priv *hpriv = host->private_data; 3700 void __iomem *mmio = hpriv->base; 3701 u32 reg; 3702 3703 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3704 return 0; /* not PCI-X capable */ 3705 reg = readl(mmio + MV_PCI_MODE); 3706 if ((reg & MV_PCI_MODE_MASK) == 0) 3707 return 0; /* conventional PCI mode */ 3708 return 1; /* chip is in PCI-X mode */ 3709 } 3710 3711 static int mv_pci_cut_through_okay(struct ata_host *host) 3712 { 3713 struct mv_host_priv *hpriv = host->private_data; 3714 void __iomem *mmio = hpriv->base; 3715 u32 reg; 3716 3717 if (!mv_in_pcix_mode(host)) { 3718 reg = readl(mmio + MV_PCI_COMMAND); 3719 if (reg & MV_PCI_COMMAND_MRDTRIG) 3720 return 0; /* not okay */ 3721 } 3722 return 1; /* okay */ 3723 } 3724 3725 static void mv_60x1b2_errata_pci7(struct ata_host *host) 3726 { 3727 struct mv_host_priv *hpriv = host->private_data; 3728 void __iomem *mmio = hpriv->base; 3729 3730 /* workaround for 60x1-B2 errata PCI#7 */ 3731 if (mv_in_pcix_mode(host)) { 3732 u32 reg = readl(mmio + MV_PCI_COMMAND); 3733 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 3734 } 3735 } 3736 3737 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3738 { 3739 struct pci_dev *pdev = to_pci_dev(host->dev); 3740 struct mv_host_priv *hpriv = host->private_data; 3741 u32 hp_flags = hpriv->hp_flags; 3742 3743 switch (board_idx) { 3744 case chip_5080: 3745 hpriv->ops = &mv5xxx_ops; 3746 hp_flags |= MV_HP_GEN_I; 3747 3748 switch (pdev->revision) { 3749 case 0x1: 3750 hp_flags |= MV_HP_ERRATA_50XXB0; 3751 break; 3752 case 0x3: 3753 hp_flags |= MV_HP_ERRATA_50XXB2; 3754 break; 3755 default: 3756 dev_warn(&pdev->dev, 3757 "Applying 50XXB2 workarounds to unknown rev\n"); 3758 hp_flags |= MV_HP_ERRATA_50XXB2; 3759 break; 3760 } 3761 break; 3762 3763 case chip_504x: 3764 case chip_508x: 3765 hpriv->ops = &mv5xxx_ops; 3766 hp_flags |= MV_HP_GEN_I; 3767 3768 switch (pdev->revision) { 3769 case 0x0: 3770 hp_flags |= MV_HP_ERRATA_50XXB0; 3771 break; 3772 case 0x3: 3773 hp_flags |= MV_HP_ERRATA_50XXB2; 3774 break; 3775 default: 3776 dev_warn(&pdev->dev, 3777 "Applying B2 workarounds to unknown rev\n"); 3778 hp_flags |= MV_HP_ERRATA_50XXB2; 3779 break; 3780 } 3781 break; 3782 3783 case chip_604x: 3784 case chip_608x: 3785 hpriv->ops = &mv6xxx_ops; 3786 hp_flags |= MV_HP_GEN_II; 3787 3788 switch (pdev->revision) { 3789 case 0x7: 3790 mv_60x1b2_errata_pci7(host); 3791 hp_flags |= MV_HP_ERRATA_60X1B2; 3792 break; 3793 case 0x9: 3794 hp_flags |= MV_HP_ERRATA_60X1C0; 3795 break; 3796 default: 3797 dev_warn(&pdev->dev, 3798 "Applying B2 workarounds to unknown rev\n"); 3799 hp_flags |= MV_HP_ERRATA_60X1B2; 3800 break; 3801 } 3802 break; 3803 3804 case chip_7042: 3805 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3806 if (pdev->vendor == PCI_VENDOR_ID_TTI && 3807 (pdev->device == 0x2300 || pdev->device == 0x2310)) 3808 { 3809 /* 3810 * Highpoint RocketRAID PCIe 23xx series cards: 3811 * 3812 * Unconfigured drives are treated as "Legacy" 3813 * by the BIOS, and it overwrites sector 8 with 3814 * a "Lgcy" metadata block prior to Linux boot. 3815 * 3816 * Configured drives (RAID or JBOD) leave sector 8 3817 * alone, but instead overwrite a high numbered 3818 * sector for the RAID metadata. This sector can 3819 * be determined exactly, by truncating the physical 3820 * drive capacity to a nice even GB value. 3821 * 3822 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 3823 * 3824 * Warn the user, lest they think we're just buggy. 3825 */ 3826 dev_warn(&pdev->dev, "Highpoint RocketRAID" 3827 " BIOS CORRUPTS DATA on all attached drives," 3828 " regardless of if/how they are configured." 3829 " BEWARE!\n"); 3830 dev_warn(&pdev->dev, "For data safety, do not" 3831 " use sectors 8-9 on \"Legacy\" drives," 3832 " and avoid the final two gigabytes on" 3833 " all RocketRAID BIOS initialized drives.\n"); 3834 } 3835 fallthrough; 3836 case chip_6042: 3837 hpriv->ops = &mv6xxx_ops; 3838 hp_flags |= MV_HP_GEN_IIE; 3839 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3840 hp_flags |= MV_HP_CUT_THROUGH; 3841 3842 switch (pdev->revision) { 3843 case 0x2: /* Rev.B0: the first/only public release */ 3844 hp_flags |= MV_HP_ERRATA_60X1C0; 3845 break; 3846 default: 3847 dev_warn(&pdev->dev, 3848 "Applying 60X1C0 workarounds to unknown rev\n"); 3849 hp_flags |= MV_HP_ERRATA_60X1C0; 3850 break; 3851 } 3852 break; 3853 case chip_soc: 3854 if (soc_is_65n(hpriv)) 3855 hpriv->ops = &mv_soc_65n_ops; 3856 else 3857 hpriv->ops = &mv_soc_ops; 3858 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3859 MV_HP_ERRATA_60X1C0; 3860 break; 3861 3862 default: 3863 dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx); 3864 return -EINVAL; 3865 } 3866 3867 hpriv->hp_flags = hp_flags; 3868 if (hp_flags & MV_HP_PCIE) { 3869 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3870 hpriv->irq_mask_offset = PCIE_IRQ_MASK; 3871 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3872 } else { 3873 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3874 hpriv->irq_mask_offset = PCI_IRQ_MASK; 3875 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3876 } 3877 3878 return 0; 3879 } 3880 3881 /** 3882 * mv_init_host - Perform some early initialization of the host. 3883 * @host: ATA host to initialize 3884 * 3885 * If possible, do an early global reset of the host. Then do 3886 * our port init and clear/unmask all/relevant host interrupts. 3887 * 3888 * LOCKING: 3889 * Inherited from caller. 3890 */ 3891 static int mv_init_host(struct ata_host *host) 3892 { 3893 int rc = 0, n_hc, port, hc; 3894 struct mv_host_priv *hpriv = host->private_data; 3895 void __iomem *mmio = hpriv->base; 3896 3897 rc = mv_chip_id(host, hpriv->board_idx); 3898 if (rc) 3899 goto done; 3900 3901 if (IS_SOC(hpriv)) { 3902 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3903 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 3904 } else { 3905 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3906 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3907 } 3908 3909 /* initialize shadow irq mask with register's value */ 3910 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 3911 3912 /* global interrupt mask: 0 == mask everything */ 3913 mv_set_main_irq_mask(host, ~0, 0); 3914 3915 n_hc = mv_get_hc_count(host->ports[0]->flags); 3916 3917 for (port = 0; port < host->n_ports; port++) 3918 if (hpriv->ops->read_preamp) 3919 hpriv->ops->read_preamp(hpriv, port, mmio); 3920 3921 rc = hpriv->ops->reset_hc(host, mmio, n_hc); 3922 if (rc) 3923 goto done; 3924 3925 hpriv->ops->reset_flash(hpriv, mmio); 3926 hpriv->ops->reset_bus(host, mmio); 3927 hpriv->ops->enable_leds(hpriv, mmio); 3928 3929 for (port = 0; port < host->n_ports; port++) { 3930 struct ata_port *ap = host->ports[port]; 3931 void __iomem *port_mmio = mv_port_base(mmio, port); 3932 3933 mv_port_init(&ap->ioaddr, port_mmio); 3934 } 3935 3936 for (hc = 0; hc < n_hc; hc++) { 3937 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3938 3939 dev_dbg(host->dev, "HC%i: HC config=0x%08x HC IRQ cause " 3940 "(before clear)=0x%08x\n", hc, 3941 readl(hc_mmio + HC_CFG), 3942 readl(hc_mmio + HC_IRQ_CAUSE)); 3943 3944 /* Clear any currently outstanding hc interrupt conditions */ 3945 writelfl(0, hc_mmio + HC_IRQ_CAUSE); 3946 } 3947 3948 if (!IS_SOC(hpriv)) { 3949 /* Clear any currently outstanding host interrupt conditions */ 3950 writelfl(0, mmio + hpriv->irq_cause_offset); 3951 3952 /* and unmask interrupt generation for host regs */ 3953 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 3954 } 3955 3956 /* 3957 * enable only global host interrupts for now. 3958 * The per-port interrupts get done later as ports are set up. 3959 */ 3960 mv_set_main_irq_mask(host, 0, PCI_ERR); 3961 mv_set_irq_coalescing(host, irq_coalescing_io_count, 3962 irq_coalescing_usecs); 3963 done: 3964 return rc; 3965 } 3966 3967 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3968 { 3969 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3970 MV_CRQB_Q_SZ, 0); 3971 if (!hpriv->crqb_pool) 3972 return -ENOMEM; 3973 3974 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3975 MV_CRPB_Q_SZ, 0); 3976 if (!hpriv->crpb_pool) 3977 return -ENOMEM; 3978 3979 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3980 MV_SG_TBL_SZ, 0); 3981 if (!hpriv->sg_tbl_pool) 3982 return -ENOMEM; 3983 3984 return 0; 3985 } 3986 3987 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 3988 const struct mbus_dram_target_info *dram) 3989 { 3990 int i; 3991 3992 for (i = 0; i < 4; i++) { 3993 writel(0, hpriv->base + WINDOW_CTRL(i)); 3994 writel(0, hpriv->base + WINDOW_BASE(i)); 3995 } 3996 3997 for (i = 0; i < dram->num_cs; i++) { 3998 const struct mbus_dram_window *cs = dram->cs + i; 3999 4000 writel(((cs->size - 1) & 0xffff0000) | 4001 (cs->mbus_attr << 8) | 4002 (dram->mbus_dram_target_id << 4) | 1, 4003 hpriv->base + WINDOW_CTRL(i)); 4004 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 4005 } 4006 } 4007 4008 /** 4009 * mv_platform_probe - handle a positive probe of an soc Marvell 4010 * host 4011 * @pdev: platform device found 4012 * 4013 * LOCKING: 4014 * Inherited from caller. 4015 */ 4016 static int mv_platform_probe(struct platform_device *pdev) 4017 { 4018 const struct mv_sata_platform_data *mv_platform_data; 4019 const struct mbus_dram_target_info *dram; 4020 const struct ata_port_info *ppi[] = 4021 { &mv_port_info[chip_soc], NULL }; 4022 struct ata_host *host; 4023 struct mv_host_priv *hpriv; 4024 struct resource *res; 4025 int n_ports = 0, irq = 0; 4026 int rc; 4027 int port; 4028 4029 ata_print_version_once(&pdev->dev, DRV_VERSION); 4030 4031 /* 4032 * Simple resource validation .. 4033 */ 4034 if (unlikely(pdev->num_resources != 1 && pdev->num_resources != 2)) { 4035 dev_err(&pdev->dev, "invalid number of resources\n"); 4036 return -EINVAL; 4037 } 4038 4039 /* 4040 * Get the register base first 4041 */ 4042 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4043 if (res == NULL) 4044 return -EINVAL; 4045 4046 /* allocate host */ 4047 if (pdev->dev.of_node) { 4048 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", 4049 &n_ports); 4050 if (rc) { 4051 dev_err(&pdev->dev, 4052 "error parsing nr-ports property: %d\n", rc); 4053 return rc; 4054 } 4055 4056 if (n_ports <= 0) { 4057 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", 4058 n_ports); 4059 return -EINVAL; 4060 } 4061 } else { 4062 mv_platform_data = dev_get_platdata(&pdev->dev); 4063 n_ports = mv_platform_data->n_ports; 4064 } 4065 irq = platform_get_irq(pdev, 0); 4066 if (irq < 0) 4067 return irq; 4068 4069 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4070 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4071 4072 if (!host || !hpriv) 4073 return -ENOMEM; 4074 hpriv->port_clks = devm_kcalloc(&pdev->dev, 4075 n_ports, sizeof(struct clk *), 4076 GFP_KERNEL); 4077 if (!hpriv->port_clks) 4078 return -ENOMEM; 4079 hpriv->port_phys = devm_kcalloc(&pdev->dev, 4080 n_ports, sizeof(struct phy *), 4081 GFP_KERNEL); 4082 if (!hpriv->port_phys) 4083 return -ENOMEM; 4084 host->private_data = hpriv; 4085 hpriv->board_idx = chip_soc; 4086 4087 host->iomap = NULL; 4088 hpriv->base = devm_ioremap(&pdev->dev, res->start, 4089 resource_size(res)); 4090 if (!hpriv->base) 4091 return -ENOMEM; 4092 4093 hpriv->base -= SATAHC0_REG_BASE; 4094 4095 hpriv->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 4096 if (IS_ERR(hpriv->clk)) 4097 return PTR_ERR(hpriv->clk); 4098 4099 for (port = 0; port < n_ports; port++) { 4100 char port_number[16]; 4101 sprintf(port_number, "%d", port); 4102 hpriv->port_clks[port] = devm_clk_get_optional_enabled(&pdev->dev, port_number); 4103 if (IS_ERR(hpriv->port_clks[port])) { 4104 rc = PTR_ERR(hpriv->port_clks[port]); 4105 hpriv->n_ports = port; 4106 goto err; 4107 } 4108 4109 sprintf(port_number, "port%d", port); 4110 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, 4111 port_number); 4112 if (IS_ERR(hpriv->port_phys[port])) { 4113 rc = PTR_ERR(hpriv->port_phys[port]); 4114 hpriv->port_phys[port] = NULL; 4115 if (rc != -EPROBE_DEFER) 4116 dev_warn(&pdev->dev, "error getting phy %d", rc); 4117 4118 /* Cleanup only the initialized ports */ 4119 hpriv->n_ports = port; 4120 goto err; 4121 } 4122 phy_power_on(hpriv->port_phys[port]); 4123 } 4124 4125 /* All the ports have been initialized */ 4126 hpriv->n_ports = n_ports; 4127 4128 /* 4129 * (Re-)program MBUS remapping windows if we are asked to. 4130 */ 4131 dram = mv_mbus_dram_info(); 4132 if (dram) 4133 mv_conf_mbus_windows(hpriv, dram); 4134 4135 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4136 if (rc) 4137 goto err; 4138 4139 /* 4140 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be 4141 * updated in the LP_PHY_CTL register. 4142 */ 4143 if (pdev->dev.of_node && 4144 of_device_is_compatible(pdev->dev.of_node, 4145 "marvell,armada-370-sata")) 4146 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; 4147 4148 /* initialize adapter */ 4149 rc = mv_init_host(host); 4150 if (rc) 4151 goto err; 4152 4153 dev_info(&pdev->dev, "slots %u ports %d\n", 4154 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); 4155 4156 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht); 4157 if (!rc) 4158 return 0; 4159 4160 err: 4161 for (port = 0; port < hpriv->n_ports; port++) 4162 phy_power_off(hpriv->port_phys[port]); 4163 4164 return rc; 4165 } 4166 4167 /* 4168 * 4169 * mv_platform_remove - unplug a platform interface 4170 * @pdev: platform device 4171 * 4172 * A platform bus SATA device has been unplugged. Perform the needed 4173 * cleanup. Also called on module unload for any active devices. 4174 */ 4175 static void mv_platform_remove(struct platform_device *pdev) 4176 { 4177 struct ata_host *host = platform_get_drvdata(pdev); 4178 struct mv_host_priv *hpriv = host->private_data; 4179 int port; 4180 ata_host_detach(host); 4181 4182 for (port = 0; port < host->n_ports; port++) 4183 phy_power_off(hpriv->port_phys[port]); 4184 } 4185 4186 #ifdef CONFIG_PM_SLEEP 4187 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 4188 { 4189 struct ata_host *host = platform_get_drvdata(pdev); 4190 4191 if (host) 4192 ata_host_suspend(host, state); 4193 return 0; 4194 } 4195 4196 static int mv_platform_resume(struct platform_device *pdev) 4197 { 4198 struct ata_host *host = platform_get_drvdata(pdev); 4199 const struct mbus_dram_target_info *dram; 4200 int ret; 4201 4202 if (host) { 4203 struct mv_host_priv *hpriv = host->private_data; 4204 4205 /* 4206 * (Re-)program MBUS remapping windows if we are asked to. 4207 */ 4208 dram = mv_mbus_dram_info(); 4209 if (dram) 4210 mv_conf_mbus_windows(hpriv, dram); 4211 4212 /* initialize adapter */ 4213 ret = mv_init_host(host); 4214 if (ret) { 4215 dev_err(&pdev->dev, "Error during HW init\n"); 4216 return ret; 4217 } 4218 ata_host_resume(host); 4219 } 4220 4221 return 0; 4222 } 4223 #else 4224 #define mv_platform_suspend NULL 4225 #define mv_platform_resume NULL 4226 #endif 4227 4228 #ifdef CONFIG_OF 4229 static const struct of_device_id mv_sata_dt_ids[] = { 4230 { .compatible = "marvell,armada-370-sata", }, 4231 { .compatible = "marvell,orion-sata", }, 4232 { /* sentinel */ } 4233 }; 4234 MODULE_DEVICE_TABLE(of, mv_sata_dt_ids); 4235 #endif 4236 4237 static struct platform_driver mv_platform_driver = { 4238 .probe = mv_platform_probe, 4239 .remove = mv_platform_remove, 4240 .suspend = mv_platform_suspend, 4241 .resume = mv_platform_resume, 4242 .driver = { 4243 .name = DRV_NAME, 4244 .of_match_table = of_match_ptr(mv_sata_dt_ids), 4245 }, 4246 }; 4247 4248 4249 #ifdef CONFIG_PCI 4250 static int mv_pci_init_one(struct pci_dev *pdev, 4251 const struct pci_device_id *ent); 4252 #ifdef CONFIG_PM_SLEEP 4253 static int mv_pci_device_resume(struct pci_dev *pdev); 4254 #endif 4255 4256 static const struct pci_device_id mv_pci_tbl[] = { 4257 { PCI_VDEVICE(MARVELL, 0x5040), .driver_data = chip_504x }, 4258 { PCI_VDEVICE(MARVELL, 0x5041), .driver_data = chip_504x }, 4259 { PCI_VDEVICE(MARVELL, 0x5080), .driver_data = chip_5080 }, 4260 { PCI_VDEVICE(MARVELL, 0x5081), .driver_data = chip_508x }, 4261 /* RocketRAID 1720/174x have different identifiers */ 4262 { PCI_VDEVICE(TTI, 0x1720), .driver_data = chip_6042 }, 4263 { PCI_VDEVICE(TTI, 0x1740), .driver_data = chip_6042 }, 4264 { PCI_VDEVICE(TTI, 0x1742), .driver_data = chip_6042 }, 4265 4266 { PCI_VDEVICE(MARVELL, 0x6040), .driver_data = chip_604x }, 4267 { PCI_VDEVICE(MARVELL, 0x6041), .driver_data = chip_604x }, 4268 { PCI_VDEVICE(MARVELL, 0x6042), .driver_data = chip_6042 }, 4269 { PCI_VDEVICE(MARVELL, 0x6080), .driver_data = chip_608x }, 4270 { PCI_VDEVICE(MARVELL, 0x6081), .driver_data = chip_608x }, 4271 4272 { PCI_VDEVICE(ADAPTEC2, 0x0241), .driver_data = chip_604x }, 4273 4274 /* Adaptec 1430SA */ 4275 { PCI_VDEVICE(ADAPTEC2, 0x0243), .driver_data = chip_7042 }, 4276 4277 /* Marvell 7042 support */ 4278 { PCI_VDEVICE(MARVELL, 0x7042), .driver_data = chip_7042 }, 4279 4280 /* Highpoint RocketRAID PCIe series */ 4281 { PCI_VDEVICE(TTI, 0x2300), .driver_data = chip_7042 }, 4282 { PCI_VDEVICE(TTI, 0x2310), .driver_data = chip_7042 }, 4283 4284 { } /* terminate list */ 4285 }; 4286 4287 static struct pci_driver mv_pci_driver = { 4288 .name = DRV_NAME, 4289 .id_table = mv_pci_tbl, 4290 .probe = mv_pci_init_one, 4291 .remove = ata_pci_remove_one, 4292 #ifdef CONFIG_PM_SLEEP 4293 .suspend = ata_pci_device_suspend, 4294 .resume = mv_pci_device_resume, 4295 #endif 4296 4297 }; 4298 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 4299 4300 /** 4301 * mv_print_info - Dump key info to kernel log for perusal. 4302 * @host: ATA host to print info about 4303 * 4304 * FIXME: complete this. 4305 * 4306 * LOCKING: 4307 * Inherited from caller. 4308 */ 4309 static void mv_print_info(struct ata_host *host) 4310 { 4311 struct pci_dev *pdev = to_pci_dev(host->dev); 4312 struct mv_host_priv *hpriv = host->private_data; 4313 u8 scc; 4314 const char *scc_s, *gen; 4315 4316 /* Use this to determine the HW stepping of the chip so we know 4317 * what errata to workaround 4318 */ 4319 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 4320 if (scc == 0) 4321 scc_s = "SCSI"; 4322 else if (scc == 0x01) 4323 scc_s = "RAID"; 4324 else 4325 scc_s = "?"; 4326 4327 if (IS_GEN_I(hpriv)) 4328 gen = "I"; 4329 else if (IS_GEN_II(hpriv)) 4330 gen = "II"; 4331 else if (IS_GEN_IIE(hpriv)) 4332 gen = "IIE"; 4333 else 4334 gen = "?"; 4335 4336 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4337 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 4338 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 4339 } 4340 4341 /** 4342 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 4343 * @pdev: PCI device found 4344 * @ent: PCI device ID entry for the matched host 4345 * 4346 * LOCKING: 4347 * Inherited from caller. 4348 */ 4349 static int mv_pci_init_one(struct pci_dev *pdev, 4350 const struct pci_device_id *ent) 4351 { 4352 unsigned int board_idx = (unsigned int)ent->driver_data; 4353 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 4354 struct ata_host *host; 4355 struct mv_host_priv *hpriv; 4356 int n_ports, port, rc; 4357 4358 ata_print_version_once(&pdev->dev, DRV_VERSION); 4359 4360 /* allocate host */ 4361 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 4362 4363 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4364 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4365 if (!host || !hpriv) 4366 return -ENOMEM; 4367 host->private_data = hpriv; 4368 hpriv->n_ports = n_ports; 4369 hpriv->board_idx = board_idx; 4370 4371 /* acquire resources */ 4372 rc = pcim_enable_device(pdev); 4373 if (rc) 4374 return rc; 4375 4376 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 4377 if (rc == -EBUSY) 4378 pcim_pin_device(pdev); 4379 if (rc) 4380 return rc; 4381 host->iomap = pcim_iomap_table(pdev); 4382 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 4383 4384 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 4385 if (rc) { 4386 dev_err(&pdev->dev, "DMA enable failed\n"); 4387 return rc; 4388 } 4389 4390 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4391 if (rc) 4392 return rc; 4393 4394 for (port = 0; port < host->n_ports; port++) { 4395 struct ata_port *ap = host->ports[port]; 4396 void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4397 unsigned int offset = port_mmio - hpriv->base; 4398 4399 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4400 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4401 } 4402 4403 /* initialize adapter */ 4404 rc = mv_init_host(host); 4405 if (rc) 4406 return rc; 4407 4408 /* Enable message-switched interrupts, if requested */ 4409 if (msi && pci_enable_msi(pdev) == 0) 4410 hpriv->hp_flags |= MV_HP_FLAG_MSI; 4411 4412 mv_dump_pci_cfg(pdev, 0x68); 4413 mv_print_info(host); 4414 4415 pci_set_master(pdev); 4416 pci_try_set_mwi(pdev); 4417 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4418 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 4419 } 4420 4421 #ifdef CONFIG_PM_SLEEP 4422 static int mv_pci_device_resume(struct pci_dev *pdev) 4423 { 4424 struct ata_host *host = pci_get_drvdata(pdev); 4425 int rc; 4426 4427 rc = ata_pci_device_do_resume(pdev); 4428 if (rc) 4429 return rc; 4430 4431 /* initialize adapter */ 4432 rc = mv_init_host(host); 4433 if (rc) 4434 return rc; 4435 4436 ata_host_resume(host); 4437 4438 return 0; 4439 } 4440 #endif 4441 #endif 4442 4443 static int __init mv_init(void) 4444 { 4445 int rc = -ENODEV; 4446 #ifdef CONFIG_PCI 4447 rc = pci_register_driver(&mv_pci_driver); 4448 if (rc < 0) 4449 return rc; 4450 #endif 4451 rc = platform_driver_register(&mv_platform_driver); 4452 4453 #ifdef CONFIG_PCI 4454 if (rc < 0) 4455 pci_unregister_driver(&mv_pci_driver); 4456 #endif 4457 return rc; 4458 } 4459 4460 static void __exit mv_exit(void) 4461 { 4462 #ifdef CONFIG_PCI 4463 pci_unregister_driver(&mv_pci_driver); 4464 #endif 4465 platform_driver_unregister(&mv_platform_driver); 4466 } 4467 4468 MODULE_AUTHOR("Brett Russ"); 4469 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 4470 MODULE_LICENSE("GPL v2"); 4471 MODULE_VERSION(DRV_VERSION); 4472 MODULE_ALIAS("platform:" DRV_NAME); 4473 4474 module_init(mv_init); 4475 module_exit(mv_exit); 4476