1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver 4 * 5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 6 */ 7 8 #ifndef _ROCKCHIP_SAI_H 9 #define _ROCKCHIP_SAI_H 10 11 /* XCR Transmit / Receive Control Register */ 12 #define SAI_XCR_START_SEL_MASK BIT(23) 13 #define SAI_XCR_START_SEL_CHAINED BIT(23) 14 #define SAI_XCR_START_SEL_STANDALONE 0 15 #define SAI_XCR_EDGE_SHIFT_MASK BIT(22) 16 #define SAI_XCR_EDGE_SHIFT_1 BIT(22) 17 #define SAI_XCR_EDGE_SHIFT_0 0 18 #define SAI_XCR_CSR_MASK GENMASK(21, 20) 19 #define SAI_XCR_CSR(x) ((x - 1) << 20) 20 #define SAI_XCR_CSR_V(v) ((((v) & SAI_XCR_CSR_MASK) >> 20) + 1) 21 #define SAI_XCR_SJM_MASK BIT(19) 22 #define SAI_XCR_SJM_L BIT(19) 23 #define SAI_XCR_SJM_R 0 24 #define SAI_XCR_FBM_MASK BIT(18) 25 #define SAI_XCR_FBM_LSB BIT(18) 26 #define SAI_XCR_FBM_MSB 0 27 #define SAI_XCR_SNB_MASK GENMASK(17, 11) 28 #define SAI_XCR_SNB(x) ((x - 1) << 11) 29 #define SAI_XCR_VDJ_MASK BIT(10) 30 #define SAI_XCR_VDJ_L BIT(10) 31 #define SAI_XCR_VDJ_R 0 32 #define SAI_XCR_SBW_MASK GENMASK(9, 5) 33 #define SAI_XCR_SBW(x) ((x - 1) << 5) 34 #define SAI_XCR_SBW_V(v) ((((v) & SAI_XCR_SBW_MASK) >> 5) + 1) 35 #define SAI_XCR_VDW_MASK GENMASK(4, 0) 36 #define SAI_XCR_VDW(x) ((x - 1) << 0) 37 38 /* FSCR Frame Sync Control Register */ 39 #define SAI_FSCR_EDGE_MASK BIT(24) 40 #define SAI_FSCR_EDGE_DUAL BIT(24) 41 #define SAI_FSCR_EDGE_RISING 0 42 #define SAI_FSCR_FPW_MASK GENMASK(23, 12) 43 #define SAI_FSCR_FPW(x) ((x - 1) << 12) 44 #define SAI_FSCR_FW_MASK GENMASK(11, 0) 45 #define SAI_FSCR_FW(x) ((x - 1) << 0) 46 #define SAI_FSCR_FW_V(v) ((((v) & SAI_FSCR_FW_MASK) >> 0) + 1) 47 48 /* MONO_CR Mono Control Register */ 49 #define SAI_MCR_RX_MONO_SLOT_MASK GENMASK(8, 2) 50 #define SAI_MCR_RX_MONO_SLOT_SEL(x) ((x - 1) << 2) 51 #define SAI_MCR_RX_MONO_MASK BIT(1) 52 #define SAI_MCR_RX_MONO_EN BIT(1) 53 #define SAI_MCR_RX_MONO_DIS 0 54 #define SAI_MCR_TX_MONO_MASK BIT(0) 55 #define SAI_MCR_TX_MONO_EN BIT(0) 56 #define SAI_MCR_TX_MONO_DIS 0 57 58 /* XFER Transfer Start Register */ 59 #define SAI_XFER_RX_IDLE BIT(8) 60 #define SAI_XFER_TX_IDLE BIT(7) 61 #define SAI_XFER_FS_IDLE BIT(6) 62 /* 63 * Used for TX only (VERSION >= SAI_VER_2311) 64 * 65 * SCLK/FSYNC auto gated when TX FIFO empty. 66 */ 67 #define SAI_XFER_TX_AUTO_MASK BIT(6) 68 #define SAI_XFER_TX_AUTO_EN BIT(6) 69 #define SAI_XFER_TX_AUTO_DIS 0 70 #define SAI_XFER_RX_CNT_MASK BIT(5) 71 #define SAI_XFER_RX_CNT_EN BIT(5) 72 #define SAI_XFER_RX_CNT_DIS 0 73 #define SAI_XFER_TX_CNT_MASK BIT(4) 74 #define SAI_XFER_TX_CNT_EN BIT(4) 75 #define SAI_XFER_TX_CNT_DIS 0 76 #define SAI_XFER_RXS_MASK BIT(3) 77 #define SAI_XFER_RXS_EN BIT(3) 78 #define SAI_XFER_RXS_DIS 0 79 #define SAI_XFER_TXS_MASK BIT(2) 80 #define SAI_XFER_TXS_EN BIT(2) 81 #define SAI_XFER_TXS_DIS 0 82 #define SAI_XFER_FSS_MASK BIT(1) 83 #define SAI_XFER_FSS_EN BIT(1) 84 #define SAI_XFER_FSS_DIS 0 85 #define SAI_XFER_CLK_MASK BIT(0) 86 #define SAI_XFER_CLK_EN BIT(0) 87 #define SAI_XFER_CLK_DIS 0 88 89 /* CLR Clear Logic Register */ 90 #define SAI_CLR_FCR BIT(3) /* TODO: what is this? */ 91 #define SAI_CLR_FSC BIT(2) 92 #define SAI_CLR_RXC BIT(1) 93 #define SAI_CLR_TXC BIT(0) 94 95 /* CKR Clock Generation Register */ 96 #define SAI_CKR_MDIV_MASK GENMASK(14, 3) 97 #define SAI_CKR_MDIV(x) ((x - 1) << 3) 98 #define SAI_CKR_MSS_MASK BIT(2) 99 #define SAI_CKR_MSS_SLAVE BIT(2) 100 #define SAI_CKR_MSS_MASTER 0 101 #define SAI_CKR_CKP_MASK BIT(1) 102 #define SAI_CKR_CKP_INVERTED BIT(1) 103 #define SAI_CKR_CKP_NORMAL 0 104 #define SAI_CKR_FSP_MASK BIT(0) 105 #define SAI_CKR_FSP_INVERTED BIT(0) 106 #define SAI_CKR_FSP_NORMAL 0 107 108 /* DMACR DMA Control Register */ 109 #define SAI_DMACR_RDE_MASK BIT(24) 110 #define SAI_DMACR_RDE(x) ((x) << 24) 111 #define SAI_DMACR_RDL_MASK GENMASK(20, 16) 112 #define SAI_DMACR_RDL(x) ((x - 1) << 16) 113 #define SAI_DMACR_RDL_V(v) ((((v) & SAI_DMACR_RDL_MASK) >> 16) + 1) 114 #define SAI_DMACR_TDE_MASK BIT(8) 115 #define SAI_DMACR_TDE(x) ((x) << 8) 116 #define SAI_DMACR_TDL_MASK GENMASK(4, 0) 117 #define SAI_DMACR_TDL(x) ((x) << 0) 118 #define SAI_DMACR_TDL_V(v) (((v) & SAI_DMACR_TDL_MASK) >> 0) 119 120 /* INTCR Interrupt Ctrl Register */ 121 #define SAI_INTCR_FSLOSTC BIT(28) 122 #define SAI_INTCR_FSLOST_MASK BIT(27) 123 #define SAI_INTCR_FSLOST(x) ((x) << 27) 124 #define SAI_INTCR_FSERRC BIT(26) 125 #define SAI_INTCR_FSERR_MASK BIT(25) 126 #define SAI_INTCR_FSERR(x) ((x) << 25) 127 #define SAI_INTCR_RXOIC BIT(18) 128 #define SAI_INTCR_RXOIE_MASK BIT(17) 129 #define SAI_INTCR_RXOIE(x) ((x) << 17) 130 #define SAI_INTCR_TXUIC BIT(2) 131 #define SAI_INTCR_TXUIE_MASK BIT(1) 132 #define SAI_INTCR_TXUIE(x) ((x) << 1) 133 134 /* INTSR Interrupt Status Register */ 135 #define SAI_INTSR_FSLOSTI_INA 0 136 #define SAI_INTSR_FSLOSTI_ACT BIT(19) 137 #define SAI_INTSR_FSERRI_INA 0 138 #define SAI_INTSR_FSERRI_ACT BIT(18) 139 #define SAI_INTSR_RXOI_INA 0 140 #define SAI_INTSR_RXOI_ACT BIT(17) 141 #define SAI_INTSR_TXUI_INA 0 142 #define SAI_INTSR_TXUI_ACT BIT(1) 143 144 /* PATH_SEL: Transfer / Receive Path Select Register */ 145 #define SAI_RX_PATH_SHIFT(x) (8 + (x) * 2) 146 #define SAI_RX_PATH_MASK(x) (0x3 << SAI_RX_PATH_SHIFT(x)) 147 #define SAI_RX_PATH(x, v) ((v) << SAI_RX_PATH_SHIFT(x)) 148 #define SAI_TX_PATH_SHIFT(x) (0 + (x) * 2) 149 #define SAI_TX_PATH_MASK(x) (0x3 << SAI_TX_PATH_SHIFT(x)) 150 #define SAI_TX_PATH(x, v) ((v) << SAI_TX_PATH_SHIFT(x)) 151 152 /* XSHIFT: Transfer / Receive Frame Sync Shift Register */ 153 154 /* 155 * TX-ONLY: LEFT Direction Feature 156 * +------------------------------------------------+ 157 * | DATA LEFTx (step: 0.5 cycle) | FSYNC Edge | 158 * +------------------------------------------------+ 159 */ 160 #define SAI_XSHIFT_LEFT_MASK GENMASK(25, 24) 161 #define SAI_XSHIFT_LEFT(x) ((x) << 24) 162 /* 163 * +------------------------------------------------+ 164 * | FSYNC Edge | DATA RIGHTx (step: 0.5 cycle) | 165 * +------------------------------------------------+ 166 */ 167 #define SAI_XSHIFT_RIGHT_MASK GENMASK(23, 0) 168 #define SAI_XSHIFT_RIGHT(x) (x) 169 170 /* XFIFOLR: Transfer / Receive FIFO Level Register */ 171 #define SAI_FIFOLR_XFL3_SHIFT 18 172 #define SAI_FIFOLR_XFL3_MASK GENMASK(23, 18) 173 #define SAI_FIFOLR_XFL2_SHIFT 12 174 #define SAI_FIFOLR_XFL2_MASK GENMASK(17, 12) 175 #define SAI_FIFOLR_XFL1_SHIFT 6 176 #define SAI_FIFOLR_XFL1_MASK GENMASK(11, 6) 177 #define SAI_FIFOLR_XFL0_SHIFT 0 178 #define SAI_FIFOLR_XFL0_MASK GENMASK(5, 0) 179 180 /* STATUS Status Register (VERSION >= SAI_VER_2307) */ 181 #define SAI_STATUS_RX_IDLE BIT(3) 182 #define SAI_STATUS_TX_IDLE BIT(2) 183 #define SAI_STATUS_FS_IDLE BIT(1) 184 185 /* VERSION */ 186 /* 187 * Updates: 188 * 189 * VERSION >= SAI_VER_2311 190 * 191 * Support Frame Sync xN (FSXN) 192 * Support Frame Sync Error Detect (FSE) 193 * Support Frame Sync Lost Detect (FSLOST) 194 * Support Force Clear (FCR) 195 * Support SAIn-Chained (e.g. SAI0-CLK-DATA + SAI3-DATA +...) 196 * Support Transmit Auto Gate Mode 197 * Support Timing Shift Left for TX 198 * 199 * Optimize SCLK/FSYNC Timing Alignment 200 * 201 * VERSION >= SAI_VER_2403 202 * 203 * Support Loopback LR Select (e.g. L:MIC R:LP) 204 * 205 */ 206 #define SAI_VER_2307 0x23073576 207 #define SAI_VER_2311 0x23112118 208 #define SAI_VER_2401 0x24013506 209 #define SAI_VER_2403 0x24031103 210 211 /* FS_TIMEOUT: Frame Sync Timeout Register */ 212 #define SAI_FS_TIMEOUT_VAL_MASK GENMASK(31, 1) 213 #define SAI_FS_TIMEOUT_VAL(x) ((x) << 1) 214 #define SAI_FS_TIMEOUT_EN_MASK BIT(0) 215 #define SAI_FS_TIMEOUT_EN(x) ((x) << 0) 216 217 /* SAI Registers */ 218 #define SAI_TXCR (0x0000) 219 #define SAI_FSCR (0x0004) 220 #define SAI_RXCR (0x0008) 221 #define SAI_MONO_CR (0x000c) 222 #define SAI_XFER (0x0010) 223 #define SAI_CLR (0x0014) 224 #define SAI_CKR (0x0018) 225 #define SAI_TXFIFOLR (0x001c) 226 #define SAI_RXFIFOLR (0x0020) 227 #define SAI_DMACR (0x0024) 228 #define SAI_INTCR (0x0028) 229 #define SAI_INTSR (0x002c) 230 #define SAI_TXDR (0x0030) 231 #define SAI_RXDR (0x0034) 232 #define SAI_PATH_SEL (0x0038) 233 #define SAI_TX_SLOT_MASK0 (0x003c) 234 #define SAI_TX_SLOT_MASK1 (0x0040) 235 #define SAI_TX_SLOT_MASK2 (0x0044) 236 #define SAI_TX_SLOT_MASK3 (0x0048) 237 #define SAI_RX_SLOT_MASK0 (0x004c) 238 #define SAI_RX_SLOT_MASK1 (0x0050) 239 #define SAI_RX_SLOT_MASK2 (0x0054) 240 #define SAI_RX_SLOT_MASK3 (0x0058) 241 #define SAI_TX_DATA_CNT (0x005c) 242 #define SAI_RX_DATA_CNT (0x0060) 243 #define SAI_TX_SHIFT (0x0064) 244 #define SAI_RX_SHIFT (0x0068) 245 #define SAI_STATUS (0x006c) 246 #define SAI_VERSION (0x0070) 247 #define SAI_FSXN (0x0074) 248 #define SAI_FS_TIMEOUT (0x0078) 249 #define SAI_LOOPBACK_LR (0x007c) 250 251 #endif /* _ROCKCHIP_SAI_H */ 252