1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2012 Samsung Electronics Co., Ltd 4 * http://www.samsung.com 5 */ 6 7 #ifndef __LINUX_MFD_SEC_IRQ_H 8 #define __LINUX_MFD_SEC_IRQ_H 9 10 enum s2mpa01_irq { 11 S2MPA01_IRQ_PWRONF, 12 S2MPA01_IRQ_PWRONR, 13 S2MPA01_IRQ_JIGONBF, 14 S2MPA01_IRQ_JIGONBR, 15 S2MPA01_IRQ_ACOKBF, 16 S2MPA01_IRQ_ACOKBR, 17 S2MPA01_IRQ_PWRON1S, 18 S2MPA01_IRQ_MRB, 19 20 S2MPA01_IRQ_RTC60S, 21 S2MPA01_IRQ_RTCA1, 22 S2MPA01_IRQ_RTCA0, 23 S2MPA01_IRQ_SMPL, 24 S2MPA01_IRQ_RTC1S, 25 S2MPA01_IRQ_WTSR, 26 27 S2MPA01_IRQ_INT120C, 28 S2MPA01_IRQ_INT140C, 29 S2MPA01_IRQ_LDO3_TSD, 30 S2MPA01_IRQ_B16_TSD, 31 S2MPA01_IRQ_B24_TSD, 32 S2MPA01_IRQ_B35_TSD, 33 34 S2MPA01_IRQ_NR, 35 }; 36 37 #define S2MPA01_IRQ_PWRONF_MASK (1 << 0) 38 #define S2MPA01_IRQ_PWRONR_MASK (1 << 1) 39 #define S2MPA01_IRQ_JIGONBF_MASK (1 << 2) 40 #define S2MPA01_IRQ_JIGONBR_MASK (1 << 3) 41 #define S2MPA01_IRQ_ACOKBF_MASK (1 << 4) 42 #define S2MPA01_IRQ_ACOKBR_MASK (1 << 5) 43 #define S2MPA01_IRQ_PWRON1S_MASK (1 << 6) 44 #define S2MPA01_IRQ_MRB_MASK (1 << 7) 45 46 #define S2MPA01_IRQ_RTC60S_MASK (1 << 0) 47 #define S2MPA01_IRQ_RTCA1_MASK (1 << 1) 48 #define S2MPA01_IRQ_RTCA0_MASK (1 << 2) 49 #define S2MPA01_IRQ_SMPL_MASK (1 << 3) 50 #define S2MPA01_IRQ_RTC1S_MASK (1 << 4) 51 #define S2MPA01_IRQ_WTSR_MASK (1 << 5) 52 53 #define S2MPA01_IRQ_INT120C_MASK (1 << 0) 54 #define S2MPA01_IRQ_INT140C_MASK (1 << 1) 55 #define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2) 56 #define S2MPA01_IRQ_B16_TSD_MASK (1 << 3) 57 #define S2MPA01_IRQ_B24_TSD_MASK (1 << 4) 58 #define S2MPA01_IRQ_B35_TSD_MASK (1 << 5) 59 60 enum s2mpg10_common_irq { 61 /* Top-level (common) block */ 62 S2MPG10_COMMON_IRQ_PMIC, 63 S2MPG10_COMMON_IRQ_UNUSED, 64 }; 65 66 enum s2mpg10_irq { 67 /* PMIC */ 68 S2MPG10_IRQ_PWRONF, 69 S2MPG10_IRQ_PWRONR, 70 S2MPG10_IRQ_JIGONBF, 71 S2MPG10_IRQ_JIGONBR, 72 S2MPG10_IRQ_ACOKBF, 73 S2MPG10_IRQ_ACOKBR, 74 S2MPG10_IRQ_PWRON1S, 75 S2MPG10_IRQ_MRB, 76 #define S2MPG10_IRQ_PWRONF_MASK BIT(0) 77 #define S2MPG10_IRQ_PWRONR_MASK BIT(1) 78 #define S2MPG10_IRQ_JIGONBF_MASK BIT(2) 79 #define S2MPG10_IRQ_JIGONBR_MASK BIT(3) 80 #define S2MPG10_IRQ_ACOKBF_MASK BIT(4) 81 #define S2MPG10_IRQ_ACOKBR_MASK BIT(5) 82 #define S2MPG10_IRQ_PWRON1S_MASK BIT(6) 83 #define S2MPG10_IRQ_MRB_MASK BIT(7) 84 85 S2MPG10_IRQ_RTC60S, 86 S2MPG10_IRQ_RTCA1, 87 S2MPG10_IRQ_RTCA0, 88 S2MPG10_IRQ_RTC1S, 89 S2MPG10_IRQ_WTSR_COLDRST, 90 S2MPG10_IRQ_WTSR, 91 S2MPG10_IRQ_WRST, 92 S2MPG10_IRQ_SMPL, 93 #define S2MPG10_IRQ_RTC60S_MASK BIT(0) 94 #define S2MPG10_IRQ_RTCA1_MASK BIT(1) 95 #define S2MPG10_IRQ_RTCA0_MASK BIT(2) 96 #define S2MPG10_IRQ_RTC1S_MASK BIT(3) 97 #define S2MPG10_IRQ_WTSR_COLDRST_MASK BIT(4) 98 #define S2MPG10_IRQ_WTSR_MASK BIT(5) 99 #define S2MPG10_IRQ_WRST_MASK BIT(6) 100 #define S2MPG10_IRQ_SMPL_MASK BIT(7) 101 102 S2MPG10_IRQ_120C, 103 S2MPG10_IRQ_140C, 104 S2MPG10_IRQ_TSD, 105 S2MPG10_IRQ_PIF_TIMEOUT1, 106 S2MPG10_IRQ_PIF_TIMEOUT2, 107 S2MPG10_IRQ_SPD_PARITY_ERR, 108 S2MPG10_IRQ_SPD_ABNORMAL_STOP, 109 S2MPG10_IRQ_PMETER_OVERF, 110 #define S2MPG10_IRQ_INT120C_MASK BIT(0) 111 #define S2MPG10_IRQ_INT140C_MASK BIT(1) 112 #define S2MPG10_IRQ_TSD_MASK BIT(2) 113 #define S2MPG10_IRQ_PIF_TIMEOUT1_MASK BIT(3) 114 #define S2MPG10_IRQ_PIF_TIMEOUT2_MASK BIT(4) 115 #define S2MPG10_IRQ_SPD_PARITY_ERR_MASK BIT(5) 116 #define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6) 117 #define S2MPG10_IRQ_PMETER_OVERF_MASK BIT(7) 118 119 S2MPG10_IRQ_OCP_B1M, 120 S2MPG10_IRQ_OCP_B2M, 121 S2MPG10_IRQ_OCP_B3M, 122 S2MPG10_IRQ_OCP_B4M, 123 S2MPG10_IRQ_OCP_B5M, 124 S2MPG10_IRQ_OCP_B6M, 125 S2MPG10_IRQ_OCP_B7M, 126 S2MPG10_IRQ_OCP_B8M, 127 #define S2MPG10_IRQ_OCP_B1M_MASK BIT(0) 128 #define S2MPG10_IRQ_OCP_B2M_MASK BIT(1) 129 #define S2MPG10_IRQ_OCP_B3M_MASK BIT(2) 130 #define S2MPG10_IRQ_OCP_B4M_MASK BIT(3) 131 #define S2MPG10_IRQ_OCP_B5M_MASK BIT(4) 132 #define S2MPG10_IRQ_OCP_B6M_MASK BIT(5) 133 #define S2MPG10_IRQ_OCP_B7M_MASK BIT(6) 134 #define S2MPG10_IRQ_OCP_B8M_MASK BIT(7) 135 136 S2MPG10_IRQ_OCP_B9M, 137 S2MPG10_IRQ_OCP_B10M, 138 S2MPG10_IRQ_WLWP_ACC, 139 S2MPG10_IRQ_SMPL_TIMEOUT, 140 S2MPG10_IRQ_WTSR_TIMEOUT, 141 S2MPG10_IRQ_SPD_SRP_PKT_RST, 142 #define S2MPG10_IRQ_OCP_B9M_MASK BIT(0) 143 #define S2MPG10_IRQ_OCP_B10M_MASK BIT(1) 144 #define S2MPG10_IRQ_WLWP_ACC_MASK BIT(2) 145 #define S2MPG10_IRQ_SMPL_TIMEOUT_MASK BIT(5) 146 #define S2MPG10_IRQ_WTSR_TIMEOUT_MASK BIT(6) 147 #define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK BIT(7) 148 149 S2MPG10_IRQ_PWR_WARN_CH0, 150 S2MPG10_IRQ_PWR_WARN_CH1, 151 S2MPG10_IRQ_PWR_WARN_CH2, 152 S2MPG10_IRQ_PWR_WARN_CH3, 153 S2MPG10_IRQ_PWR_WARN_CH4, 154 S2MPG10_IRQ_PWR_WARN_CH5, 155 S2MPG10_IRQ_PWR_WARN_CH6, 156 S2MPG10_IRQ_PWR_WARN_CH7, 157 #define S2MPG10_IRQ_PWR_WARN_CH0_MASK BIT(0) 158 #define S2MPG10_IRQ_PWR_WARN_CH1_MASK BIT(1) 159 #define S2MPG10_IRQ_PWR_WARN_CH2_MASK BIT(2) 160 #define S2MPG10_IRQ_PWR_WARN_CH3_MASK BIT(3) 161 #define S2MPG10_IRQ_PWR_WARN_CH4_MASK BIT(4) 162 #define S2MPG10_IRQ_PWR_WARN_CH5_MASK BIT(5) 163 #define S2MPG10_IRQ_PWR_WARN_CH6_MASK BIT(6) 164 #define S2MPG10_IRQ_PWR_WARN_CH7_MASK BIT(7) 165 166 S2MPG10_IRQ_NR, 167 }; 168 169 enum s2mps11_irq { 170 S2MPS11_IRQ_PWRONF, 171 S2MPS11_IRQ_PWRONR, 172 S2MPS11_IRQ_JIGONBF, 173 S2MPS11_IRQ_JIGONBR, 174 S2MPS11_IRQ_ACOKBF, 175 S2MPS11_IRQ_ACOKBR, 176 S2MPS11_IRQ_PWRON1S, 177 S2MPS11_IRQ_MRB, 178 179 S2MPS11_IRQ_RTC60S, 180 S2MPS11_IRQ_RTCA1, 181 S2MPS11_IRQ_RTCA0, 182 S2MPS11_IRQ_SMPL, 183 S2MPS11_IRQ_RTC1S, 184 S2MPS11_IRQ_WTSR, 185 186 S2MPS11_IRQ_INT120C, 187 S2MPS11_IRQ_INT140C, 188 189 S2MPS11_IRQ_NR, 190 }; 191 192 #define S2MPS11_IRQ_PWRONF_MASK (1 << 0) 193 #define S2MPS11_IRQ_PWRONR_MASK (1 << 1) 194 #define S2MPS11_IRQ_JIGONBF_MASK (1 << 2) 195 #define S2MPS11_IRQ_JIGONBR_MASK (1 << 3) 196 #define S2MPS11_IRQ_ACOKBF_MASK (1 << 4) 197 #define S2MPS11_IRQ_ACOKBR_MASK (1 << 5) 198 #define S2MPS11_IRQ_PWRON1S_MASK (1 << 6) 199 #define S2MPS11_IRQ_MRB_MASK (1 << 7) 200 201 #define S2MPS11_IRQ_RTC60S_MASK (1 << 0) 202 #define S2MPS11_IRQ_RTCA1_MASK (1 << 1) 203 #define S2MPS11_IRQ_RTCA0_MASK (1 << 2) 204 #define S2MPS11_IRQ_SMPL_MASK (1 << 3) 205 #define S2MPS11_IRQ_RTC1S_MASK (1 << 4) 206 #define S2MPS11_IRQ_WTSR_MASK (1 << 5) 207 208 #define S2MPS11_IRQ_INT120C_MASK (1 << 0) 209 #define S2MPS11_IRQ_INT140C_MASK (1 << 1) 210 211 enum s2mps14_irq { 212 S2MPS14_IRQ_PWRONF, 213 S2MPS14_IRQ_PWRONR, 214 S2MPS14_IRQ_JIGONBF, 215 S2MPS14_IRQ_JIGONBR, 216 S2MPS14_IRQ_ACOKBF, 217 S2MPS14_IRQ_ACOKBR, 218 S2MPS14_IRQ_PWRON1S, 219 S2MPS14_IRQ_MRB, 220 221 S2MPS14_IRQ_RTC60S, 222 S2MPS14_IRQ_RTCA1, 223 S2MPS14_IRQ_RTCA0, 224 S2MPS14_IRQ_SMPL, 225 S2MPS14_IRQ_RTC1S, 226 S2MPS14_IRQ_WTSR, 227 228 S2MPS14_IRQ_INT120C, 229 S2MPS14_IRQ_INT140C, 230 S2MPS14_IRQ_TSD, 231 232 S2MPS14_IRQ_NR, 233 }; 234 235 enum s2mpu02_irq { 236 S2MPU02_IRQ_PWRONF, 237 S2MPU02_IRQ_PWRONR, 238 S2MPU02_IRQ_JIGONBF, 239 S2MPU02_IRQ_JIGONBR, 240 S2MPU02_IRQ_ACOKBF, 241 S2MPU02_IRQ_ACOKBR, 242 S2MPU02_IRQ_PWRON1S, 243 S2MPU02_IRQ_MRB, 244 245 S2MPU02_IRQ_RTC60S, 246 S2MPU02_IRQ_RTCA1, 247 S2MPU02_IRQ_RTCA0, 248 S2MPU02_IRQ_SMPL, 249 S2MPU02_IRQ_RTC1S, 250 S2MPU02_IRQ_WTSR, 251 252 S2MPU02_IRQ_INT120C, 253 S2MPU02_IRQ_INT140C, 254 S2MPU02_IRQ_TSD, 255 256 S2MPU02_IRQ_NR, 257 }; 258 259 /* Masks for interrupts are the same as in s2mps11 */ 260 #define S2MPS14_IRQ_TSD_MASK (1 << 2) 261 262 enum s2mpu05_irq { 263 S2MPU05_IRQ_PWRONF, 264 S2MPU05_IRQ_PWRONR, 265 S2MPU05_IRQ_JIGONBF, 266 S2MPU05_IRQ_JIGONBR, 267 S2MPU05_IRQ_ACOKF, 268 S2MPU05_IRQ_ACOKR, 269 S2MPU05_IRQ_PWRON1S, 270 S2MPU05_IRQ_MRB, 271 272 S2MPU05_IRQ_RTC60S, 273 S2MPU05_IRQ_RTCA1, 274 S2MPU05_IRQ_RTCA0, 275 S2MPU05_IRQ_SMPL, 276 S2MPU05_IRQ_RTC1S, 277 S2MPU05_IRQ_WTSR, 278 279 S2MPU05_IRQ_INT120C, 280 S2MPU05_IRQ_INT140C, 281 S2MPU05_IRQ_TSD, 282 283 S2MPU05_IRQ_NR, 284 }; 285 286 #define S2MPU05_IRQ_PWRONF_MASK BIT(0) 287 #define S2MPU05_IRQ_PWRONR_MASK BIT(1) 288 #define S2MPU05_IRQ_JIGONBF_MASK BIT(2) 289 #define S2MPU05_IRQ_JIGONBR_MASK BIT(3) 290 #define S2MPU05_IRQ_ACOKF_MASK BIT(4) 291 #define S2MPU05_IRQ_ACOKR_MASK BIT(5) 292 #define S2MPU05_IRQ_PWRON1S_MASK BIT(6) 293 #define S2MPU05_IRQ_MRB_MASK BIT(7) 294 295 #define S2MPU05_IRQ_RTC60S_MASK BIT(0) 296 #define S2MPU05_IRQ_RTCA1_MASK BIT(1) 297 #define S2MPU05_IRQ_RTCA0_MASK BIT(2) 298 #define S2MPU05_IRQ_SMPL_MASK BIT(3) 299 #define S2MPU05_IRQ_RTC1S_MASK BIT(4) 300 #define S2MPU05_IRQ_WTSR_MASK BIT(5) 301 302 #define S2MPU05_IRQ_INT120C_MASK BIT(0) 303 #define S2MPU05_IRQ_INT140C_MASK BIT(1) 304 #define S2MPU05_IRQ_TSD_MASK BIT(2) 305 306 enum s5m8767_irq { 307 S5M8767_IRQ_PWRR, 308 S5M8767_IRQ_PWRF, 309 S5M8767_IRQ_PWR1S, 310 S5M8767_IRQ_JIGR, 311 S5M8767_IRQ_JIGF, 312 S5M8767_IRQ_LOWBAT2, 313 S5M8767_IRQ_LOWBAT1, 314 315 S5M8767_IRQ_MRB, 316 S5M8767_IRQ_DVSOK2, 317 S5M8767_IRQ_DVSOK3, 318 S5M8767_IRQ_DVSOK4, 319 320 S5M8767_IRQ_RTC60S, 321 S5M8767_IRQ_RTCA1, 322 S5M8767_IRQ_RTCA2, 323 S5M8767_IRQ_SMPL, 324 S5M8767_IRQ_RTC1S, 325 S5M8767_IRQ_WTSR, 326 327 S5M8767_IRQ_NR, 328 }; 329 330 #define S5M8767_IRQ_PWRR_MASK (1 << 0) 331 #define S5M8767_IRQ_PWRF_MASK (1 << 1) 332 #define S5M8767_IRQ_PWR1S_MASK (1 << 3) 333 #define S5M8767_IRQ_JIGR_MASK (1 << 4) 334 #define S5M8767_IRQ_JIGF_MASK (1 << 5) 335 #define S5M8767_IRQ_LOWBAT2_MASK (1 << 6) 336 #define S5M8767_IRQ_LOWBAT1_MASK (1 << 7) 337 338 #define S5M8767_IRQ_MRB_MASK (1 << 2) 339 #define S5M8767_IRQ_DVSOK2_MASK (1 << 3) 340 #define S5M8767_IRQ_DVSOK3_MASK (1 << 4) 341 #define S5M8767_IRQ_DVSOK4_MASK (1 << 5) 342 343 #define S5M8767_IRQ_RTC60S_MASK (1 << 0) 344 #define S5M8767_IRQ_RTCA1_MASK (1 << 1) 345 #define S5M8767_IRQ_RTCA2_MASK (1 << 2) 346 #define S5M8767_IRQ_SMPL_MASK (1 << 3) 347 #define S5M8767_IRQ_RTC1S_MASK (1 << 4) 348 #define S5M8767_IRQ_WTSR_MASK (1 << 5) 349 350 #endif /* __LINUX_MFD_SEC_IRQ_H */ 351