xref: /linux/include/linux/mfd/samsung/irq.h (revision e9ef810dfee7a2227da9d423aecb0ced35faddbe) 
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2012 Samsung Electronics Co., Ltd
4  *              http://www.samsung.com
5  */
6 
7 #ifndef __LINUX_MFD_SEC_IRQ_H
8 #define __LINUX_MFD_SEC_IRQ_H
9 
10 enum s2mpa01_irq {
11 	S2MPA01_IRQ_PWRONF,
12 	S2MPA01_IRQ_PWRONR,
13 	S2MPA01_IRQ_JIGONBF,
14 	S2MPA01_IRQ_JIGONBR,
15 	S2MPA01_IRQ_ACOKBF,
16 	S2MPA01_IRQ_ACOKBR,
17 	S2MPA01_IRQ_PWRON1S,
18 	S2MPA01_IRQ_MRB,
19 
20 	S2MPA01_IRQ_RTC60S,
21 	S2MPA01_IRQ_RTCA1,
22 	S2MPA01_IRQ_RTCA0,
23 	S2MPA01_IRQ_SMPL,
24 	S2MPA01_IRQ_RTC1S,
25 	S2MPA01_IRQ_WTSR,
26 
27 	S2MPA01_IRQ_INT120C,
28 	S2MPA01_IRQ_INT140C,
29 	S2MPA01_IRQ_LDO3_TSD,
30 	S2MPA01_IRQ_B16_TSD,
31 	S2MPA01_IRQ_B24_TSD,
32 	S2MPA01_IRQ_B35_TSD,
33 
34 	S2MPA01_IRQ_NR,
35 };
36 
37 #define S2MPA01_IRQ_PWRONF_MASK		(1 << 0)
38 #define S2MPA01_IRQ_PWRONR_MASK		(1 << 1)
39 #define S2MPA01_IRQ_JIGONBF_MASK	(1 << 2)
40 #define S2MPA01_IRQ_JIGONBR_MASK	(1 << 3)
41 #define S2MPA01_IRQ_ACOKBF_MASK		(1 << 4)
42 #define S2MPA01_IRQ_ACOKBR_MASK		(1 << 5)
43 #define S2MPA01_IRQ_PWRON1S_MASK	(1 << 6)
44 #define S2MPA01_IRQ_MRB_MASK		(1 << 7)
45 
46 #define S2MPA01_IRQ_RTC60S_MASK		(1 << 0)
47 #define S2MPA01_IRQ_RTCA1_MASK		(1 << 1)
48 #define S2MPA01_IRQ_RTCA0_MASK		(1 << 2)
49 #define S2MPA01_IRQ_SMPL_MASK		(1 << 3)
50 #define S2MPA01_IRQ_RTC1S_MASK		(1 << 4)
51 #define S2MPA01_IRQ_WTSR_MASK		(1 << 5)
52 
53 #define S2MPA01_IRQ_INT120C_MASK	(1 << 0)
54 #define S2MPA01_IRQ_INT140C_MASK	(1 << 1)
55 #define S2MPA01_IRQ_LDO3_TSD_MASK	(1 << 2)
56 #define S2MPA01_IRQ_B16_TSD_MASK	(1 << 3)
57 #define S2MPA01_IRQ_B24_TSD_MASK	(1 << 4)
58 #define S2MPA01_IRQ_B35_TSD_MASK	(1 << 5)
59 
60 enum s2mpg10_irq {
61 	/* PMIC */
62 	S2MPG10_IRQ_PWRONF,
63 	S2MPG10_IRQ_PWRONR,
64 	S2MPG10_IRQ_JIGONBF,
65 	S2MPG10_IRQ_JIGONBR,
66 	S2MPG10_IRQ_ACOKBF,
67 	S2MPG10_IRQ_ACOKBR,
68 	S2MPG10_IRQ_PWRON1S,
69 	S2MPG10_IRQ_MRB,
70 #define S2MPG10_IRQ_PWRONF_MASK		BIT(0)
71 #define S2MPG10_IRQ_PWRONR_MASK		BIT(1)
72 #define S2MPG10_IRQ_JIGONBF_MASK	BIT(2)
73 #define S2MPG10_IRQ_JIGONBR_MASK	BIT(3)
74 #define S2MPG10_IRQ_ACOKBF_MASK		BIT(4)
75 #define S2MPG10_IRQ_ACOKBR_MASK		BIT(5)
76 #define S2MPG10_IRQ_PWRON1S_MASK	BIT(6)
77 #define S2MPG10_IRQ_MRB_MASK		BIT(7)
78 
79 	S2MPG10_IRQ_RTC60S,
80 	S2MPG10_IRQ_RTCA1,
81 	S2MPG10_IRQ_RTCA0,
82 	S2MPG10_IRQ_RTC1S,
83 	S2MPG10_IRQ_WTSR_COLDRST,
84 	S2MPG10_IRQ_WTSR,
85 	S2MPG10_IRQ_WRST,
86 	S2MPG10_IRQ_SMPL,
87 #define S2MPG10_IRQ_RTC60S_MASK		BIT(0)
88 #define S2MPG10_IRQ_RTCA1_MASK		BIT(1)
89 #define S2MPG10_IRQ_RTCA0_MASK		BIT(2)
90 #define S2MPG10_IRQ_RTC1S_MASK		BIT(3)
91 #define S2MPG10_IRQ_WTSR_COLDRST_MASK	BIT(4)
92 #define S2MPG10_IRQ_WTSR_MASK		BIT(5)
93 #define S2MPG10_IRQ_WRST_MASK		BIT(6)
94 #define S2MPG10_IRQ_SMPL_MASK		BIT(7)
95 
96 	S2MPG10_IRQ_120C,
97 	S2MPG10_IRQ_140C,
98 	S2MPG10_IRQ_TSD,
99 	S2MPG10_IRQ_PIF_TIMEOUT1,
100 	S2MPG10_IRQ_PIF_TIMEOUT2,
101 	S2MPG10_IRQ_SPD_PARITY_ERR,
102 	S2MPG10_IRQ_SPD_ABNORMAL_STOP,
103 	S2MPG10_IRQ_PMETER_OVERF,
104 #define S2MPG10_IRQ_INT120C_MASK		BIT(0)
105 #define S2MPG10_IRQ_INT140C_MASK		BIT(1)
106 #define S2MPG10_IRQ_TSD_MASK			BIT(2)
107 #define S2MPG10_IRQ_PIF_TIMEOUT1_MASK		BIT(3)
108 #define S2MPG10_IRQ_PIF_TIMEOUT2_MASK		BIT(4)
109 #define S2MPG10_IRQ_SPD_PARITY_ERR_MASK		BIT(5)
110 #define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK	BIT(6)
111 #define S2MPG10_IRQ_PMETER_OVERF_MASK		BIT(7)
112 
113 	S2MPG10_IRQ_OCP_B1M,
114 	S2MPG10_IRQ_OCP_B2M,
115 	S2MPG10_IRQ_OCP_B3M,
116 	S2MPG10_IRQ_OCP_B4M,
117 	S2MPG10_IRQ_OCP_B5M,
118 	S2MPG10_IRQ_OCP_B6M,
119 	S2MPG10_IRQ_OCP_B7M,
120 	S2MPG10_IRQ_OCP_B8M,
121 #define S2MPG10_IRQ_OCP_B1M_MASK	BIT(0)
122 #define S2MPG10_IRQ_OCP_B2M_MASK	BIT(1)
123 #define S2MPG10_IRQ_OCP_B3M_MASK	BIT(2)
124 #define S2MPG10_IRQ_OCP_B4M_MASK	BIT(3)
125 #define S2MPG10_IRQ_OCP_B5M_MASK	BIT(4)
126 #define S2MPG10_IRQ_OCP_B6M_MASK	BIT(5)
127 #define S2MPG10_IRQ_OCP_B7M_MASK	BIT(6)
128 #define S2MPG10_IRQ_OCP_B8M_MASK	BIT(7)
129 
130 	S2MPG10_IRQ_OCP_B9M,
131 	S2MPG10_IRQ_OCP_B10M,
132 	S2MPG10_IRQ_WLWP_ACC,
133 	S2MPG10_IRQ_SMPL_TIMEOUT,
134 	S2MPG10_IRQ_WTSR_TIMEOUT,
135 	S2MPG10_IRQ_SPD_SRP_PKT_RST,
136 #define S2MPG10_IRQ_OCP_B9M_MASK		BIT(0)
137 #define S2MPG10_IRQ_OCP_B10M_MASK		BIT(1)
138 #define S2MPG10_IRQ_WLWP_ACC_MASK		BIT(2)
139 #define S2MPG10_IRQ_SMPL_TIMEOUT_MASK		BIT(5)
140 #define S2MPG10_IRQ_WTSR_TIMEOUT_MASK		BIT(6)
141 #define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK	BIT(7)
142 
143 	S2MPG10_IRQ_PWR_WARN_CH0,
144 	S2MPG10_IRQ_PWR_WARN_CH1,
145 	S2MPG10_IRQ_PWR_WARN_CH2,
146 	S2MPG10_IRQ_PWR_WARN_CH3,
147 	S2MPG10_IRQ_PWR_WARN_CH4,
148 	S2MPG10_IRQ_PWR_WARN_CH5,
149 	S2MPG10_IRQ_PWR_WARN_CH6,
150 	S2MPG10_IRQ_PWR_WARN_CH7,
151 #define S2MPG10_IRQ_PWR_WARN_CH0_MASK	BIT(0)
152 #define S2MPG10_IRQ_PWR_WARN_CH1_MASK	BIT(1)
153 #define S2MPG10_IRQ_PWR_WARN_CH2_MASK	BIT(2)
154 #define S2MPG10_IRQ_PWR_WARN_CH3_MASK	BIT(3)
155 #define S2MPG10_IRQ_PWR_WARN_CH4_MASK	BIT(4)
156 #define S2MPG10_IRQ_PWR_WARN_CH5_MASK	BIT(5)
157 #define S2MPG10_IRQ_PWR_WARN_CH6_MASK	BIT(6)
158 #define S2MPG10_IRQ_PWR_WARN_CH7_MASK	BIT(7)
159 
160 	S2MPG10_IRQ_NR,
161 };
162 
163 enum s2mps11_irq {
164 	S2MPS11_IRQ_PWRONF,
165 	S2MPS11_IRQ_PWRONR,
166 	S2MPS11_IRQ_JIGONBF,
167 	S2MPS11_IRQ_JIGONBR,
168 	S2MPS11_IRQ_ACOKBF,
169 	S2MPS11_IRQ_ACOKBR,
170 	S2MPS11_IRQ_PWRON1S,
171 	S2MPS11_IRQ_MRB,
172 
173 	S2MPS11_IRQ_RTC60S,
174 	S2MPS11_IRQ_RTCA1,
175 	S2MPS11_IRQ_RTCA0,
176 	S2MPS11_IRQ_SMPL,
177 	S2MPS11_IRQ_RTC1S,
178 	S2MPS11_IRQ_WTSR,
179 
180 	S2MPS11_IRQ_INT120C,
181 	S2MPS11_IRQ_INT140C,
182 
183 	S2MPS11_IRQ_NR,
184 };
185 
186 #define S2MPS11_IRQ_PWRONF_MASK		(1 << 0)
187 #define S2MPS11_IRQ_PWRONR_MASK		(1 << 1)
188 #define S2MPS11_IRQ_JIGONBF_MASK	(1 << 2)
189 #define S2MPS11_IRQ_JIGONBR_MASK	(1 << 3)
190 #define S2MPS11_IRQ_ACOKBF_MASK		(1 << 4)
191 #define S2MPS11_IRQ_ACOKBR_MASK		(1 << 5)
192 #define S2MPS11_IRQ_PWRON1S_MASK	(1 << 6)
193 #define S2MPS11_IRQ_MRB_MASK		(1 << 7)
194 
195 #define S2MPS11_IRQ_RTC60S_MASK		(1 << 0)
196 #define S2MPS11_IRQ_RTCA1_MASK		(1 << 1)
197 #define S2MPS11_IRQ_RTCA0_MASK		(1 << 2)
198 #define S2MPS11_IRQ_SMPL_MASK		(1 << 3)
199 #define S2MPS11_IRQ_RTC1S_MASK		(1 << 4)
200 #define S2MPS11_IRQ_WTSR_MASK		(1 << 5)
201 
202 #define S2MPS11_IRQ_INT120C_MASK	(1 << 0)
203 #define S2MPS11_IRQ_INT140C_MASK	(1 << 1)
204 
205 enum s2mps14_irq {
206 	S2MPS14_IRQ_PWRONF,
207 	S2MPS14_IRQ_PWRONR,
208 	S2MPS14_IRQ_JIGONBF,
209 	S2MPS14_IRQ_JIGONBR,
210 	S2MPS14_IRQ_ACOKBF,
211 	S2MPS14_IRQ_ACOKBR,
212 	S2MPS14_IRQ_PWRON1S,
213 	S2MPS14_IRQ_MRB,
214 
215 	S2MPS14_IRQ_RTC60S,
216 	S2MPS14_IRQ_RTCA1,
217 	S2MPS14_IRQ_RTCA0,
218 	S2MPS14_IRQ_SMPL,
219 	S2MPS14_IRQ_RTC1S,
220 	S2MPS14_IRQ_WTSR,
221 
222 	S2MPS14_IRQ_INT120C,
223 	S2MPS14_IRQ_INT140C,
224 	S2MPS14_IRQ_TSD,
225 
226 	S2MPS14_IRQ_NR,
227 };
228 
229 enum s2mpu02_irq {
230 	S2MPU02_IRQ_PWRONF,
231 	S2MPU02_IRQ_PWRONR,
232 	S2MPU02_IRQ_JIGONBF,
233 	S2MPU02_IRQ_JIGONBR,
234 	S2MPU02_IRQ_ACOKBF,
235 	S2MPU02_IRQ_ACOKBR,
236 	S2MPU02_IRQ_PWRON1S,
237 	S2MPU02_IRQ_MRB,
238 
239 	S2MPU02_IRQ_RTC60S,
240 	S2MPU02_IRQ_RTCA1,
241 	S2MPU02_IRQ_RTCA0,
242 	S2MPU02_IRQ_SMPL,
243 	S2MPU02_IRQ_RTC1S,
244 	S2MPU02_IRQ_WTSR,
245 
246 	S2MPU02_IRQ_INT120C,
247 	S2MPU02_IRQ_INT140C,
248 	S2MPU02_IRQ_TSD,
249 
250 	S2MPU02_IRQ_NR,
251 };
252 
253 /* Masks for interrupts are the same as in s2mps11 */
254 #define S2MPS14_IRQ_TSD_MASK		(1 << 2)
255 
256 enum s2mpu05_irq {
257 	S2MPU05_IRQ_PWRONF,
258 	S2MPU05_IRQ_PWRONR,
259 	S2MPU05_IRQ_JIGONBF,
260 	S2MPU05_IRQ_JIGONBR,
261 	S2MPU05_IRQ_ACOKF,
262 	S2MPU05_IRQ_ACOKR,
263 	S2MPU05_IRQ_PWRON1S,
264 	S2MPU05_IRQ_MRB,
265 
266 	S2MPU05_IRQ_RTC60S,
267 	S2MPU05_IRQ_RTCA1,
268 	S2MPU05_IRQ_RTCA0,
269 	S2MPU05_IRQ_SMPL,
270 	S2MPU05_IRQ_RTC1S,
271 	S2MPU05_IRQ_WTSR,
272 
273 	S2MPU05_IRQ_INT120C,
274 	S2MPU05_IRQ_INT140C,
275 	S2MPU05_IRQ_TSD,
276 
277 	S2MPU05_IRQ_NR,
278 };
279 
280 #define S2MPU05_IRQ_PWRONF_MASK		BIT(0)
281 #define S2MPU05_IRQ_PWRONR_MASK		BIT(1)
282 #define S2MPU05_IRQ_JIGONBF_MASK	BIT(2)
283 #define S2MPU05_IRQ_JIGONBR_MASK	BIT(3)
284 #define S2MPU05_IRQ_ACOKF_MASK		BIT(4)
285 #define S2MPU05_IRQ_ACOKR_MASK		BIT(5)
286 #define S2MPU05_IRQ_PWRON1S_MASK	BIT(6)
287 #define S2MPU05_IRQ_MRB_MASK		BIT(7)
288 
289 #define S2MPU05_IRQ_RTC60S_MASK		BIT(0)
290 #define S2MPU05_IRQ_RTCA1_MASK		BIT(1)
291 #define S2MPU05_IRQ_RTCA0_MASK		BIT(2)
292 #define S2MPU05_IRQ_SMPL_MASK		BIT(3)
293 #define S2MPU05_IRQ_RTC1S_MASK		BIT(4)
294 #define S2MPU05_IRQ_WTSR_MASK		BIT(5)
295 
296 #define S2MPU05_IRQ_INT120C_MASK	BIT(0)
297 #define S2MPU05_IRQ_INT140C_MASK	BIT(1)
298 #define S2MPU05_IRQ_TSD_MASK		BIT(2)
299 
300 enum s5m8767_irq {
301 	S5M8767_IRQ_PWRR,
302 	S5M8767_IRQ_PWRF,
303 	S5M8767_IRQ_PWR1S,
304 	S5M8767_IRQ_JIGR,
305 	S5M8767_IRQ_JIGF,
306 	S5M8767_IRQ_LOWBAT2,
307 	S5M8767_IRQ_LOWBAT1,
308 
309 	S5M8767_IRQ_MRB,
310 	S5M8767_IRQ_DVSOK2,
311 	S5M8767_IRQ_DVSOK3,
312 	S5M8767_IRQ_DVSOK4,
313 
314 	S5M8767_IRQ_RTC60S,
315 	S5M8767_IRQ_RTCA1,
316 	S5M8767_IRQ_RTCA2,
317 	S5M8767_IRQ_SMPL,
318 	S5M8767_IRQ_RTC1S,
319 	S5M8767_IRQ_WTSR,
320 
321 	S5M8767_IRQ_NR,
322 };
323 
324 #define S5M8767_IRQ_PWRR_MASK		(1 << 0)
325 #define S5M8767_IRQ_PWRF_MASK		(1 << 1)
326 #define S5M8767_IRQ_PWR1S_MASK		(1 << 3)
327 #define S5M8767_IRQ_JIGR_MASK		(1 << 4)
328 #define S5M8767_IRQ_JIGF_MASK		(1 << 5)
329 #define S5M8767_IRQ_LOWBAT2_MASK	(1 << 6)
330 #define S5M8767_IRQ_LOWBAT1_MASK	(1 << 7)
331 
332 #define S5M8767_IRQ_MRB_MASK		(1 << 2)
333 #define S5M8767_IRQ_DVSOK2_MASK		(1 << 3)
334 #define S5M8767_IRQ_DVSOK3_MASK		(1 << 4)
335 #define S5M8767_IRQ_DVSOK4_MASK		(1 << 5)
336 
337 #define S5M8767_IRQ_RTC60S_MASK		(1 << 0)
338 #define S5M8767_IRQ_RTCA1_MASK		(1 << 1)
339 #define S5M8767_IRQ_RTCA2_MASK		(1 << 2)
340 #define S5M8767_IRQ_SMPL_MASK		(1 << 3)
341 #define S5M8767_IRQ_RTC1S_MASK		(1 << 4)
342 #define S5M8767_IRQ_WTSR_MASK		(1 << 5)
343 
344 #endif /*  __LINUX_MFD_SEC_IRQ_H */
345