| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 132 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName()
314 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper()
397 SmallVectorImpl<unsigned> &Regs, in shouldUseFrameHelper()
475 SmallVector<unsigned, 8> Regs; in lowerEpilog() local
558 SmallVector<unsigned, 8> Regs; in lowerProlog() local
|
| H A D | AArch64ISelDAGToDAG.cpp | 1397 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1406 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1415 SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) { in createZTuple()
1425 SDValue AArch64DAGToDAGISel::createZMulTuple(ArrayRef<SDValue> Regs) { in createZMulTuple()
1437 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1475 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1864 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectCVTIntrinsic() local
1888 SmallVector<SDValue, 4> Regs(N->op_begin() + StartIdx, in SelectDestructiveMultiIntrinsic() local
2023 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectClamp() local
2150 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, in SelectUnaryMultiIntrinsic() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
453 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); getFrameRegister() local
[all...] |
| H A D | SystemZFrameLowering.cpp | 922 auto *Regs = in isXPLeafCandidate() local
971 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in assignCalleeSavedSpillSlots() local
1074 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in determineCalleeSaves() local
1092 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in spillCalleeSavedRegisters() local
1154 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in restoreCalleeSavedRegisters() local
1211 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in emitPrologue() local
1326 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in emitEpilogue() local
1460 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>(); in processFunctionBeforeFrameFinalized() local
1505 auto *Regs = in determineFrameLayout() local
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument
390 AllocateReg(ArrayRef<MCPhysReg> Regs,const MCPhysReg * ShadowRegs) AllocateReg() argument
[all...] |
| H A D | RegisterPressure.h | 276 RegSet Regs; variable
|
| H A D | RDFRegisters.h | 193 BitVector Regs; member
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | HWEventListener.h | 78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
381 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
508 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
872 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1440 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 145 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 140 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
290 if (const TaintedSubRegions *Regs = in getTaintedSymbolsImpl() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
|
| H A D | ARMLoadStoreOptimizer.cpp | 617 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg()
632 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti()
839 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreDouble()
865 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 817 AddressRegs Regs = getRegs(Opc, *LSO.TII); in setMI() local
1514 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1555 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
1598 AddressRegs Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair() local
1895 AddressRegs Regs = getRegs(Opcode, *TII); in mergeBufferStorePair() local
|
| H A D | AMDGPUArgumentUsageInfo.h | 97 SmallVector<MCRegister> Regs; member
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | IRTranslator.h | 708 auto Regs = getOrCreateVRegs(Val); in getOrCreateVReg() local
718 auto &Regs = *VMap.getVRegs(Token); in getOrCreateConvergenceTokenVReg() local
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 80 std::vector<unsigned> &Regs, in GetGroupRegs()
546 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
|
| H A D | ExecutionDomainFix.cpp | 329 SmallVector<int, 4> Regs; in visitSoftInstr() local
|
| H A D | CallingConvLower.cpp | 201 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
|
| H A D | RDFRegisters.cpp | 388 BitVector Regs = PRI.getUnitAliases(U); makeRegRef() local
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 215 RegUnitIterator(const CodeGenRegister::Vec &Regs) in RegUnitIterator()
1200 std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1711 CodeGenRegister::Vec Regs; member
1740 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2510 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record *> Regs) { in computeCoveredRegisters()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUPALMetadata.cpp | 171 auto Regs = getRegisters(); in getRegister() local
772 auto Regs = getRegisters(); in toString() local
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 35 SmallVector<Register, 1> Regs; member in __anon9afe8d680111::GISelAsmOperandInfo
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 239 static SDValue createTuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createTuple()
350 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLSEG() local
390 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLSEGFF() local
432 SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp, in selectVLXSEG() local
483 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); in selectVSSEG() local
513 SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); in selectVSXSEG() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYFrameLowering.cpp | 412 const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
|