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Searched defs:RegClass (Results 1 – 25 of 37) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
H A DRDFRegisters.h181 const TargetRegisterClass *RegClass = nullptr; member
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
H A DWebAssemblyRegStackify.cpp108 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
670 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreloadKernArgProlog.cpp45 const TargetRegisterClass *RegClass; member
H A DGCNDPPCombine.cpp198 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
H A DAMDGPUISelDAGToDAG.cpp366 int RegClass = Desc.operands()[OpIdx].RegClass; in getOperandRegClass() local
442 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp385 SDValue RegClass = in createGPRPairNode() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp140 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
H A DMachineRegisterInfo.cpp156 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h312 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1701 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameMOP() local
1907 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename() local
1935 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in findRenameRegForSameLdStRegPair() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1846 SDValue RegClass = in createGPRPairNode() local
1857 SDValue RegClass = in createSRegPairNode() local
1868 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1879 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1891 SDValue RegClass = in createQuadSRegsNode() local
1906 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1921 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
H A DThumb2InstrInfo.cpp564 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
H A DMVETPAndVPTOptimisationsPass.cpp615 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
H A DARMBaseRegisterInfo.cpp884 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp150 #define DECODE_OPERAND_REG_8(RegClass) \ argument
178 #define DECODE_OPERAND_SREG_7(RegClass, OpWidth) \ argument
181 #define DECODE_OPERAND_SREG_8(RegClass, OpWidth) \ argument
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp159 const Record *RegClass) { in validateRegister()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1119 for (const Record *RegClass : R->getValueAsListOfDefs("Classes")) in CodeGenRegisterCategory() local
1608 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp446 auto RegClass = GR->getRegClass(SpvType); in insertAssignInstr() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp49 const TargetRegisterClass &RegClass) { in constrainRegToClass()
60 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp1007 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
3744 auto &RegClass = in adjustStackWithPops() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp448 uint16_t Encoding) { in copyPhysRegVector()
632 const TargetRegisterClass *RegClass = in copyPhysReg() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp584 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); in getRegAllocationHints() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1972 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local

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