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Searched defs:RegClass (Results 1 – 25 of 35) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
H A DRDFRegisters.h183 const TargetRegisterClass *RegClass = nullptr; member
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
641 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1883 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1950 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2010 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2124 const TargetRegisterClass *RegClass = in createEntryPHI() local
2262 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2396 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
H A DGCNDPPCombine.cpp197 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
H A DAMDGPUISelDAGToDAG.cpp371 int RegClass = Desc.operands()[OpIdx].RegClass; in getOperandRegClass() local
446 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
H A DMachineRegisterInfo.cpp159 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
H A DTargetInstrInfo.cpp54 short RegClass = MCID.operands()[OpNum].RegClass; in getRegClass() local
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp385 SDValue RegClass = in createGPRPairNode() local
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1425 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameMOP() local
1628 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename() local
1656 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in findRenameRegForSameLdStRegPair() local
H A DAArch64AsmPrinter.cpp1110 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp562 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
H A DARMISelDAGToDAG.cpp1855 SDValue RegClass = in createGPRPairNode() local
1866 SDValue RegClass = in createSRegPairNode() local
1877 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1888 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1900 SDValue RegClass = in createQuadSRegsNode() local
1915 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1930 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
H A DMVETPAndVPTOptimisationsPass.cpp617 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
H A DARMBaseRegisterInfo.cpp855 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp151 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp162 #define DECODE_OPERAND_REG_8(RegClass) \ argument
197 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ argument
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp49 const TargetRegisterClass &RegClass) { in constrainRegToClass()
60 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1675 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1736 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp953 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
3680 auto &RegClass = in adjustStackWithPops() local
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp590 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); in getRegAllocationHints() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp385 uint16_t Encoding) { in copyPhysRegVector()
549 for (const auto &RegClass : RVVRegClasses) { in copyPhysReg() local
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2027 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local

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