1 /* 2 * 3 * Handle TWL4030 Power initialization 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * Copyright (C) 2006 Texas Instruments, Inc 7 * 8 * Written by Kalle Jokiniemi 9 * Peter De Schrijver <peter.de-schrijver@nokia.com> 10 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com> 11 * 12 * This file is subject to the terms and conditions of the GNU General 13 * Public License. See the file "COPYING" in the main directory of this 14 * archive for more details. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 */ 25 26 #include <linux/module.h> 27 #include <linux/pm.h> 28 #include <linux/mfd/twl.h> 29 #include <linux/platform_device.h> 30 #include <linux/property.h> 31 #include <linux/of.h> 32 33 static u8 twl4030_start_script_address = 0x2b; 34 35 /* Register bits for P1, P2 and P3_SW_EVENTS */ 36 #define PWR_STOPON_PRWON BIT(6) 37 #define PWR_STOPON_SYSEN BIT(5) 38 #define PWR_ENABLE_WARMRESET BIT(4) 39 #define PWR_LVL_WAKEUP BIT(3) 40 #define PWR_DEVACT BIT(2) 41 #define PWR_DEVSLP BIT(1) 42 #define PWR_DEVOFF BIT(0) 43 44 /* Register bits for CFG_P1_TRANSITION (also for P2 and P3) */ 45 #define STARTON_SWBUG BIT(7) /* Start on watchdog */ 46 #define STARTON_VBUS BIT(5) /* Start on VBUS */ 47 #define STARTON_VBAT BIT(4) /* Start on battery insert */ 48 #define STARTON_RTC BIT(3) /* Start on RTC */ 49 #define STARTON_USB BIT(2) /* Start on USB host */ 50 #define STARTON_CHG BIT(1) /* Start on charger */ 51 #define STARTON_PWON BIT(0) /* Start on PWRON button */ 52 53 #define SEQ_OFFSYNC (1 << 0) 54 55 #define PHY_TO_OFF_PM_MASTER(p) (p - 0x36) 56 #define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b) 57 58 /* resource - hfclk */ 59 #define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6) 60 61 /* PM events */ 62 #define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46) 63 #define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47) 64 #define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48) 65 #define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36) 66 #define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37) 67 #define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38) 68 69 #define END_OF_SCRIPT 0x3f 70 71 #define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55) 72 #define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56) 73 #define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57) 74 #define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58) 75 #define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59) 76 #define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a) 77 78 /* resource configuration registers 79 <RESOURCE>_DEV_GRP at address 'n+0' 80 <RESOURCE>_TYPE at address 'n+1' 81 <RESOURCE>_REMAP at address 'n+2' 82 <RESOURCE>_DEDICATED at address 'n+3' 83 */ 84 #define DEV_GRP_OFFSET 0 85 #define TYPE_OFFSET 1 86 #define REMAP_OFFSET 2 87 #define DEDICATED_OFFSET 3 88 89 /* Bit positions in the registers */ 90 91 /* <RESOURCE>_DEV_GRP */ 92 #define DEV_GRP_SHIFT 5 93 #define DEV_GRP_MASK (7 << DEV_GRP_SHIFT) 94 95 /* <RESOURCE>_TYPE */ 96 #define TYPE_SHIFT 0 97 #define TYPE_MASK (7 << TYPE_SHIFT) 98 #define TYPE2_SHIFT 3 99 #define TYPE2_MASK (3 << TYPE2_SHIFT) 100 101 /* <RESOURCE>_REMAP */ 102 #define SLEEP_STATE_SHIFT 0 103 #define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT) 104 #define OFF_STATE_SHIFT 4 105 #define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT) 106 107 static u8 res_config_addrs[] = { 108 [RES_VAUX1] = 0x17, 109 [RES_VAUX2] = 0x1b, 110 [RES_VAUX3] = 0x1f, 111 [RES_VAUX4] = 0x23, 112 [RES_VMMC1] = 0x27, 113 [RES_VMMC2] = 0x2b, 114 [RES_VPLL1] = 0x2f, 115 [RES_VPLL2] = 0x33, 116 [RES_VSIM] = 0x37, 117 [RES_VDAC] = 0x3b, 118 [RES_VINTANA1] = 0x3f, 119 [RES_VINTANA2] = 0x43, 120 [RES_VINTDIG] = 0x47, 121 [RES_VIO] = 0x4b, 122 [RES_VDD1] = 0x55, 123 [RES_VDD2] = 0x63, 124 [RES_VUSB_1V5] = 0x71, 125 [RES_VUSB_1V8] = 0x74, 126 [RES_VUSB_3V1] = 0x77, 127 [RES_VUSBCP] = 0x7a, 128 [RES_REGEN] = 0x7f, 129 [RES_NRES_PWRON] = 0x82, 130 [RES_CLKEN] = 0x85, 131 [RES_SYSEN] = 0x88, 132 [RES_HFCLKOUT] = 0x8b, 133 [RES_32KCLKOUT] = 0x8e, 134 [RES_RESET] = 0x91, 135 [RES_MAIN_REF] = 0x94, 136 }; 137 138 /* 139 * Usable values for .remap_sleep and .remap_off 140 * Based on table "5.3.3 Resource Operating modes" 141 */ 142 enum { 143 TWL_REMAP_OFF = 0, 144 TWL_REMAP_SLEEP = 8, 145 TWL_REMAP_ACTIVE = 9, 146 }; 147 148 /* 149 * Macros to configure the PM register states for various resources. 150 * Note that we can make MSG_SINGULAR etc private to this driver once 151 * omap3 has been made DT only. 152 */ 153 #define TWL_DFLT_DELAY 2 /* typically 2 32 KiHz cycles */ 154 #define TWL_DEV_GRP_P123 (DEV_GRP_P1 | DEV_GRP_P2 | DEV_GRP_P3) 155 #define TWL_RESOURCE_SET(res, state) \ 156 { MSG_SINGULAR(DEV_GRP_NULL, (res), (state)), TWL_DFLT_DELAY } 157 #define TWL_RESOURCE_ON(res) TWL_RESOURCE_SET(res, RES_STATE_ACTIVE) 158 #define TWL_RESOURCE_OFF(res) TWL_RESOURCE_SET(res, RES_STATE_OFF) 159 #define TWL_RESOURCE_RESET(res) TWL_RESOURCE_SET(res, RES_STATE_WRST) 160 /* 161 * It seems that type1 and type2 is just the resource init order 162 * number for the type1 and type2 group. 163 */ 164 #define TWL_RESOURCE_SET_ACTIVE(res, state) \ 165 { MSG_SINGULAR(DEV_GRP_NULL, (res), RES_STATE_ACTIVE), (state) } 166 #define TWL_RESOURCE_GROUP_RESET(group, type1, type2) \ 167 { MSG_BROADCAST(DEV_GRP_NULL, (group), (type1), (type2), \ 168 RES_STATE_WRST), TWL_DFLT_DELAY } 169 #define TWL_RESOURCE_GROUP_SLEEP(group, type, type2) \ 170 { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \ 171 RES_STATE_SLEEP), TWL_DFLT_DELAY } 172 #define TWL_RESOURCE_GROUP_ACTIVE(group, type, type2) \ 173 { MSG_BROADCAST(DEV_GRP_NULL, (group), (type), (type2), \ 174 RES_STATE_ACTIVE), TWL_DFLT_DELAY } 175 #define TWL_REMAP_SLEEP(res, devgrp, typ, typ2) \ 176 { .resource = (res), .devgroup = (devgrp), \ 177 .type = (typ), .type2 = (typ2), \ 178 .remap_off = TWL_REMAP_OFF, \ 179 .remap_sleep = TWL_REMAP_SLEEP, } 180 #define TWL_REMAP_OFF(res, devgrp, typ, typ2) \ 181 { .resource = (res), .devgroup = (devgrp), \ 182 .type = (typ), .type2 = (typ2), \ 183 .remap_off = TWL_REMAP_OFF, .remap_sleep = TWL_REMAP_OFF, } 184 185 static int twl4030_write_script_byte(u8 address, u8 byte) 186 { 187 int err; 188 189 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS); 190 if (err) 191 goto out; 192 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA); 193 out: 194 return err; 195 } 196 197 static int twl4030_write_script_ins(u8 address, u16 pmb_message, 198 u8 delay, u8 next) 199 { 200 int err; 201 202 address *= 4; 203 err = twl4030_write_script_byte(address++, pmb_message >> 8); 204 if (err) 205 goto out; 206 err = twl4030_write_script_byte(address++, pmb_message & 0xff); 207 if (err) 208 goto out; 209 err = twl4030_write_script_byte(address++, delay); 210 if (err) 211 goto out; 212 err = twl4030_write_script_byte(address++, next); 213 out: 214 return err; 215 } 216 217 static int twl4030_write_script(u8 address, struct twl4030_ins *script, 218 int len) 219 { 220 int err = -EINVAL; 221 222 for (; len; len--, address++, script++) { 223 if (len == 1) { 224 err = twl4030_write_script_ins(address, 225 script->pmb_message, 226 script->delay, 227 END_OF_SCRIPT); 228 if (err) 229 break; 230 } else { 231 err = twl4030_write_script_ins(address, 232 script->pmb_message, 233 script->delay, 234 address + 1); 235 if (err) 236 break; 237 } 238 } 239 return err; 240 } 241 242 static int twl4030_config_wakeup3_sequence(u8 address) 243 { 244 int err; 245 u8 data; 246 247 /* Set SLEEP to ACTIVE SEQ address for P3 */ 248 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3); 249 if (err) 250 goto out; 251 252 /* P3 LVL_WAKEUP should be on LEVEL */ 253 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS); 254 if (err) 255 goto out; 256 data |= PWR_LVL_WAKEUP; 257 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS); 258 out: 259 if (err) 260 pr_err("TWL4030 wakeup sequence for P3 config error\n"); 261 return err; 262 } 263 264 static int 265 twl4030_config_wakeup12_sequence(const struct twl4030_power_data *pdata, 266 u8 address) 267 { 268 int err = 0; 269 u8 data; 270 271 /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */ 272 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12); 273 if (err) 274 goto out; 275 276 /* P1/P2 LVL_WAKEUP should be on LEVEL */ 277 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS); 278 if (err) 279 goto out; 280 281 data |= PWR_LVL_WAKEUP; 282 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS); 283 if (err) 284 goto out; 285 286 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS); 287 if (err) 288 goto out; 289 290 data |= PWR_LVL_WAKEUP; 291 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS); 292 if (err) 293 goto out; 294 295 if (pdata->ac_charger_quirk || of_machine_is_compatible("ti,omap3430-sdp") || 296 of_machine_is_compatible("ti,omap3-ldp")) { 297 /* Disabling AC charger effect on sleep-active transitions */ 298 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, 299 R_CFG_P1_TRANSITION); 300 if (err) 301 goto out; 302 data &= ~STARTON_CHG; 303 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, 304 R_CFG_P1_TRANSITION); 305 if (err) 306 goto out; 307 } 308 309 out: 310 if (err) 311 pr_err("TWL4030 wakeup sequence for P1 and P2" \ 312 "config error\n"); 313 return err; 314 } 315 316 static int twl4030_config_sleep_sequence(u8 address) 317 { 318 int err; 319 320 /* Set ACTIVE to SLEEP SEQ address in T2 memory*/ 321 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S); 322 323 if (err) 324 pr_err("TWL4030 sleep sequence config error\n"); 325 326 return err; 327 } 328 329 static int twl4030_config_warmreset_sequence(u8 address) 330 { 331 int err; 332 u8 rd_data; 333 334 /* Set WARM RESET SEQ address for P1 */ 335 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM); 336 if (err) 337 goto out; 338 339 /* P1/P2/P3 enable WARMRESET */ 340 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS); 341 if (err) 342 goto out; 343 344 rd_data |= PWR_ENABLE_WARMRESET; 345 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS); 346 if (err) 347 goto out; 348 349 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS); 350 if (err) 351 goto out; 352 353 rd_data |= PWR_ENABLE_WARMRESET; 354 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS); 355 if (err) 356 goto out; 357 358 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS); 359 if (err) 360 goto out; 361 362 rd_data |= PWR_ENABLE_WARMRESET; 363 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS); 364 out: 365 if (err) 366 pr_err("TWL4030 warmreset seq config error\n"); 367 return err; 368 } 369 370 static int twl4030_configure_resource(struct twl4030_resconfig *rconfig) 371 { 372 int rconfig_addr; 373 int err; 374 u8 type; 375 u8 grp; 376 u8 remap; 377 378 if (rconfig->resource > TOTAL_RESOURCES) { 379 pr_err("TWL4030 Resource %d does not exist\n", 380 rconfig->resource); 381 return -EINVAL; 382 } 383 384 rconfig_addr = res_config_addrs[rconfig->resource]; 385 386 /* Set resource group */ 387 err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp, 388 rconfig_addr + DEV_GRP_OFFSET); 389 if (err) { 390 pr_err("TWL4030 Resource %d group could not be read\n", 391 rconfig->resource); 392 return err; 393 } 394 395 if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) { 396 grp &= ~DEV_GRP_MASK; 397 grp |= rconfig->devgroup << DEV_GRP_SHIFT; 398 err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 399 grp, rconfig_addr + DEV_GRP_OFFSET); 400 if (err < 0) { 401 pr_err("TWL4030 failed to program devgroup\n"); 402 return err; 403 } 404 } 405 406 /* Set resource types */ 407 err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type, 408 rconfig_addr + TYPE_OFFSET); 409 if (err < 0) { 410 pr_err("TWL4030 Resource %d type could not be read\n", 411 rconfig->resource); 412 return err; 413 } 414 415 if (rconfig->type != TWL4030_RESCONFIG_UNDEF) { 416 type &= ~TYPE_MASK; 417 type |= rconfig->type << TYPE_SHIFT; 418 } 419 420 if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) { 421 type &= ~TYPE2_MASK; 422 type |= rconfig->type2 << TYPE2_SHIFT; 423 } 424 425 err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 426 type, rconfig_addr + TYPE_OFFSET); 427 if (err < 0) { 428 pr_err("TWL4030 failed to program resource type\n"); 429 return err; 430 } 431 432 /* Set remap states */ 433 err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap, 434 rconfig_addr + REMAP_OFFSET); 435 if (err < 0) { 436 pr_err("TWL4030 Resource %d remap could not be read\n", 437 rconfig->resource); 438 return err; 439 } 440 441 if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) { 442 remap &= ~OFF_STATE_MASK; 443 remap |= rconfig->remap_off << OFF_STATE_SHIFT; 444 } 445 446 if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) { 447 remap &= ~SLEEP_STATE_MASK; 448 remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT; 449 } 450 451 err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 452 remap, 453 rconfig_addr + REMAP_OFFSET); 454 if (err < 0) { 455 pr_err("TWL4030 failed to program remap\n"); 456 return err; 457 } 458 459 return 0; 460 } 461 462 static int load_twl4030_script(const struct twl4030_power_data *pdata, 463 struct twl4030_script *tscript, 464 u8 address) 465 { 466 int err; 467 static int order; 468 469 /* Make sure the script isn't going beyond last valid address (0x3f) */ 470 if ((address + tscript->size) > END_OF_SCRIPT) { 471 pr_err("TWL4030 scripts too big error\n"); 472 return -EINVAL; 473 } 474 475 err = twl4030_write_script(address, tscript->script, tscript->size); 476 if (err) 477 goto out; 478 479 if (tscript->flags & TWL4030_WRST_SCRIPT) { 480 err = twl4030_config_warmreset_sequence(address); 481 if (err) 482 goto out; 483 } 484 if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) { 485 /* Reset any existing sleep script to avoid hangs on reboot */ 486 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT, 487 R_SEQ_ADD_A2S); 488 if (err) 489 goto out; 490 491 err = twl4030_config_wakeup12_sequence(pdata, address); 492 if (err) 493 goto out; 494 order = 1; 495 } 496 if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) { 497 err = twl4030_config_wakeup3_sequence(address); 498 if (err) 499 goto out; 500 } 501 if (tscript->flags & TWL4030_SLEEP_SCRIPT) { 502 if (!order) 503 pr_warn("TWL4030: Bad order of scripts (sleep script before wakeup) Leads to boot failure on some boards\n"); 504 err = twl4030_config_sleep_sequence(address); 505 } 506 out: 507 return err; 508 } 509 510 int twl4030_remove_script(u8 flags) 511 { 512 int err = 0; 513 514 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, 515 TWL4030_PM_MASTER_PROTECT_KEY); 516 if (err) { 517 pr_err("twl4030: unable to unlock PROTECT_KEY\n"); 518 return err; 519 } 520 521 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, 522 TWL4030_PM_MASTER_PROTECT_KEY); 523 if (err) { 524 pr_err("twl4030: unable to unlock PROTECT_KEY\n"); 525 return err; 526 } 527 528 if (flags & TWL4030_WRST_SCRIPT) { 529 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT, 530 R_SEQ_ADD_WARM); 531 if (err) 532 return err; 533 } 534 if (flags & TWL4030_WAKEUP12_SCRIPT) { 535 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT, 536 R_SEQ_ADD_S2A12); 537 if (err) 538 return err; 539 } 540 if (flags & TWL4030_WAKEUP3_SCRIPT) { 541 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT, 542 R_SEQ_ADD_S2A3); 543 if (err) 544 return err; 545 } 546 if (flags & TWL4030_SLEEP_SCRIPT) { 547 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT, 548 R_SEQ_ADD_A2S); 549 if (err) 550 return err; 551 } 552 553 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, 554 TWL4030_PM_MASTER_PROTECT_KEY); 555 if (err) 556 pr_err("TWL4030 Unable to relock registers\n"); 557 558 return err; 559 } 560 561 static int 562 twl4030_power_configure_scripts(const struct twl4030_power_data *pdata) 563 { 564 int err; 565 int i; 566 u8 address = twl4030_start_script_address; 567 568 for (i = 0; i < pdata->num; i++) { 569 err = load_twl4030_script(pdata, pdata->scripts[i], address); 570 if (err) 571 return err; 572 address += pdata->scripts[i]->size; 573 } 574 575 return 0; 576 } 577 578 static void twl4030_patch_rconfig(struct twl4030_resconfig *common, 579 struct twl4030_resconfig *board) 580 { 581 while (common->resource) { 582 struct twl4030_resconfig *b = board; 583 584 while (b->resource) { 585 if (b->resource == common->resource) { 586 *common = *b; 587 break; 588 } 589 b++; 590 } 591 common++; 592 } 593 } 594 595 static int 596 twl4030_power_configure_resources(const struct twl4030_power_data *pdata) 597 { 598 struct twl4030_resconfig *resconfig = pdata->resource_config; 599 struct twl4030_resconfig *boardconf = pdata->board_config; 600 int err; 601 602 if (resconfig) { 603 if (boardconf) 604 twl4030_patch_rconfig(resconfig, boardconf); 605 606 while (resconfig->resource) { 607 err = twl4030_configure_resource(resconfig); 608 if (err) 609 return err; 610 resconfig++; 611 } 612 } 613 614 return 0; 615 } 616 617 static int twl4030_starton_mask_and_set(u8 bitmask, u8 bitvalues) 618 { 619 u8 regs[3] = { TWL4030_PM_MASTER_CFG_P1_TRANSITION, 620 TWL4030_PM_MASTER_CFG_P2_TRANSITION, 621 TWL4030_PM_MASTER_CFG_P3_TRANSITION, }; 622 u8 val; 623 int i, err; 624 625 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, 626 TWL4030_PM_MASTER_PROTECT_KEY); 627 if (err) 628 goto relock; 629 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 630 TWL4030_PM_MASTER_KEY_CFG2, 631 TWL4030_PM_MASTER_PROTECT_KEY); 632 if (err) 633 goto relock; 634 635 for (i = 0; i < sizeof(regs); i++) { 636 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, 637 &val, regs[i]); 638 if (err) 639 break; 640 val = (~bitmask & val) | (bitmask & bitvalues); 641 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 642 val, regs[i]); 643 if (err) 644 break; 645 } 646 647 if (err) 648 pr_err("TWL4030 Register access failed: %i\n", err); 649 650 relock: 651 return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, 652 TWL4030_PM_MASTER_PROTECT_KEY); 653 } 654 655 /* 656 * In master mode, start the power off sequence. 657 * After a successful execution, TWL shuts down the power to the SoC 658 * and all peripherals connected to it. 659 */ 660 void twl4030_power_off(void) 661 { 662 int err; 663 664 /* Disable start on charger or VBUS as it can break poweroff */ 665 err = twl4030_starton_mask_and_set(STARTON_VBUS | STARTON_CHG, 0); 666 if (err) 667 pr_err("TWL4030 Unable to configure start-up\n"); 668 669 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF, 670 TWL4030_PM_MASTER_P1_SW_EVENTS); 671 if (err) 672 pr_err("TWL4030 Unable to power off\n"); 673 } 674 675 static bool twl4030_power_use_poweroff(const struct twl4030_power_data *pdata, 676 struct device_node *node) 677 { 678 if (pdata && pdata->use_poweroff) 679 return true; 680 681 if (of_property_read_bool(node, "ti,system-power-controller")) 682 return true; 683 684 if (of_property_read_bool(node, "ti,use_poweroff")) 685 return true; 686 687 if (of_device_is_system_power_controller(node->parent)) 688 return true; 689 690 return false; 691 } 692 693 #ifdef CONFIG_OF 694 695 /* Generic warm reset configuration for omap3 */ 696 697 static struct twl4030_ins omap3_wrst_seq[] = { 698 TWL_RESOURCE_OFF(RES_NRES_PWRON), 699 TWL_RESOURCE_OFF(RES_RESET), 700 TWL_RESOURCE_RESET(RES_MAIN_REF), 701 TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R2), 702 TWL_RESOURCE_RESET(RES_VUSB_3V1), 703 TWL_RESOURCE_RESET(RES_VMMC1), 704 TWL_RESOURCE_GROUP_RESET(RES_GRP_ALL, RES_TYPE_R0, RES_TYPE2_R1), 705 TWL_RESOURCE_GROUP_RESET(RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0), 706 TWL_RESOURCE_ON(RES_RESET), 707 TWL_RESOURCE_ON(RES_NRES_PWRON), 708 }; 709 710 static struct twl4030_script omap3_wrst_script = { 711 .script = omap3_wrst_seq, 712 .size = ARRAY_SIZE(omap3_wrst_seq), 713 .flags = TWL4030_WRST_SCRIPT, 714 }; 715 716 static struct twl4030_script *omap3_reset_scripts[] = { 717 &omap3_wrst_script, 718 }; 719 720 static struct twl4030_resconfig omap3_rconfig[] = { 721 TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, -1, -1), 722 TWL_REMAP_SLEEP(RES_VDD1, DEV_GRP_P1, -1, -1), 723 TWL_REMAP_SLEEP(RES_VDD2, DEV_GRP_P1, -1, -1), 724 { 0, 0 }, 725 }; 726 727 static struct twl4030_power_data omap3_reset = { 728 .scripts = omap3_reset_scripts, 729 .num = ARRAY_SIZE(omap3_reset_scripts), 730 .resource_config = omap3_rconfig, 731 }; 732 733 /* Recommended generic default idle configuration for off-idle */ 734 735 /* Broadcast message to put res to sleep */ 736 static struct twl4030_ins omap3_idle_sleep_on_seq[] = { 737 TWL_RESOURCE_GROUP_SLEEP(RES_GRP_ALL, RES_TYPE_ALL, 0), 738 }; 739 740 static struct twl4030_script omap3_idle_sleep_on_script = { 741 .script = omap3_idle_sleep_on_seq, 742 .size = ARRAY_SIZE(omap3_idle_sleep_on_seq), 743 .flags = TWL4030_SLEEP_SCRIPT, 744 }; 745 746 /* Broadcast message to put res to active */ 747 static struct twl4030_ins omap3_idle_wakeup_p12_seq[] = { 748 TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0), 749 }; 750 751 static struct twl4030_script omap3_idle_wakeup_p12_script = { 752 .script = omap3_idle_wakeup_p12_seq, 753 .size = ARRAY_SIZE(omap3_idle_wakeup_p12_seq), 754 .flags = TWL4030_WAKEUP12_SCRIPT, 755 }; 756 757 /* Broadcast message to put res to active */ 758 static struct twl4030_ins omap3_idle_wakeup_p3_seq[] = { 759 TWL_RESOURCE_SET_ACTIVE(RES_CLKEN, 0x37), 760 TWL_RESOURCE_GROUP_ACTIVE(RES_GRP_ALL, RES_TYPE_ALL, 0), 761 }; 762 763 static struct twl4030_script omap3_idle_wakeup_p3_script = { 764 .script = omap3_idle_wakeup_p3_seq, 765 .size = ARRAY_SIZE(omap3_idle_wakeup_p3_seq), 766 .flags = TWL4030_WAKEUP3_SCRIPT, 767 }; 768 769 static struct twl4030_script *omap3_idle_scripts[] = { 770 &omap3_idle_wakeup_p12_script, 771 &omap3_idle_wakeup_p3_script, 772 &omap3_wrst_script, 773 &omap3_idle_sleep_on_script, 774 }; 775 776 /* 777 * Recommended configuration based on "Recommended Sleep 778 * Sequences for the Zoom Platform": 779 * http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf 780 * Note that the type1 and type2 seem to be just the init order number 781 * for type1 and type2 groups as specified in the document mentioned 782 * above. 783 */ 784 static struct twl4030_resconfig omap3_idle_rconfig[] = { 785 TWL_REMAP_SLEEP(RES_VAUX1, TWL4030_RESCONFIG_UNDEF, 0, 0), 786 TWL_REMAP_SLEEP(RES_VAUX2, TWL4030_RESCONFIG_UNDEF, 0, 0), 787 TWL_REMAP_SLEEP(RES_VAUX3, TWL4030_RESCONFIG_UNDEF, 0, 0), 788 TWL_REMAP_SLEEP(RES_VAUX4, TWL4030_RESCONFIG_UNDEF, 0, 0), 789 TWL_REMAP_SLEEP(RES_VMMC1, TWL4030_RESCONFIG_UNDEF, 0, 0), 790 TWL_REMAP_SLEEP(RES_VMMC2, TWL4030_RESCONFIG_UNDEF, 0, 0), 791 TWL_REMAP_OFF(RES_VPLL1, DEV_GRP_P1, 3, 1), 792 TWL_REMAP_SLEEP(RES_VPLL2, DEV_GRP_P1, 0, 0), 793 TWL_REMAP_SLEEP(RES_VSIM, TWL4030_RESCONFIG_UNDEF, 0, 0), 794 TWL_REMAP_SLEEP(RES_VDAC, TWL4030_RESCONFIG_UNDEF, 0, 0), 795 TWL_REMAP_SLEEP(RES_VINTANA1, TWL_DEV_GRP_P123, 1, 2), 796 TWL_REMAP_SLEEP(RES_VINTANA2, TWL_DEV_GRP_P123, 0, 2), 797 TWL_REMAP_SLEEP(RES_VINTDIG, TWL_DEV_GRP_P123, 1, 2), 798 TWL_REMAP_SLEEP(RES_VIO, TWL_DEV_GRP_P123, 2, 2), 799 TWL_REMAP_OFF(RES_VDD1, DEV_GRP_P1, 4, 1), 800 TWL_REMAP_OFF(RES_VDD2, DEV_GRP_P1, 3, 1), 801 TWL_REMAP_SLEEP(RES_VUSB_1V5, TWL4030_RESCONFIG_UNDEF, 0, 0), 802 TWL_REMAP_SLEEP(RES_VUSB_1V8, TWL4030_RESCONFIG_UNDEF, 0, 0), 803 TWL_REMAP_SLEEP(RES_VUSB_3V1, TWL_DEV_GRP_P123, 0, 0), 804 /* Resource #20 USB charge pump skipped */ 805 TWL_REMAP_SLEEP(RES_REGEN, TWL_DEV_GRP_P123, 2, 1), 806 TWL_REMAP_SLEEP(RES_NRES_PWRON, TWL_DEV_GRP_P123, 0, 1), 807 TWL_REMAP_SLEEP(RES_CLKEN, TWL_DEV_GRP_P123, 3, 2), 808 TWL_REMAP_SLEEP(RES_SYSEN, TWL_DEV_GRP_P123, 6, 1), 809 TWL_REMAP_SLEEP(RES_HFCLKOUT, DEV_GRP_P3, 0, 2), 810 TWL_REMAP_SLEEP(RES_32KCLKOUT, TWL_DEV_GRP_P123, 0, 0), 811 TWL_REMAP_SLEEP(RES_RESET, TWL_DEV_GRP_P123, 6, 0), 812 TWL_REMAP_SLEEP(RES_MAIN_REF, TWL_DEV_GRP_P123, 0, 0), 813 { /* Terminator */ }, 814 }; 815 816 static struct twl4030_power_data omap3_idle = { 817 .scripts = omap3_idle_scripts, 818 .num = ARRAY_SIZE(omap3_idle_scripts), 819 .resource_config = omap3_idle_rconfig, 820 }; 821 822 /* Disable 32 KiHz oscillator during idle */ 823 static struct twl4030_resconfig osc_off_rconfig[] = { 824 TWL_REMAP_OFF(RES_CLKEN, DEV_GRP_P1 | DEV_GRP_P3, 3, 2), 825 { /* Terminator */ }, 826 }; 827 828 static struct twl4030_power_data osc_off_idle = { 829 .scripts = omap3_idle_scripts, 830 .num = ARRAY_SIZE(omap3_idle_scripts), 831 .resource_config = omap3_idle_rconfig, 832 .board_config = osc_off_rconfig, 833 }; 834 835 static struct twl4030_power_data omap3_idle_ac_quirk = { 836 .scripts = omap3_idle_scripts, 837 .num = ARRAY_SIZE(omap3_idle_scripts), 838 .resource_config = omap3_idle_rconfig, 839 .ac_charger_quirk = true, 840 }; 841 842 static struct twl4030_power_data omap3_idle_ac_quirk_osc_off = { 843 .scripts = omap3_idle_scripts, 844 .num = ARRAY_SIZE(omap3_idle_scripts), 845 .resource_config = omap3_idle_rconfig, 846 .board_config = osc_off_rconfig, 847 .ac_charger_quirk = true, 848 }; 849 850 static const struct of_device_id twl4030_power_of_match[] = { 851 { 852 .compatible = "ti,twl4030-power", 853 }, 854 { 855 .compatible = "ti,twl4030-power-reset", 856 .data = &omap3_reset, 857 }, 858 { 859 .compatible = "ti,twl4030-power-idle", 860 .data = &omap3_idle, 861 }, 862 { 863 .compatible = "ti,twl4030-power-idle-osc-off", 864 .data = &osc_off_idle, 865 }, 866 { 867 .compatible = "ti,twl4030-power-omap3-sdp", 868 .data = &omap3_idle_ac_quirk, 869 }, 870 { 871 .compatible = "ti,twl4030-power-omap3-ldp", 872 .data = &omap3_idle_ac_quirk_osc_off, 873 }, 874 { 875 .compatible = "ti,twl4030-power-omap3-evm", 876 .data = &omap3_idle_ac_quirk, 877 }, 878 { }, 879 }; 880 MODULE_DEVICE_TABLE(of, twl4030_power_of_match); 881 #endif /* CONFIG_OF */ 882 883 static int twl4030_power_probe(struct platform_device *pdev) 884 { 885 const struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev); 886 struct device_node *node = pdev->dev.of_node; 887 int err = 0; 888 int err2 = 0; 889 u8 val; 890 891 if (!pdata && !node) { 892 dev_err(&pdev->dev, "Platform data is missing\n"); 893 return -EINVAL; 894 } 895 896 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, 897 TWL4030_PM_MASTER_PROTECT_KEY); 898 err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 899 TWL4030_PM_MASTER_KEY_CFG2, 900 TWL4030_PM_MASTER_PROTECT_KEY); 901 902 if (err) { 903 pr_err("TWL4030 Unable to unlock registers\n"); 904 return err; 905 } 906 907 if (node) 908 pdata = device_get_match_data(&pdev->dev); 909 910 if (pdata) { 911 err = twl4030_power_configure_scripts(pdata); 912 if (err) { 913 pr_err("TWL4030 failed to load scripts\n"); 914 goto relock; 915 } 916 err = twl4030_power_configure_resources(pdata); 917 if (err) { 918 pr_err("TWL4030 failed to configure resource\n"); 919 goto relock; 920 } 921 } 922 923 /* Board has to be wired properly to use this feature */ 924 if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) { 925 /* Default for SEQ_OFFSYNC is set, lets ensure this */ 926 err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val, 927 TWL4030_PM_MASTER_CFG_P123_TRANSITION); 928 if (err) { 929 pr_warn("TWL4030 Unable to read registers\n"); 930 } else if (!(val & SEQ_OFFSYNC)) { 931 val |= SEQ_OFFSYNC; 932 err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val, 933 TWL4030_PM_MASTER_CFG_P123_TRANSITION); 934 if (err) { 935 pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n"); 936 goto relock; 937 } 938 } 939 940 pm_power_off = twl4030_power_off; 941 } 942 943 relock: 944 err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, 945 TWL4030_PM_MASTER_PROTECT_KEY); 946 if (err2) { 947 pr_err("TWL4030 Unable to relock registers\n"); 948 return err2; 949 } 950 951 return err; 952 } 953 954 static struct platform_driver twl4030_power_driver = { 955 .driver = { 956 .name = "twl4030_power", 957 .of_match_table = of_match_ptr(twl4030_power_of_match), 958 }, 959 .probe = twl4030_power_probe, 960 }; 961 962 module_platform_driver(twl4030_power_driver); 963 964 MODULE_AUTHOR("Nokia Corporation"); 965 MODULE_AUTHOR("Texas Instruments, Inc."); 966 MODULE_DESCRIPTION("Power management for TWL4030"); 967 MODULE_LICENSE("GPL"); 968 MODULE_ALIAS("platform:twl4030_power"); 969