xref: /linux/drivers/net/wireless/realtek/rtw89/pci.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_PCI_H__
6 #define __RTW89_PCI_H__
7 
8 #include "txrx.h"
9 
10 #define MDIO_PG0_G1 0
11 #define MDIO_PG1_G1 1
12 #define MDIO_PG0_G2 2
13 #define MDIO_PG1_G2 3
14 #define RAC_CTRL_PPR			0x00
15 #define RAC_ANA03			0x03
16 #define OOBS_SEN_MASK			GENMASK(5, 1)
17 #define RAC_ANA09			0x09
18 #define BAC_OOBS_SEL			BIT(4)
19 #define RAC_ANA0A			0x0A
20 #define B_BAC_EQ_SEL			BIT(5)
21 #define RAC_ANA0C			0x0C
22 #define B_PCIE_BIT_PSAVE		BIT(15)
23 #define RAC_ANA0D			0x0D
24 #define BAC_RX_TEST_EN			BIT(6)
25 #define RAC_ANA10			0x10
26 #define ADDR_SEL_PINOUT_DIS_VAL		0x3C4
27 #define B_PCIE_BIT_PINOUT_DIS		BIT(3)
28 #define RAC_REG_REV2			0x1B
29 #define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
30 #define PCIE_DPHY_DLY_25US		0x1
31 #define RAC_ANA19			0x19
32 #define B_PCIE_BIT_RD_SEL		BIT(2)
33 #define RAC_REG_FLD_0			0x1D
34 #define BAC_AUTOK_N_MASK		GENMASK(3, 2)
35 #define PCIE_AUTOK_4			0x3
36 #define RAC_ANA1E			0x1E
37 #define RAC_ANA1E_G1_VAL		0x66EA
38 #define RAC_ANA1E_G2_VAL		0x6EEA
39 #define RAC_ANA1F			0x1F
40 #define OOBS_LEVEL_MASK			GENMASK(12, 8)
41 #define RAC_ANA24			0x24
42 #define B_AX_DEGLITCH			GENMASK(11, 8)
43 #define RAC_ANA26			0x26
44 #define B_AX_RXEN			GENMASK(15, 14)
45 #define RAC_ANA2E			0x2E
46 #define RAC_ANA2E_VAL			0xFFFE
47 #define RAC_CTRL_PPR_V1			0x30
48 #define B_AX_CLK_CALIB_EN		BIT(12)
49 #define B_AX_CALIB_EN			BIT(13)
50 #define B_AX_DIV			GENMASK(15, 14)
51 #define RAC_SET_PPR_V1			0x31
52 
53 #define R_AX_DBI_FLAG			0x1090
54 #define B_AX_DBI_RFLAG			BIT(17)
55 #define B_AX_DBI_WFLAG			BIT(16)
56 #define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
57 #define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
58 #define B_AX_DBI_2LSB			GENMASK(1, 0)
59 #define R_AX_DBI_WDATA			0x1094
60 #define R_AX_DBI_RDATA			0x1098
61 
62 #define R_AX_MDIO_WDATA			0x10A4
63 #define R_AX_MDIO_RDATA			0x10A6
64 
65 #define R_AX_PCIE_PS_CTRL_V1		0x3008
66 #define B_AX_CMAC_EXIT_L1_EN		BIT(7)
67 #define B_AX_DMAC0_EXIT_L1_EN		BIT(6)
68 #define B_AX_SEL_XFER_PENDING		BIT(3)
69 #define B_AX_SEL_REQ_ENTR_L1		BIT(2)
70 #define B_AX_SEL_REQ_EXIT_L1		BIT(0)
71 
72 #define R_AX_PCIE_MIX_CFG_V1		0x300C
73 #define B_AX_ASPM_CTRL_L1		BIT(17)
74 #define B_AX_ASPM_CTRL_L0		BIT(16)
75 #define B_AX_ASPM_CTRL_MASK		GENMASK(17, 16)
76 #define B_AX_XFER_PENDING_FW		BIT(11)
77 #define B_AX_XFER_PENDING		BIT(10)
78 #define B_AX_REQ_EXIT_L1		BIT(9)
79 #define B_AX_REQ_ENTR_L1		BIT(8)
80 #define B_AX_L1SUB_DISABLE		BIT(0)
81 
82 #define R_AX_L1_CLK_CTRL		0x3010
83 #define B_AX_CLK_REQ_N			BIT(1)
84 
85 #define R_AX_PCIE_BG_CLR		0x303C
86 #define B_AX_BG_CLR_ASYNC_M3		BIT(4)
87 
88 #define R_AX_PCIE_LAT_CTRL		0x3044
89 #define B_AX_CLK_REQ_SEL_OPT		BIT(1)
90 #define B_AX_CLK_REQ_SEL		BIT(0)
91 
92 #define R_AX_PCIE_IO_RCY_M1 0x3100
93 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
94 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
95 #define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
96 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
97 
98 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
99 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
100 
101 #define R_AX_PCIE_IO_RCY_M2 0x310C
102 #define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
103 #define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
104 #define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
105 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
106 
107 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
108 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
109 
110 #define R_AX_PCIE_IO_RCY_E0 0x3118
111 #define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
112 #define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
113 #define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
114 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
115 
116 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
117 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
118 
119 #define R_AX_PCIE_IO_RCY_S1 0x3124
120 #define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
121 #define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
122 #define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
123 #define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
124 #define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
125 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
126 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
127 
128 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
129 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
130 
131 #define R_RAC_DIRECT_OFFSET_G1 0x3800
132 #define FILTER_OUT_EQ_MASK GENMASK(14, 10)
133 #define R_RAC_DIRECT_OFFSET_G2 0x3880
134 #define REG_FILTER_OUT_MASK GENMASK(6, 2)
135 #define RAC_MULT 2
136 
137 #define RTW89_PCI_WR_RETRY_CNT		20
138 
139 /* Interrupts */
140 #define R_AX_HIMR0 0x01A0
141 #define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
142 #define B_AX_HALT_C2H_INT_EN BIT(21)
143 #define R_AX_HISR0 0x01A4
144 
145 #define R_AX_HIMR1 0x01A8
146 #define B_AX_GPIO18_INT_EN BIT(2)
147 #define B_AX_GPIO17_INT_EN BIT(1)
148 #define B_AX_GPIO16_INT_EN BIT(0)
149 
150 #define R_AX_HISR1 0x01AC
151 #define B_AX_GPIO18_INT BIT(2)
152 #define B_AX_GPIO17_INT BIT(1)
153 #define B_AX_GPIO16_INT BIT(0)
154 
155 #define R_AX_MDIO_CFG			0x10A0
156 #define B_AX_MDIO_PHY_ADDR_MASK		GENMASK(13, 12)
157 #define B_AX_MDIO_RFLAG			BIT(9)
158 #define B_AX_MDIO_WFLAG			BIT(8)
159 #define B_AX_MDIO_ADDR_MASK		GENMASK(4, 0)
160 
161 #define R_AX_PCIE_HIMR00	0x10B0
162 #define R_AX_HAXI_HIMR00 0x10B0
163 #define B_AX_HC00ISR_IND_INT_EN		BIT(27)
164 #define B_AX_HD1ISR_IND_INT_EN		BIT(26)
165 #define B_AX_HD0ISR_IND_INT_EN		BIT(25)
166 #define B_AX_HS0ISR_IND_INT_EN		BIT(24)
167 #define B_AX_HS0ISR_IND_INT_EN_WKARND	BIT(23)
168 #define B_AX_RETRAIN_INT_EN		BIT(21)
169 #define B_AX_RPQBD_FULL_INT_EN		BIT(20)
170 #define B_AX_RDU_INT_EN			BIT(19)
171 #define B_AX_RXDMA_STUCK_INT_EN		BIT(18)
172 #define B_AX_TXDMA_STUCK_INT_EN		BIT(17)
173 #define B_AX_PCIE_HOTRST_INT_EN		BIT(16)
174 #define B_AX_PCIE_FLR_INT_EN		BIT(15)
175 #define B_AX_PCIE_PERST_INT_EN		BIT(14)
176 #define B_AX_TXDMA_CH12_INT_EN		BIT(13)
177 #define B_AX_TXDMA_CH9_INT_EN		BIT(12)
178 #define B_AX_TXDMA_CH8_INT_EN		BIT(11)
179 #define B_AX_TXDMA_ACH7_INT_EN		BIT(10)
180 #define B_AX_TXDMA_ACH6_INT_EN		BIT(9)
181 #define B_AX_TXDMA_ACH5_INT_EN		BIT(8)
182 #define B_AX_TXDMA_ACH4_INT_EN		BIT(7)
183 #define B_AX_TXDMA_ACH3_INT_EN		BIT(6)
184 #define B_AX_TXDMA_ACH2_INT_EN		BIT(5)
185 #define B_AX_TXDMA_ACH1_INT_EN		BIT(4)
186 #define B_AX_TXDMA_ACH0_INT_EN		BIT(3)
187 #define B_AX_RPQDMA_INT_EN		BIT(2)
188 #define B_AX_RXP1DMA_INT_EN		BIT(1)
189 #define B_AX_RXDMA_INT_EN		BIT(0)
190 
191 #define R_AX_PCIE_HISR00	0x10B4
192 #define R_AX_HAXI_HISR00 0x10B4
193 #define B_AX_HC00ISR_IND_INT		BIT(27)
194 #define B_AX_HD1ISR_IND_INT		BIT(26)
195 #define B_AX_HD0ISR_IND_INT		BIT(25)
196 #define B_AX_HS0ISR_IND_INT		BIT(24)
197 #define B_AX_RETRAIN_INT		BIT(21)
198 #define B_AX_RPQBD_FULL_INT		BIT(20)
199 #define B_AX_RDU_INT			BIT(19)
200 #define B_AX_RXDMA_STUCK_INT		BIT(18)
201 #define B_AX_TXDMA_STUCK_INT		BIT(17)
202 #define B_AX_PCIE_HOTRST_INT		BIT(16)
203 #define B_AX_PCIE_FLR_INT		BIT(15)
204 #define B_AX_PCIE_PERST_INT		BIT(14)
205 #define B_AX_TXDMA_CH12_INT		BIT(13)
206 #define B_AX_TXDMA_CH9_INT		BIT(12)
207 #define B_AX_TXDMA_CH8_INT		BIT(11)
208 #define B_AX_TXDMA_ACH7_INT		BIT(10)
209 #define B_AX_TXDMA_ACH6_INT		BIT(9)
210 #define B_AX_TXDMA_ACH5_INT		BIT(8)
211 #define B_AX_TXDMA_ACH4_INT		BIT(7)
212 #define B_AX_TXDMA_ACH3_INT		BIT(6)
213 #define B_AX_TXDMA_ACH2_INT		BIT(5)
214 #define B_AX_TXDMA_ACH1_INT		BIT(4)
215 #define B_AX_TXDMA_ACH0_INT		BIT(3)
216 #define B_AX_RPQDMA_INT			BIT(2)
217 #define B_AX_RXP1DMA_INT		BIT(1)
218 #define B_AX_RXDMA_INT			BIT(0)
219 
220 #define R_AX_HAXI_IDCT_MSK 0x10B8
221 #define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
222 #define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
223 #define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
224 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
225 
226 #define R_AX_HAXI_IDCT 0x10BC
227 #define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
228 #define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
229 #define B_AX_RXMDA_STUCK_IDCT BIT(1)
230 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
231 
232 #define R_AX_HAXI_HIMR10 0x11E0
233 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
234 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
235 
236 #define R_AX_PCIE_HIMR10	0x13B0
237 #define B_AX_HC10ISR_IND_INT_EN		BIT(28)
238 #define B_AX_TXDMA_CH11_INT_EN		BIT(12)
239 #define B_AX_TXDMA_CH10_INT_EN		BIT(11)
240 
241 #define R_AX_PCIE_HISR10	0x13B4
242 #define B_AX_HC10ISR_IND_INT		BIT(28)
243 #define B_AX_TXDMA_CH11_INT		BIT(12)
244 #define B_AX_TXDMA_CH10_INT		BIT(11)
245 
246 #define R_AX_PCIE_HIMR00_V1 0x30B0
247 #define B_AX_HCI_AXIDMA_INT_EN BIT(29)
248 #define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
249 #define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
250 #define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
251 #define B_AX_HS1ISR_IND_INT_EN BIT(25)
252 #define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
253 
254 #define R_AX_PCIE_HISR00_V1 0x30B4
255 #define B_AX_HCI_AXIDMA_INT BIT(29)
256 #define B_AX_HC00ISR_IND_INT_V1 BIT(28)
257 #define B_AX_HD1ISR_IND_INT_V1 BIT(27)
258 #define B_AX_HD0ISR_IND_INT_V1 BIT(26)
259 #define B_AX_HS1ISR_IND_INT BIT(25)
260 #define B_AX_PCIE_DBG_STE_INT BIT(13)
261 
262 #define R_BE_PCIE_FRZ_CLK 0x3004
263 #define B_BE_PCIE_FRZ_MAC_HW_RST BIT(31)
264 #define B_BE_PCIE_FRZ_CFG_SPC_RST BIT(30)
265 #define B_BE_PCIE_FRZ_ELBI_RST BIT(29)
266 #define B_BE_PCIE_MAC_IS_ACTIVE BIT(28)
267 #define B_BE_PCIE_FRZ_RTK_HW_RST BIT(27)
268 #define B_BE_PCIE_FRZ_REG_RST BIT(26)
269 #define B_BE_PCIE_FRZ_ANA_RST BIT(25)
270 #define B_BE_PCIE_FRZ_WLAN_RST BIT(24)
271 #define B_BE_PCIE_FRZ_FLR_RST BIT(23)
272 #define B_BE_PCIE_FRZ_RET_NON_STKY_RST BIT(22)
273 #define B_BE_PCIE_FRZ_RET_STKY_RST BIT(21)
274 #define B_BE_PCIE_FRZ_NON_STKY_RST BIT(20)
275 #define B_BE_PCIE_FRZ_STKY_RST BIT(19)
276 #define B_BE_PCIE_FRZ_RET_CORE_RST BIT(18)
277 #define B_BE_PCIE_FRZ_PWR_RST BIT(17)
278 #define B_BE_PCIE_FRZ_PERST_RST BIT(16)
279 #define B_BE_PCIE_FRZ_PHY_ALOAD BIT(15)
280 #define B_BE_PCIE_FRZ_PHY_HW_RST BIT(14)
281 #define B_BE_PCIE_DBG_CLK BIT(4)
282 #define B_BE_PCIE_EN_CLK BIT(3)
283 #define B_BE_PCIE_DBI_ACLK_ACT BIT(2)
284 #define B_BE_PCIE_S1_ACLK_ACT BIT(1)
285 #define B_BE_PCIE_EN_AUX_CLK BIT(0)
286 
287 #define R_BE_PCIE_PS_CTRL 0x3008
288 #define B_BE_RSM_L0S_EN BIT(8)
289 #define B_BE_CMAC_EXIT_L1_EN BIT(7)
290 #define B_BE_DMAC0_EXIT_L1_EN BIT(6)
291 #define B_BE_FORCE_L0 BIT(5)
292 #define B_BE_DBI_RO_WR_DISABLE BIT(4)
293 #define B_BE_SEL_XFER_PENDING BIT(3)
294 #define B_BE_SEL_REQ_ENTR_L1 BIT(2)
295 #define B_BE_PCIE_EN_SWENT_L23 BIT(1)
296 #define B_BE_SEL_REQ_EXIT_L1 BIT(0)
297 
298 #define R_BE_PCIE_MIX_CFG 0x300C
299 #define B_BE_L1SS_TIMEOUT_CTRL BIT(18)
300 #define B_BE_ASPM_CTRL_L1 BIT(17)
301 #define B_BE_ASPM_CTRL_L0 BIT(16)
302 #define B_BE_XFER_PENDING_FW BIT(11)
303 #define B_BE_XFER_PENDING BIT(10)
304 #define B_BE_REQ_EXIT_L1 BIT(9)
305 #define B_BE_REQ_ENTR_L1 BIT(8)
306 #define B_BE_L1SUB_ENABLE BIT(0)
307 
308 #define R_BE_L1_CLK_CTRL 0x3010
309 #define B_BE_RAS_SD_HOLD_LTSSM BIT(12)
310 #define B_BE_CLK_REQ_N BIT(1)
311 #define B_BE_CLK_PM_EN BIT(0)
312 
313 #define R_BE_PCIE_LAT_CTRL 0x3044
314 #define B_BE_ELBI_PHY_REMAP_MASK GENMASK(29, 24)
315 #define B_BE_SYS_SUS_L12_EN BIT(17)
316 #define B_BE_MDIO_S_EN BIT(16)
317 #define B_BE_SYM_AUX_CLK_SEL BIT(15)
318 #define B_BE_RTK_LDO_POWER_LATENCY_MASK GENMASK(11, 10)
319 #define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)
320 #define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)
321 #define B_BE_RTK_PM_SEL_OPT BIT(1)
322 #define B_BE_CLK_REQ_SEL BIT(0)
323 
324 #define R_BE_PCIE_HIMR0 0x30B0
325 #define B_BE_PCIE_HB1_IND_INTA_IMR BIT(31)
326 #define B_BE_PCIE_HB0_IND_INTA_IMR BIT(30)
327 #define B_BE_HCI_AXIDMA_INTA_IMR BIT(29)
328 #define B_BE_HC0_IND_INTA_IMR BIT(28)
329 #define B_BE_HD1_IND_INTA_IMR BIT(27)
330 #define B_BE_HD0_IND_INTA_IMR BIT(26)
331 #define B_BE_HS1_IND_INTA_IMR BIT(25)
332 #define B_BE_HS0_IND_INTA_IMR BIT(24)
333 #define B_BE_PCIE_HOTRST_INT_EN BIT(16)
334 #define B_BE_PCIE_FLR_INT_EN BIT(15)
335 #define B_BE_PCIE_PERST_INT_EN BIT(14)
336 #define B_BE_PCIE_DBG_STE_INT_EN BIT(13)
337 #define B_BE_HB1_IND_INT_EN0 BIT(9)
338 #define B_BE_HB0_IND_INT_EN0 BIT(8)
339 #define B_BE_HC1_IND_INT_EN0 BIT(7)
340 #define B_BE_HCI_AXIDMA_INT_EN0 BIT(5)
341 #define B_BE_HC0_IND_INT_EN0 BIT(4)
342 #define B_BE_HD1_IND_INT_EN0 BIT(3)
343 #define B_BE_HD0_IND_INT_EN0 BIT(2)
344 #define B_BE_HS1_IND_INT_EN0 BIT(1)
345 #define B_BE_HS0_IND_INT_EN0 BIT(0)
346 
347 #define R_BE_PCIE_HISR 0x30B4
348 #define B_BE_PCIE_HOTRST_INT BIT(16)
349 #define B_BE_PCIE_FLR_INT BIT(15)
350 #define B_BE_PCIE_PERST_INT BIT(14)
351 #define B_BE_PCIE_DBG_STE_INT BIT(13)
352 #define B_BE_HB1IMR_IND BIT(9)
353 #define B_BE_HB0IMR_IND BIT(8)
354 #define B_BE_HC1ISR_IND_INT BIT(7)
355 #define B_BE_HCI_AXIDMA_INT BIT(5)
356 #define B_BE_HC0ISR_IND_INT BIT(4)
357 #define B_BE_HD1ISR_IND_INT BIT(3)
358 #define B_BE_HD0ISR_IND_INT BIT(2)
359 #define B_BE_HS1ISR_IND_INT BIT(1)
360 #define B_BE_HS0ISR_IND_INT BIT(0)
361 
362 #define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
363 #define B_BE_PCIE_RX_RX1P1_IMR0_V1 BIT(23)
364 #define B_BE_PCIE_RX_RX0P1_IMR0_V1 BIT(22)
365 #define B_BE_PCIE_RX_ROQ1_IMR0_V1 BIT(21)
366 #define B_BE_PCIE_RX_RPQ1_IMR0_V1 BIT(20)
367 #define B_BE_PCIE_RX_RX1P2_IMR0_V1 BIT(19)
368 #define B_BE_PCIE_RX_ROQ0_IMR0_V1 BIT(18)
369 #define B_BE_PCIE_RX_RPQ0_IMR0_V1 BIT(17)
370 #define B_BE_PCIE_RX_RX0P2_IMR0_V1 BIT(16)
371 #define B_BE_PCIE_TX_CH14_IMR0 BIT(14)
372 #define B_BE_PCIE_TX_CH13_IMR0 BIT(13)
373 #define B_BE_PCIE_TX_CH12_IMR0 BIT(12)
374 #define B_BE_PCIE_TX_CH11_IMR0 BIT(11)
375 #define B_BE_PCIE_TX_CH10_IMR0 BIT(10)
376 #define B_BE_PCIE_TX_CH9_IMR0 BIT(9)
377 #define B_BE_PCIE_TX_CH8_IMR0 BIT(8)
378 #define B_BE_PCIE_TX_CH7_IMR0 BIT(7)
379 #define B_BE_PCIE_TX_CH6_IMR0 BIT(6)
380 #define B_BE_PCIE_TX_CH5_IMR0 BIT(5)
381 #define B_BE_PCIE_TX_CH4_IMR0 BIT(4)
382 #define B_BE_PCIE_TX_CH3_IMR0 BIT(3)
383 #define B_BE_PCIE_TX_CH2_IMR0 BIT(2)
384 #define B_BE_PCIE_TX_CH1_IMR0 BIT(1)
385 #define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
386 
387 #define R_BE_PCIE_DMA_ISR 0x30BC
388 #define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23)
389 #define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22)
390 #define B_BE_PCIE_RX_ROQ1_ISR_V1 BIT(21)
391 #define B_BE_PCIE_RX_RPQ1_ISR_V1 BIT(20)
392 #define B_BE_PCIE_RX_RX1P2_ISR_V1 BIT(19)
393 #define B_BE_PCIE_RX_ROQ0_ISR_V1 BIT(18)
394 #define B_BE_PCIE_RX_RPQ0_ISR_V1 BIT(17)
395 #define B_BE_PCIE_RX_RX0P2_ISR_V1 BIT(16)
396 #define B_BE_PCIE_TX_CH14_ISR BIT(14)
397 #define B_BE_PCIE_TX_CH13_ISR BIT(13)
398 #define B_BE_PCIE_TX_CH12_ISR BIT(12)
399 #define B_BE_PCIE_TX_CH11_ISR BIT(11)
400 #define B_BE_PCIE_TX_CH10_ISR BIT(10)
401 #define B_BE_PCIE_TX_CH9_ISR BIT(9)
402 #define B_BE_PCIE_TX_CH8_ISR BIT(8)
403 #define B_BE_PCIE_TX_CH7_ISR BIT(7)
404 #define B_BE_PCIE_TX_CH6_ISR BIT(6)
405 #define B_BE_PCIE_TX_CH5_ISR BIT(5)
406 #define B_BE_PCIE_TX_CH4_ISR BIT(4)
407 #define B_BE_PCIE_TX_CH3_ISR BIT(3)
408 #define B_BE_PCIE_TX_CH2_ISR BIT(2)
409 #define B_BE_PCIE_TX_CH1_ISR BIT(1)
410 #define B_BE_PCIE_TX_CH0_ISR BIT(0)
411 
412 #define R_BE_HAXI_HIMR00 0xB0B0
413 #define B_BE_RDU_CH5_INT_IMR_V1 BIT(30)
414 #define B_BE_RDU_CH4_INT_IMR_V1 BIT(29)
415 #define B_BE_RDU_CH3_INT_IMR_V1 BIT(28)
416 #define B_BE_RDU_CH2_INT_IMR_V1 BIT(27)
417 #define B_BE_RDU_CH1_INT_IMR_V1 BIT(26)
418 #define B_BE_RDU_CH0_INT_IMR_V1 BIT(25)
419 #define B_BE_RXDMA_STUCK_INT_EN_V1 BIT(24)
420 #define B_BE_TXDMA_STUCK_INT_EN_V1 BIT(23)
421 #define B_BE_TXDMA_CH14_INT_EN_V1 BIT(22)
422 #define B_BE_TXDMA_CH13_INT_EN_V1 BIT(21)
423 #define B_BE_TXDMA_CH12_INT_EN_V1 BIT(20)
424 #define B_BE_TXDMA_CH11_INT_EN_V1 BIT(19)
425 #define B_BE_TXDMA_CH10_INT_EN_V1 BIT(18)
426 #define B_BE_TXDMA_CH9_INT_EN_V1 BIT(17)
427 #define B_BE_TXDMA_CH8_INT_EN_V1 BIT(16)
428 #define B_BE_TXDMA_CH7_INT_EN_V1 BIT(15)
429 #define B_BE_TXDMA_CH6_INT_EN_V1 BIT(14)
430 #define B_BE_TXDMA_CH5_INT_EN_V1 BIT(13)
431 #define B_BE_TXDMA_CH4_INT_EN_V1 BIT(12)
432 #define B_BE_TXDMA_CH3_INT_EN_V1 BIT(11)
433 #define B_BE_TXDMA_CH2_INT_EN_V1 BIT(10)
434 #define B_BE_TXDMA_CH1_INT_EN_V1 BIT(9)
435 #define B_BE_TXDMA_CH0_INT_EN_V1 BIT(8)
436 #define B_BE_RX1P1DMA_INT_EN_V1 BIT(7)
437 #define B_BE_RX0P1DMA_INT_EN_V1 BIT(6)
438 #define B_BE_RO1DMA_INT_EN BIT(5)
439 #define B_BE_RP1DMA_INT_EN BIT(4)
440 #define B_BE_RX1DMA_INT_EN BIT(3)
441 #define B_BE_RO0DMA_INT_EN BIT(2)
442 #define B_BE_RP0DMA_INT_EN BIT(1)
443 #define B_BE_RX0DMA_INT_EN BIT(0)
444 
445 #define R_BE_HAXI_HISR00 0xB0B4
446 #define B_BE_RDU_CH6_INT BIT(28)
447 #define B_BE_RDU_CH5_INT BIT(27)
448 #define B_BE_RDU_CH4_INT BIT(26)
449 #define B_BE_RDU_CH2_INT BIT(25)
450 #define B_BE_RDU_CH1_INT BIT(24)
451 #define B_BE_RDU_CH0_INT BIT(23)
452 #define B_BE_RXDMA_STUCK_INT BIT(22)
453 #define B_BE_TXDMA_STUCK_INT BIT(21)
454 #define B_BE_TXDMA_CH14_INT BIT(20)
455 #define B_BE_TXDMA_CH13_INT BIT(19)
456 #define B_BE_TXDMA_CH12_INT BIT(18)
457 #define B_BE_TXDMA_CH11_INT BIT(17)
458 #define B_BE_TXDMA_CH10_INT BIT(16)
459 #define B_BE_TXDMA_CH9_INT BIT(15)
460 #define B_BE_TXDMA_CH8_INT BIT(14)
461 #define B_BE_TXDMA_CH7_INT BIT(13)
462 #define B_BE_TXDMA_CH6_INT BIT(12)
463 #define B_BE_TXDMA_CH5_INT BIT(11)
464 #define B_BE_TXDMA_CH4_INT BIT(10)
465 #define B_BE_TXDMA_CH3_INT BIT(9)
466 #define B_BE_TXDMA_CH2_INT BIT(8)
467 #define B_BE_TXDMA_CH1_INT BIT(7)
468 #define B_BE_TXDMA_CH0_INT BIT(6)
469 #define B_BE_RPQ1DMA_INT BIT(5)
470 #define B_BE_RX1P1DMA_INT BIT(4)
471 #define B_BE_RX1DMA_INT BIT(3)
472 #define B_BE_RPQ0DMA_INT BIT(2)
473 #define B_BE_RX0P1DMA_INT BIT(1)
474 #define B_BE_RX0DMA_INT BIT(0)
475 
476 /* TX/RX */
477 #define R_AX_DRV_FW_HSK_0	0x01B0
478 #define R_AX_DRV_FW_HSK_1	0x01B4
479 #define R_AX_DRV_FW_HSK_2	0x01B8
480 #define R_AX_DRV_FW_HSK_3	0x01BC
481 #define R_AX_DRV_FW_HSK_4	0x01C0
482 #define R_AX_DRV_FW_HSK_5	0x01C4
483 #define R_AX_DRV_FW_HSK_6	0x01C8
484 #define R_AX_DRV_FW_HSK_7	0x01CC
485 
486 #define R_AX_RXQ_RXBD_IDX	0x1050
487 #define R_AX_RPQ_RXBD_IDX	0x1054
488 #define R_AX_ACH0_TXBD_IDX	0x1058
489 #define R_AX_ACH1_TXBD_IDX	0x105C
490 #define R_AX_ACH2_TXBD_IDX	0x1060
491 #define R_AX_ACH3_TXBD_IDX	0x1064
492 #define R_AX_ACH4_TXBD_IDX	0x1068
493 #define R_AX_ACH5_TXBD_IDX	0x106C
494 #define R_AX_ACH6_TXBD_IDX	0x1070
495 #define R_AX_ACH7_TXBD_IDX	0x1074
496 #define R_AX_CH8_TXBD_IDX	0x1078 /* Management Queue band 0 */
497 #define R_AX_CH9_TXBD_IDX	0x107C /* HI Queue band 0 */
498 #define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */
499 #define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */
500 #define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */
501 #define R_AX_CH10_TXBD_IDX_V1	0x11D0
502 #define R_AX_CH11_TXBD_IDX_V1	0x11D4
503 #define R_AX_RXQ_RXBD_IDX_V1	0x1218
504 #define R_AX_RPQ_RXBD_IDX_V1	0x121C
505 #define TXBD_HW_IDX_MASK	GENMASK(27, 16)
506 #define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
507 
508 #define R_AX_ACH0_TXBD_DESA_L	0x1110
509 #define R_AX_ACH0_TXBD_DESA_H	0x1114
510 #define R_AX_ACH1_TXBD_DESA_L	0x1118
511 #define R_AX_ACH1_TXBD_DESA_H	0x111C
512 #define R_AX_ACH2_TXBD_DESA_L	0x1120
513 #define R_AX_ACH2_TXBD_DESA_H	0x1124
514 #define R_AX_ACH3_TXBD_DESA_L	0x1128
515 #define R_AX_ACH3_TXBD_DESA_H	0x112C
516 #define R_AX_ACH4_TXBD_DESA_L	0x1130
517 #define R_AX_ACH4_TXBD_DESA_H	0x1134
518 #define R_AX_ACH5_TXBD_DESA_L	0x1138
519 #define R_AX_ACH5_TXBD_DESA_H	0x113C
520 #define R_AX_ACH6_TXBD_DESA_L	0x1140
521 #define R_AX_ACH6_TXBD_DESA_H	0x1144
522 #define R_AX_ACH7_TXBD_DESA_L	0x1148
523 #define R_AX_ACH7_TXBD_DESA_H	0x114C
524 #define R_AX_CH8_TXBD_DESA_L	0x1150
525 #define R_AX_CH8_TXBD_DESA_H	0x1154
526 #define R_AX_CH9_TXBD_DESA_L	0x1158
527 #define R_AX_CH9_TXBD_DESA_H	0x115C
528 #define R_AX_CH10_TXBD_DESA_L	0x1358
529 #define R_AX_CH10_TXBD_DESA_H	0x135C
530 #define R_AX_CH11_TXBD_DESA_L	0x1360
531 #define R_AX_CH11_TXBD_DESA_H	0x1364
532 #define R_AX_CH12_TXBD_DESA_L	0x1160
533 #define R_AX_CH12_TXBD_DESA_H	0x1164
534 #define R_AX_RXQ_RXBD_DESA_L	0x1100
535 #define R_AX_RXQ_RXBD_DESA_H	0x1104
536 #define R_AX_RPQ_RXBD_DESA_L	0x1108
537 #define R_AX_RPQ_RXBD_DESA_H	0x110C
538 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
539 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
540 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
541 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
542 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
543 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
544 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
545 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
546 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
547 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
548 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
549 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
550 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
551 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
552 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
553 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
554 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
555 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
556 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
557 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
558 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
559 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
560 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
561 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
562 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
563 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
564 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
565 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
566 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
567 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
568 #define B_AX_DESC_NUM_MSK		GENMASK(11, 0)
569 
570 #define R_AX_RXQ_RXBD_NUM	0x1020
571 #define R_AX_RPQ_RXBD_NUM	0x1022
572 #define R_AX_ACH0_TXBD_NUM	0x1024
573 #define R_AX_ACH1_TXBD_NUM	0x1026
574 #define R_AX_ACH2_TXBD_NUM	0x1028
575 #define R_AX_ACH3_TXBD_NUM	0x102A
576 #define R_AX_ACH4_TXBD_NUM	0x102C
577 #define R_AX_ACH5_TXBD_NUM	0x102E
578 #define R_AX_ACH6_TXBD_NUM	0x1030
579 #define R_AX_ACH7_TXBD_NUM	0x1032
580 #define R_AX_CH8_TXBD_NUM	0x1034
581 #define R_AX_CH9_TXBD_NUM	0x1036
582 #define R_AX_CH10_TXBD_NUM	0x1338
583 #define R_AX_CH11_TXBD_NUM	0x133A
584 #define R_AX_CH12_TXBD_NUM	0x1038
585 #define R_AX_RXQ_RXBD_NUM_V1	0x1210
586 #define R_AX_RPQ_RXBD_NUM_V1	0x1212
587 #define R_AX_CH10_TXBD_NUM_V1	0x1438
588 #define R_AX_CH11_TXBD_NUM_V1	0x143A
589 
590 #define R_AX_ACH0_BDRAM_CTRL	0x1200
591 #define R_AX_ACH1_BDRAM_CTRL	0x1204
592 #define R_AX_ACH2_BDRAM_CTRL	0x1208
593 #define R_AX_ACH3_BDRAM_CTRL	0x120C
594 #define R_AX_ACH4_BDRAM_CTRL	0x1210
595 #define R_AX_ACH5_BDRAM_CTRL	0x1214
596 #define R_AX_ACH6_BDRAM_CTRL	0x1218
597 #define R_AX_ACH7_BDRAM_CTRL	0x121C
598 #define R_AX_CH8_BDRAM_CTRL	0x1220
599 #define R_AX_CH9_BDRAM_CTRL	0x1224
600 #define R_AX_CH10_BDRAM_CTRL	0x1320
601 #define R_AX_CH11_BDRAM_CTRL	0x1324
602 #define R_AX_CH12_BDRAM_CTRL	0x1228
603 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
604 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
605 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
606 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
607 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
608 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
609 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
610 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
611 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
612 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
613 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
614 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
615 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
616 #define BDRAM_SIDX_MASK		GENMASK(7, 0)
617 #define BDRAM_MAX_MASK		GENMASK(15, 8)
618 #define BDRAM_MIN_MASK		GENMASK(23, 16)
619 
620 #define R_AX_PCIE_INIT_CFG1	0x1000
621 #define B_AX_PCIE_RXRST_KEEP_REG	BIT(23)
622 #define B_AX_PCIE_TXRST_KEEP_REG	BIT(22)
623 #define B_AX_PCIE_PERST_KEEP_REG	BIT(21)
624 #define B_AX_PCIE_FLR_KEEP_REG		BIT(20)
625 #define B_AX_PCIE_TRAIN_KEEP_REG	BIT(19)
626 #define B_AX_RXBD_MODE			BIT(18)
627 #define B_AX_PCIE_MAX_RXDMA_MASK	GENMASK(16, 14)
628 #define B_AX_RXHCI_EN			BIT(13)
629 #define B_AX_LATENCY_CONTROL		BIT(12)
630 #define B_AX_TXHCI_EN			BIT(11)
631 #define B_AX_PCIE_MAX_TXDMA_MASK	GENMASK(10, 8)
632 #define B_AX_TX_TRUNC_MODE		BIT(5)
633 #define B_AX_RX_TRUNC_MODE		BIT(4)
634 #define B_AX_RST_BDRAM			BIT(3)
635 #define B_AX_DIS_RXDMA_PRE		BIT(2)
636 
637 #define R_AX_TXDMA_ADDR_H	0x10F0
638 #define R_AX_RXDMA_ADDR_H	0x10F4
639 
640 #define R_AX_PCIE_DMA_STOP1	0x1010
641 #define B_AX_STOP_PCIEIO		BIT(20)
642 #define B_AX_STOP_WPDMA			BIT(19)
643 #define B_AX_STOP_CH12			BIT(18)
644 #define B_AX_STOP_CH9			BIT(17)
645 #define B_AX_STOP_CH8			BIT(16)
646 #define B_AX_STOP_ACH7			BIT(15)
647 #define B_AX_STOP_ACH6			BIT(14)
648 #define B_AX_STOP_ACH5			BIT(13)
649 #define B_AX_STOP_ACH4			BIT(12)
650 #define B_AX_STOP_ACH3			BIT(11)
651 #define B_AX_STOP_ACH2			BIT(10)
652 #define B_AX_STOP_ACH1			BIT(9)
653 #define B_AX_STOP_ACH0			BIT(8)
654 #define B_AX_STOP_RPQ			BIT(1)
655 #define B_AX_STOP_RXQ			BIT(0)
656 #define B_AX_TX_STOP1_ALL		GENMASK(18, 8)
657 #define B_AX_TX_STOP1_MASK		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
658 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
659 					 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
660 					 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
661 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
662 					 B_AX_STOP_CH12)
663 #define B_AX_TX_STOP1_MASK_V1		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
664 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
665 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
666 					 B_AX_STOP_CH12)
667 
668 #define R_AX_PCIE_DMA_STOP2	0x1310
669 #define B_AX_STOP_CH11			BIT(1)
670 #define B_AX_STOP_CH10			BIT(0)
671 #define B_AX_TX_STOP2_ALL		GENMASK(1, 0)
672 
673 #define R_AX_TXBD_RWPTR_CLR1	0x1014
674 #define B_AX_CLR_CH12_IDX		BIT(10)
675 #define B_AX_CLR_CH9_IDX		BIT(9)
676 #define B_AX_CLR_CH8_IDX		BIT(8)
677 #define B_AX_CLR_ACH7_IDX		BIT(7)
678 #define B_AX_CLR_ACH6_IDX		BIT(6)
679 #define B_AX_CLR_ACH5_IDX		BIT(5)
680 #define B_AX_CLR_ACH4_IDX		BIT(4)
681 #define B_AX_CLR_ACH3_IDX		BIT(3)
682 #define B_AX_CLR_ACH2_IDX		BIT(2)
683 #define B_AX_CLR_ACH1_IDX		BIT(1)
684 #define B_AX_CLR_ACH0_IDX		BIT(0)
685 #define B_AX_TXBD_CLR1_ALL		GENMASK(10, 0)
686 
687 #define R_AX_RXBD_RWPTR_CLR	0x1018
688 #define B_AX_CLR_RPQ_IDX		BIT(1)
689 #define B_AX_CLR_RXQ_IDX		BIT(0)
690 #define B_AX_RXBD_CLR_ALL		GENMASK(1, 0)
691 
692 #define R_AX_TXBD_RWPTR_CLR2	0x1314
693 #define B_AX_CLR_CH11_IDX		BIT(1)
694 #define B_AX_CLR_CH10_IDX		BIT(0)
695 #define B_AX_TXBD_CLR2_ALL		GENMASK(1, 0)
696 
697 #define R_AX_PCIE_DMA_BUSY1	0x101C
698 #define B_AX_PCIEIO_RX_BUSY		BIT(22)
699 #define B_AX_PCIEIO_TX_BUSY		BIT(21)
700 #define B_AX_PCIEIO_BUSY		BIT(20)
701 #define B_AX_WPDMA_BUSY			BIT(19)
702 #define B_AX_CH12_BUSY			BIT(18)
703 #define B_AX_CH9_BUSY			BIT(17)
704 #define B_AX_CH8_BUSY			BIT(16)
705 #define B_AX_ACH7_BUSY			BIT(15)
706 #define B_AX_ACH6_BUSY			BIT(14)
707 #define B_AX_ACH5_BUSY			BIT(13)
708 #define B_AX_ACH4_BUSY			BIT(12)
709 #define B_AX_ACH3_BUSY			BIT(11)
710 #define B_AX_ACH2_BUSY			BIT(10)
711 #define B_AX_ACH1_BUSY			BIT(9)
712 #define B_AX_ACH0_BUSY			BIT(8)
713 #define B_AX_RPQ_BUSY			BIT(1)
714 #define B_AX_RXQ_BUSY			BIT(0)
715 #define DMA_BUSY1_CHECK		(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
716 				 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
717 				 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
718 				 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
719 #define DMA_BUSY1_CHECK_V1	(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
720 				 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
721 				 B_AX_CH12_BUSY)
722 
723 #define R_AX_PCIE_DMA_BUSY2	0x131C
724 #define B_AX_CH11_BUSY			BIT(1)
725 #define B_AX_CH10_BUSY			BIT(0)
726 
727 #define R_AX_WP_ADDR_H_SEL0_3 0x1334
728 #define R_AX_WP_ADDR_H_SEL4_7 0x1338
729 #define R_AX_WP_ADDR_H_SEL8_11 0x133C
730 #define R_AX_WP_ADDR_H_SEL12_15 0x1340
731 
732 #define R_BE_HAXI_DMA_STOP1 0xB010
733 #define B_BE_STOP_WPDMA BIT(31)
734 #define B_BE_STOP_CH14 BIT(14)
735 #define B_BE_STOP_CH13 BIT(13)
736 #define B_BE_STOP_CH12 BIT(12)
737 #define B_BE_STOP_CH11 BIT(11)
738 #define B_BE_STOP_CH10 BIT(10)
739 #define B_BE_STOP_CH9 BIT(9)
740 #define B_BE_STOP_CH8 BIT(8)
741 #define B_BE_STOP_CH7 BIT(7)
742 #define B_BE_STOP_CH6 BIT(6)
743 #define B_BE_STOP_CH5 BIT(5)
744 #define B_BE_STOP_CH4 BIT(4)
745 #define B_BE_STOP_CH3 BIT(3)
746 #define B_BE_STOP_CH2 BIT(2)
747 #define B_BE_STOP_CH1 BIT(1)
748 #define B_BE_STOP_CH0 BIT(0)
749 #define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
750 			    B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
751 			    B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
752 			    B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
753 			    B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
754 			    B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
755 			    B_BE_STOP_CH12)
756 
757 #define R_BE_CH0_TXBD_NUM_V1 0xB030
758 #define R_BE_CH1_TXBD_NUM_V1 0xB032
759 #define R_BE_CH2_TXBD_NUM_V1 0xB034
760 #define R_BE_CH3_TXBD_NUM_V1 0xB036
761 #define R_BE_CH4_TXBD_NUM_V1 0xB038
762 #define R_BE_CH5_TXBD_NUM_V1 0xB03A
763 #define R_BE_CH6_TXBD_NUM_V1 0xB03C
764 #define R_BE_CH7_TXBD_NUM_V1 0xB03E
765 #define R_BE_CH8_TXBD_NUM_V1 0xB040
766 #define R_BE_CH9_TXBD_NUM_V1 0xB042
767 #define R_BE_CH10_TXBD_NUM_V1 0xB044
768 #define R_BE_CH11_TXBD_NUM_V1 0xB046
769 #define R_BE_CH12_TXBD_NUM_V1 0xB048
770 #define R_BE_CH13_TXBD_NUM_V1 0xB04C
771 #define R_BE_CH14_TXBD_NUM_V1 0xB04E
772 
773 #define R_BE_RXQ0_RXBD_NUM_V1 0xB050
774 #define R_BE_RPQ0_RXBD_NUM_V1 0xB052
775 
776 #define R_BE_CH0_TXBD_IDX_V1 0xB100
777 #define R_BE_CH1_TXBD_IDX_V1 0xB104
778 #define R_BE_CH2_TXBD_IDX_V1 0xB108
779 #define R_BE_CH3_TXBD_IDX_V1 0xB10C
780 #define R_BE_CH4_TXBD_IDX_V1 0xB110
781 #define R_BE_CH5_TXBD_IDX_V1 0xB114
782 #define R_BE_CH6_TXBD_IDX_V1 0xB118
783 #define R_BE_CH7_TXBD_IDX_V1 0xB11C
784 #define R_BE_CH8_TXBD_IDX_V1 0xB120
785 #define R_BE_CH9_TXBD_IDX_V1 0xB124
786 #define R_BE_CH10_TXBD_IDX_V1 0xB128
787 #define R_BE_CH11_TXBD_IDX_V1 0xB12C
788 #define R_BE_CH12_TXBD_IDX_V1 0xB130
789 #define R_BE_CH13_TXBD_IDX_V1 0xB134
790 #define R_BE_CH14_TXBD_IDX_V1 0xB138
791 
792 #define R_BE_RXQ0_RXBD_IDX_V1 0xB160
793 #define R_BE_RPQ0_RXBD_IDX_V1 0xB164
794 
795 #define R_BE_CH0_TXBD_DESA_L_V1 0xB200
796 #define R_BE_CH0_TXBD_DESA_H_V1 0xB204
797 #define R_BE_CH1_TXBD_DESA_L_V1 0xB208
798 #define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
799 #define R_BE_CH2_TXBD_DESA_L_V1 0xB210
800 #define R_BE_CH2_TXBD_DESA_H_V1 0xB214
801 #define R_BE_CH3_TXBD_DESA_L_V1 0xB218
802 #define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
803 #define R_BE_CH4_TXBD_DESA_L_V1 0xB220
804 #define R_BE_CH4_TXBD_DESA_H_V1 0xB224
805 #define R_BE_CH5_TXBD_DESA_L_V1 0xB228
806 #define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
807 #define R_BE_CH6_TXBD_DESA_L_V1 0xB230
808 #define R_BE_CH6_TXBD_DESA_H_V1 0xB234
809 #define R_BE_CH7_TXBD_DESA_L_V1 0xB238
810 #define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
811 #define R_BE_CH8_TXBD_DESA_L_V1 0xB240
812 #define R_BE_CH8_TXBD_DESA_H_V1 0xB244
813 #define R_BE_CH9_TXBD_DESA_L_V1 0xB248
814 #define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
815 #define R_BE_CH10_TXBD_DESA_L_V1 0xB250
816 #define R_BE_CH10_TXBD_DESA_H_V1 0xB254
817 #define R_BE_CH11_TXBD_DESA_L_V1 0xB258
818 #define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
819 #define R_BE_CH12_TXBD_DESA_L_V1 0xB260
820 #define R_BE_CH12_TXBD_DESA_H_V1 0xB264
821 #define R_BE_CH13_TXBD_DESA_L_V1 0xB268
822 #define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
823 #define R_BE_CH14_TXBD_DESA_L_V1 0xB270
824 #define R_BE_CH14_TXBD_DESA_H_V1 0xB274
825 
826 #define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
827 #define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
828 #define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
829 #define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
830 
831 #define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420
832 #define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424
833 #define R_BE_WP_ADDR_H_SEL8_11_V1 0xB428
834 #define R_BE_WP_ADDR_H_SEL12_15_V1 0xB42C
835 
836 /* Configure */
837 #define R_AX_PCIE_INIT_CFG2		0x1004
838 #define B_AX_WD_ITVL_IDLE		GENMASK(27, 24)
839 #define B_AX_WD_ITVL_ACT		GENMASK(19, 16)
840 #define B_AX_PCIE_RX_APPLEN_MASK	GENMASK(13, 0)
841 
842 #define R_AX_PCIE_PS_CTRL		0x1008
843 #define B_AX_L1OFF_PWR_OFF_EN		BIT(5)
844 
845 #define R_AX_INT_MIT_RX			0x10D4
846 #define B_AX_RXMIT_RXP2_SEL		BIT(19)
847 #define B_AX_RXMIT_RXP1_SEL		BIT(18)
848 #define B_AX_RXTIMER_UNIT_MASK		GENMASK(17, 16)
849 #define AX_RXTIMER_UNIT_64US		0
850 #define AX_RXTIMER_UNIT_128US		1
851 #define AX_RXTIMER_UNIT_256US		2
852 #define AX_RXTIMER_UNIT_512US		3
853 #define B_AX_RXCOUNTER_MATCH_MASK	GENMASK(15, 8)
854 #define B_AX_RXTIMER_MATCH_MASK		GENMASK(7, 0)
855 
856 #define R_AX_DBG_ERR_FLAG_V1 0x1104
857 
858 #define R_AX_INT_MIT_RX_V1 0x1184
859 #define B_AX_RXMIT_RXP2_SEL_V1 BIT(19)
860 #define B_AX_RXMIT_RXP1_SEL_V1 BIT(18)
861 #define B_AX_MIT_RXTIMER_UNIT_MASK GENMASK(17, 16)
862 #define B_AX_MIT_RXCOUNTER_MATCH_MASK GENMASK(15, 8)
863 #define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
864 
865 #define R_AX_DBG_ERR_FLAG		0x11C4
866 #define B_AX_PCIE_RPQ_FULL		BIT(29)
867 #define B_AX_PCIE_RXQ_FULL		BIT(28)
868 #define B_AX_CPL_STATUS_MASK		GENMASK(27, 25)
869 #define B_AX_RX_STUCK			BIT(22)
870 #define B_AX_TX_STUCK			BIT(21)
871 #define B_AX_PCIEDBG_TXERR0		BIT(16)
872 #define B_AX_PCIE_RXP1_ERR0		BIT(4)
873 #define B_AX_PCIE_TXBD_LEN0		BIT(1)
874 #define B_AX_PCIE_TXBD_4KBOUD_LENERR	BIT(0)
875 
876 #define R_AX_TXBD_RWPTR_CLR2_V1		0x11C4
877 #define B_AX_CLR_CH11_IDX		BIT(1)
878 #define B_AX_CLR_CH10_IDX		BIT(0)
879 
880 #define R_AX_LBC_WATCHDOG		0x11D8
881 #define B_AX_LBC_TIMER			GENMASK(7, 4)
882 #define B_AX_LBC_FLAG			BIT(1)
883 #define B_AX_LBC_EN			BIT(0)
884 
885 #define R_AX_RXBD_RWPTR_CLR_V1		0x1200
886 #define B_AX_CLR_RPQ_IDX		BIT(1)
887 #define B_AX_CLR_RXQ_IDX		BIT(0)
888 
889 #define R_AX_HAXI_EXP_CTRL		0x1204
890 #define B_AX_MAX_TAG_NUM_V1_MASK	GENMASK(2, 0)
891 
892 #define R_AX_PCIE_EXP_CTRL		0x13F0
893 #define B_AX_EN_CHKDSC_NO_RX_STUCK	BIT(20)
894 #define B_AX_MAX_TAG_NUM		GENMASK(18, 16)
895 #define B_AX_SIC_EN_FORCE_CLKREQ	BIT(4)
896 
897 #define R_AX_PCIE_RX_PREF_ADV		0x13F4
898 #define B_AX_RXDMA_PREF_ADV_EN		BIT(0)
899 
900 #define R_AX_PCIE_HRPWM_V1		0x30C0
901 #define R_AX_PCIE_CRPWM			0x30C4
902 
903 #define R_AX_LBC_WATCHDOG_V1 0x30D8
904 
905 #define R_BE_PCIE_HRPWM 0x30C0
906 #define R_BE_PCIE_CRPWM 0x30C4
907 
908 #define R_BE_L1_2_CTRL_HCILDO 0x3110
909 #define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
910 
911 #define R_BE_PL1_DBG_INFO 0x3120
912 #define B_BE_END_PL1_CNT_MASK GENMASK(23, 16)
913 #define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
914 
915 #define R_BE_PCIE_MIT0_TMR 0x3330
916 #define B_BE_PCIE_MIT0_RX_TMR_MASK GENMASK(5, 4)
917 #define BE_MIT0_TMR_UNIT_1MS 0
918 #define BE_MIT0_TMR_UNIT_2MS 1
919 #define BE_MIT0_TMR_UNIT_4MS 2
920 #define BE_MIT0_TMR_UNIT_8MS 3
921 #define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
922 
923 #define R_BE_PCIE_MIT0_CNT 0x3334
924 #define B_BE_PCIE_RX_MIT0_CNT_MASK GENMASK(31, 24)
925 #define B_BE_PCIE_TX_MIT0_CNT_MASK GENMASK(23, 16)
926 #define B_BE_PCIE_RX_MIT0_TMR_CNT_MASK GENMASK(15, 8)
927 #define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
928 
929 #define R_BE_PCIE_MIT_CH_EN 0x3338
930 #define B_BE_PCIE_MIT_RX1P1_EN BIT(23)
931 #define B_BE_PCIE_MIT_RX0P1_EN BIT(22)
932 #define B_BE_PCIE_MIT_ROQ1_EN BIT(21)
933 #define B_BE_PCIE_MIT_RPQ1_EN BIT(20)
934 #define B_BE_PCIE_MIT_RX1P2_EN BIT(19)
935 #define B_BE_PCIE_MIT_ROQ0_EN BIT(18)
936 #define B_BE_PCIE_MIT_RPQ0_EN BIT(17)
937 #define B_BE_PCIE_MIT_RX0P2_EN BIT(16)
938 #define B_BE_PCIE_MIT_TXCH14_EN BIT(14)
939 #define B_BE_PCIE_MIT_TXCH13_EN BIT(13)
940 #define B_BE_PCIE_MIT_TXCH12_EN BIT(12)
941 #define B_BE_PCIE_MIT_TXCH11_EN BIT(11)
942 #define B_BE_PCIE_MIT_TXCH10_EN BIT(10)
943 #define B_BE_PCIE_MIT_TXCH9_EN BIT(9)
944 #define B_BE_PCIE_MIT_TXCH8_EN BIT(8)
945 #define B_BE_PCIE_MIT_TXCH7_EN BIT(7)
946 #define B_BE_PCIE_MIT_TXCH6_EN BIT(6)
947 #define B_BE_PCIE_MIT_TXCH5_EN BIT(5)
948 #define B_BE_PCIE_MIT_TXCH4_EN BIT(4)
949 #define B_BE_PCIE_MIT_TXCH3_EN BIT(3)
950 #define B_BE_PCIE_MIT_TXCH2_EN BIT(2)
951 #define B_BE_PCIE_MIT_TXCH1_EN BIT(1)
952 #define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
953 
954 #define R_BE_SER_PL1_CTRL 0x34A8
955 #define B_BE_PL1_SER_PL1_EN BIT(31)
956 #define B_BE_PL1_IGNORE_HOT_RST BIT(30)
957 #define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
958 #define B_BE_PL1_TIMER_CLEAR BIT(0)
959 
960 #define R_BE_REG_PL1_MASK 0x34B0
961 #define B_BE_SER_PCLKREQ_ACK_MASK BIT(5)
962 #define B_BE_SER_PM_CLK_MASK BIT(4)
963 #define B_BE_SER_LTSSM_IMR BIT(3)
964 #define B_BE_SER_PM_MASTER_IMR BIT(2)
965 #define B_BE_SER_L1SUB_IMR BIT(1)
966 #define B_BE_SER_PMU_IMR BIT(0)
967 
968 #define R_BE_REG_PL1_ISR 0x34B4
969 
970 #define R_BE_RX_APPEND_MODE 0x8920
971 #define B_BE_APPEND_OFFSET_MASK GENMASK(23, 16)
972 #define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
973 
974 #define R_BE_TXBD_RWPTR_CLR1 0xB014
975 #define B_BE_CLR_CH14_IDX BIT(14)
976 #define B_BE_CLR_CH13_IDX BIT(13)
977 #define B_BE_CLR_CH12_IDX BIT(12)
978 #define B_BE_CLR_CH11_IDX BIT(11)
979 #define B_BE_CLR_CH10_IDX BIT(10)
980 #define B_BE_CLR_CH9_IDX BIT(9)
981 #define B_BE_CLR_CH8_IDX BIT(8)
982 #define B_BE_CLR_CH7_IDX BIT(7)
983 #define B_BE_CLR_CH6_IDX BIT(6)
984 #define B_BE_CLR_CH5_IDX BIT(5)
985 #define B_BE_CLR_CH4_IDX BIT(4)
986 #define B_BE_CLR_CH3_IDX BIT(3)
987 #define B_BE_CLR_CH2_IDX BIT(2)
988 #define B_BE_CLR_CH1_IDX BIT(1)
989 #define B_BE_CLR_CH0_IDX BIT(0)
990 
991 #define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
992 #define B_BE_CLR_ROQ1_IDX_V1 BIT(5)
993 #define B_BE_CLR_RPQ1_IDX_V1 BIT(4)
994 #define B_BE_CLR_RXQ1_IDX_V1 BIT(3)
995 #define B_BE_CLR_ROQ0_IDX BIT(2)
996 #define B_BE_CLR_RPQ0_IDX BIT(1)
997 #define B_BE_CLR_RXQ0_IDX BIT(0)
998 
999 #define R_BE_HAXI_DMA_BUSY1 0xB01C
1000 #define B_BE_HAXI_MST_BUSY BIT(31)
1001 #define B_BE_HAXI_RX_IDLE BIT(25)
1002 #define B_BE_HAXI_TX_IDLE BIT(24)
1003 #define B_BE_ROQ1_BUSY_V1 BIT(21)
1004 #define B_BE_RPQ1_BUSY_V1 BIT(20)
1005 #define B_BE_RXQ1_BUSY_V1 BIT(19)
1006 #define B_BE_ROQ0_BUSY_V1 BIT(18)
1007 #define B_BE_RPQ0_BUSY_V1 BIT(17)
1008 #define B_BE_RXQ0_BUSY_V1 BIT(16)
1009 #define B_BE_WPDMA_BUSY BIT(15)
1010 #define B_BE_CH14_BUSY BIT(14)
1011 #define B_BE_CH13_BUSY BIT(13)
1012 #define B_BE_CH12_BUSY BIT(12)
1013 #define B_BE_CH11_BUSY BIT(11)
1014 #define B_BE_CH10_BUSY BIT(10)
1015 #define B_BE_CH9_BUSY BIT(9)
1016 #define B_BE_CH8_BUSY BIT(8)
1017 #define B_BE_CH7_BUSY BIT(7)
1018 #define B_BE_CH6_BUSY BIT(6)
1019 #define B_BE_CH5_BUSY BIT(5)
1020 #define B_BE_CH4_BUSY BIT(4)
1021 #define B_BE_CH3_BUSY BIT(3)
1022 #define B_BE_CH2_BUSY BIT(2)
1023 #define B_BE_CH1_BUSY BIT(1)
1024 #define B_BE_CH0_BUSY BIT(0)
1025 #define DMA_BUSY1_CHECK_BE (B_BE_CH0_BUSY | B_BE_CH1_BUSY | B_BE_CH2_BUSY | \
1026 			    B_BE_CH3_BUSY | B_BE_CH4_BUSY | B_BE_CH5_BUSY | \
1027 			    B_BE_CH6_BUSY | B_BE_CH7_BUSY | B_BE_CH8_BUSY | \
1028 			    B_BE_CH9_BUSY | B_BE_CH10_BUSY | B_BE_CH11_BUSY | \
1029 			    B_BE_CH12_BUSY | B_BE_CH13_BUSY | B_BE_CH14_BUSY)
1030 
1031 #define R_BE_HAXI_EXP_CTRL_V1 0xB020
1032 #define B_BE_R_NO_SEC_ACCESS BIT(31)
1033 #define B_BE_FORCE_EN_DMA_RX_GCLK BIT(5)
1034 #define B_BE_FORCE_EN_DMA_TX_GCLK BIT(4)
1035 #define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1036 
1037 #define RTW89_PCI_TXBD_NUM_MAX		256
1038 #define RTW89_PCI_RXBD_NUM_MAX		256
1039 #define RTW89_PCI_TXWD_NUM_MAX		512
1040 #define RTW89_PCI_TXWD_PAGE_SIZE	128
1041 #define RTW89_PCI_ADDRINFO_MAX		4
1042 #define RTW89_PCI_RX_BUF_SIZE		(11454 + 40) /* +40 for rtw89_rxdesc_long_v2 */
1043 
1044 #define RTW89_PCI_POLL_BDRAM_RST_CNT	100
1045 #define RTW89_PCI_MULTITAG		8
1046 
1047 /* PCIE CFG register */
1048 #define RTW89_PCIE_CAPABILITY_SPEED	0x7C
1049 #define RTW89_PCIE_SUPPORT_GEN_MASK	GENMASK(3, 0)
1050 #define RTW89_PCIE_L1_STS_V1		0x80
1051 #define RTW89_BCFG_LINK_SPEED_MASK	GENMASK(19, 16)
1052 #define RTW89_PCIE_GEN1_SPEED		0x01
1053 #define RTW89_PCIE_GEN2_SPEED		0x02
1054 #define RTW89_PCIE_PHY_RATE		0x82
1055 #define RTW89_PCIE_PHY_RATE_MASK	GENMASK(1, 0)
1056 #define RTW89_PCIE_LINK_CHANGE_SPEED	0xA0
1057 #define RTW89_PCIE_L1SS_STS_V1		0x0168
1058 #define RTW89_PCIE_BIT_ASPM_L11		BIT(3)
1059 #define RTW89_PCIE_BIT_ASPM_L12		BIT(2)
1060 #define RTW89_PCIE_BIT_PCI_L11		BIT(1)
1061 #define RTW89_PCIE_BIT_PCI_L12		BIT(0)
1062 #define RTW89_PCIE_ASPM_CTRL		0x070F
1063 #define RTW89_L1DLY_MASK		GENMASK(5, 3)
1064 #define RTW89_L0DLY_MASK		GENMASK(2, 0)
1065 #define RTW89_PCIE_TIMER_CTRL		0x0718
1066 #define RTW89_PCIE_BIT_L1SUB		BIT(5)
1067 #define RTW89_PCIE_L1_CTRL		0x0719
1068 #define RTW89_PCIE_BIT_EN_64BITS	BIT(5)
1069 #define RTW89_PCIE_BIT_CLK		BIT(4)
1070 #define RTW89_PCIE_BIT_L1		BIT(3)
1071 #define RTW89_PCIE_CLK_CTRL		0x0725
1072 #define RTW89_PCIE_FTS			0x080C
1073 #define RTW89_PCIE_POLLING_BIT		BIT(17)
1074 #define RTW89_PCIE_RST_MSTATE		0x0B48
1075 #define RTW89_PCIE_BIT_CFG_RST_MSTATE	BIT(0)
1076 
1077 #define INTF_INTGRA_MINREF_V1	90
1078 #define INTF_INTGRA_HOSTREF_V1	100
1079 
1080 enum rtw89_pcie_phy {
1081 	PCIE_PHY_GEN1,
1082 	PCIE_PHY_GEN2,
1083 	PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1084 };
1085 
1086 enum rtw89_pcie_l0sdly {
1087 	PCIE_L0SDLY_1US = 0,
1088 	PCIE_L0SDLY_2US = 1,
1089 	PCIE_L0SDLY_3US = 2,
1090 	PCIE_L0SDLY_4US = 3,
1091 	PCIE_L0SDLY_5US = 4,
1092 	PCIE_L0SDLY_6US = 5,
1093 	PCIE_L0SDLY_7US = 6,
1094 };
1095 
1096 enum rtw89_pcie_l1dly {
1097 	PCIE_L1DLY_16US = 4,
1098 	PCIE_L1DLY_32US = 5,
1099 	PCIE_L1DLY_64US = 6,
1100 	PCIE_L1DLY_HW_INFI = 7,
1101 };
1102 
1103 enum rtw89_pcie_clkdly_hw {
1104 	PCIE_CLKDLY_HW_0 = 0,
1105 	PCIE_CLKDLY_HW_30US = 0x1,
1106 	PCIE_CLKDLY_HW_50US = 0x2,
1107 	PCIE_CLKDLY_HW_100US = 0x3,
1108 	PCIE_CLKDLY_HW_150US = 0x4,
1109 	PCIE_CLKDLY_HW_200US = 0x5,
1110 };
1111 
1112 enum rtw89_pcie_clkdly_hw_v1 {
1113 	PCIE_CLKDLY_HW_V1_0 = 0,
1114 	PCIE_CLKDLY_HW_V1_16US = 0x1,
1115 	PCIE_CLKDLY_HW_V1_32US = 0x2,
1116 	PCIE_CLKDLY_HW_V1_64US = 0x3,
1117 	PCIE_CLKDLY_HW_V1_80US = 0x4,
1118 	PCIE_CLKDLY_HW_V1_96US = 0x5,
1119 };
1120 
1121 enum mac_ax_bd_trunc_mode {
1122 	MAC_AX_BD_NORM,
1123 	MAC_AX_BD_TRUNC,
1124 	MAC_AX_BD_DEF = 0xFE
1125 };
1126 
1127 enum mac_ax_rxbd_mode {
1128 	MAC_AX_RXBD_PKT,
1129 	MAC_AX_RXBD_SEP,
1130 	MAC_AX_RXBD_DEF = 0xFE
1131 };
1132 
1133 enum mac_ax_tag_mode {
1134 	MAC_AX_TAG_SGL,
1135 	MAC_AX_TAG_MULTI,
1136 	MAC_AX_TAG_DEF = 0xFE
1137 };
1138 
1139 enum mac_ax_tx_burst {
1140 	MAC_AX_TX_BURST_16B = 0,
1141 	MAC_AX_TX_BURST_32B = 1,
1142 	MAC_AX_TX_BURST_64B = 2,
1143 	MAC_AX_TX_BURST_V1_64B = 0,
1144 	MAC_AX_TX_BURST_128B = 3,
1145 	MAC_AX_TX_BURST_V1_128B = 1,
1146 	MAC_AX_TX_BURST_256B = 4,
1147 	MAC_AX_TX_BURST_V1_256B = 2,
1148 	MAC_AX_TX_BURST_512B = 5,
1149 	MAC_AX_TX_BURST_1024B = 6,
1150 	MAC_AX_TX_BURST_2048B = 7,
1151 	MAC_AX_TX_BURST_DEF = 0xFE
1152 };
1153 
1154 enum mac_ax_rx_burst {
1155 	MAC_AX_RX_BURST_16B = 0,
1156 	MAC_AX_RX_BURST_32B = 1,
1157 	MAC_AX_RX_BURST_64B = 2,
1158 	MAC_AX_RX_BURST_V1_64B = 0,
1159 	MAC_AX_RX_BURST_128B = 3,
1160 	MAC_AX_RX_BURST_V1_128B = 1,
1161 	MAC_AX_RX_BURST_V1_256B = 0,
1162 	MAC_AX_RX_BURST_DEF = 0xFE
1163 };
1164 
1165 enum mac_ax_wd_dma_intvl {
1166 	MAC_AX_WD_DMA_INTVL_0S,
1167 	MAC_AX_WD_DMA_INTVL_256NS,
1168 	MAC_AX_WD_DMA_INTVL_512NS,
1169 	MAC_AX_WD_DMA_INTVL_768NS,
1170 	MAC_AX_WD_DMA_INTVL_1US,
1171 	MAC_AX_WD_DMA_INTVL_1_5US,
1172 	MAC_AX_WD_DMA_INTVL_2US,
1173 	MAC_AX_WD_DMA_INTVL_4US,
1174 	MAC_AX_WD_DMA_INTVL_8US,
1175 	MAC_AX_WD_DMA_INTVL_16US,
1176 	MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1177 };
1178 
1179 enum mac_ax_multi_tag_num {
1180 	MAC_AX_TAG_NUM_1,
1181 	MAC_AX_TAG_NUM_2,
1182 	MAC_AX_TAG_NUM_3,
1183 	MAC_AX_TAG_NUM_4,
1184 	MAC_AX_TAG_NUM_5,
1185 	MAC_AX_TAG_NUM_6,
1186 	MAC_AX_TAG_NUM_7,
1187 	MAC_AX_TAG_NUM_8,
1188 	MAC_AX_TAG_NUM_DEF = 0xFE
1189 };
1190 
1191 enum mac_ax_lbc_tmr {
1192 	MAC_AX_LBC_TMR_8US = 0,
1193 	MAC_AX_LBC_TMR_16US,
1194 	MAC_AX_LBC_TMR_32US,
1195 	MAC_AX_LBC_TMR_64US,
1196 	MAC_AX_LBC_TMR_128US,
1197 	MAC_AX_LBC_TMR_256US,
1198 	MAC_AX_LBC_TMR_512US,
1199 	MAC_AX_LBC_TMR_1MS,
1200 	MAC_AX_LBC_TMR_2MS,
1201 	MAC_AX_LBC_TMR_4MS,
1202 	MAC_AX_LBC_TMR_8MS,
1203 	MAC_AX_LBC_TMR_DEF = 0xFE
1204 };
1205 
1206 enum mac_ax_pcie_func_ctrl {
1207 	MAC_AX_PCIE_DISABLE = 0,
1208 	MAC_AX_PCIE_ENABLE = 1,
1209 	MAC_AX_PCIE_DEFAULT = 0xFE,
1210 	MAC_AX_PCIE_IGNORE = 0xFF
1211 };
1212 
1213 enum mac_ax_io_rcy_tmr {
1214 	MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
1215 	MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
1216 	MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
1217 	MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1218 };
1219 
1220 enum rtw89_pci_intr_mask_cfg {
1221 	RTW89_PCI_INTR_MASK_RESET,
1222 	RTW89_PCI_INTR_MASK_NORMAL,
1223 	RTW89_PCI_INTR_MASK_LOW_POWER,
1224 	RTW89_PCI_INTR_MASK_RECOVERY_START,
1225 	RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
1226 };
1227 
1228 struct rtw89_pci_isrs;
1229 struct rtw89_pci;
1230 
1231 struct rtw89_pci_bd_idx_addr {
1232 	u32 tx_bd_addrs[RTW89_TXCH_NUM];
1233 	u32 rx_bd_addrs[RTW89_RXCH_NUM];
1234 };
1235 
1236 struct rtw89_pci_ch_dma_addr {
1237 	u32 num;
1238 	u32 idx;
1239 	u32 bdram;
1240 	u32 desa_l;
1241 	u32 desa_h;
1242 };
1243 
1244 struct rtw89_pci_ch_dma_addr_set {
1245 	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
1246 	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
1247 };
1248 
1249 struct rtw89_pci_bd_ram {
1250 	u8 start_idx;
1251 	u8 max_num;
1252 	u8 min_num;
1253 };
1254 
1255 struct rtw89_pci_gen_def {
1256 	u32 isr_rdu;
1257 	u32 isr_halt_c2h;
1258 	u32 isr_wdt_timeout;
1259 	struct rtw89_reg2_def isr_clear_rpq;
1260 	struct rtw89_reg2_def isr_clear_rxq;
1261 
1262 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
1263 	int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
1264 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
1265 
1266 	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
1267 	int (*rst_bdram)(struct rtw89_dev *rtwdev);
1268 
1269 	int (*lv1rst_stop_dma)(struct rtw89_dev *rtwdev);
1270 	int (*lv1rst_start_dma)(struct rtw89_dev *rtwdev);
1271 
1272 	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
1273 	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
1274 	int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
1275 
1276 	void (*aspm_set)(struct rtw89_dev *rtwdev, bool enable);
1277 	void (*clkreq_set)(struct rtw89_dev *rtwdev, bool enable);
1278 	void (*l1ss_set)(struct rtw89_dev *rtwdev, bool enable);
1279 };
1280 
1281 struct rtw89_pci_info {
1282 	const struct rtw89_pci_gen_def *gen_def;
1283 	enum mac_ax_bd_trunc_mode txbd_trunc_mode;
1284 	enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
1285 	enum mac_ax_rxbd_mode rxbd_mode;
1286 	enum mac_ax_tag_mode tag_mode;
1287 	enum mac_ax_tx_burst tx_burst;
1288 	enum mac_ax_rx_burst rx_burst;
1289 	enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
1290 	enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
1291 	enum mac_ax_multi_tag_num multi_tag_num;
1292 	enum mac_ax_pcie_func_ctrl lbc_en;
1293 	enum mac_ax_lbc_tmr lbc_tmr;
1294 	enum mac_ax_pcie_func_ctrl autok_en;
1295 	enum mac_ax_pcie_func_ctrl io_rcy_en;
1296 	enum mac_ax_io_rcy_tmr io_rcy_tmr;
1297 	bool rx_ring_eq_is_full;
1298 	bool check_rx_tag;
1299 
1300 	u32 init_cfg_reg;
1301 	u32 txhci_en_bit;
1302 	u32 rxhci_en_bit;
1303 	u32 rxbd_mode_bit;
1304 	u32 exp_ctrl_reg;
1305 	u32 max_tag_num_mask;
1306 	u32 rxbd_rwptr_clr_reg;
1307 	u32 txbd_rwptr_clr2_reg;
1308 	struct rtw89_reg_def dma_io_stop;
1309 	struct rtw89_reg_def dma_stop1;
1310 	struct rtw89_reg_def dma_stop2;
1311 	struct rtw89_reg_def dma_busy1;
1312 	u32 dma_busy2_reg;
1313 	u32 dma_busy3_reg;
1314 
1315 	u32 rpwm_addr;
1316 	u32 cpwm_addr;
1317 	u32 mit_addr;
1318 	u32 wp_sel_addr;
1319 	u32 tx_dma_ch_mask;
1320 	const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
1321 	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
1322 	const struct rtw89_pci_bd_ram (*bd_ram_table)[RTW89_TXCH_NUM];
1323 
1324 	int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
1325 	u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
1326 				void *txaddr_info_addr, u32 total_len,
1327 				dma_addr_t dma, u8 *add_info_nr);
1328 	void (*config_intr_mask)(struct rtw89_dev *rtwdev);
1329 	void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1330 	void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1331 	void (*recognize_intrs)(struct rtw89_dev *rtwdev,
1332 				struct rtw89_pci *rtwpci,
1333 				struct rtw89_pci_isrs *isrs);
1334 };
1335 
1336 struct rtw89_pci_tx_data {
1337 	dma_addr_t dma;
1338 };
1339 
1340 struct rtw89_pci_rx_info {
1341 	dma_addr_t dma;
1342 	u32 fs:1, ls:1, tag:13, len:14;
1343 };
1344 
1345 struct rtw89_pci_tx_bd_32 {
1346 	__le16 length;
1347 	__le16 opt;
1348 #define RTW89_PCI_TXBD_OPT_LS		BIT(14)
1349 #define RTW89_PCI_TXBD_OPT_DMA_HI	GENMASK(13, 6)
1350 	__le32 dma;
1351 } __packed;
1352 
1353 #define RTW89_PCI_TXWP_VALID		BIT(15)
1354 
1355 struct rtw89_pci_tx_wp_info {
1356 	__le16 seq0;
1357 	__le16 seq1;
1358 	__le16 seq2;
1359 	__le16 seq3;
1360 } __packed;
1361 
1362 #define RTW89_PCI_ADDR_MSDU_LS		BIT(15)
1363 #define RTW89_PCI_ADDR_LS		BIT(14)
1364 #define RTW89_PCI_ADDR_HIGH_MASK	GENMASK(13, 6)
1365 #define RTW89_PCI_ADDR_NUM(x)		((x) & GENMASK(5, 0))
1366 
1367 struct rtw89_pci_tx_addr_info_32 {
1368 	__le16 length;
1369 	__le16 option;
1370 	__le32 dma;
1371 } __packed;
1372 
1373 #define RTW89_TXADDR_INFO_NR_V1		10
1374 
1375 struct rtw89_pci_tx_addr_info_32_v1 {
1376 	__le16 length_opt;
1377 #define B_PCIADDR_LEN_V1_MASK		GENMASK(10, 0)
1378 #define B_PCIADDR_HIGH_SEL_V1_MASK	GENMASK(14, 11)
1379 #define B_PCIADDR_LS_V1_MASK		BIT(15)
1380 #define TXADDR_INFO_LENTHG_V1_MAX	ALIGN_DOWN(BIT(11) - 1, 4)
1381 	__le16 dma_low_lsb;
1382 	__le16 dma_low_msb;
1383 } __packed;
1384 
1385 #define RTW89_PCI_RPP_POLLUTED		BIT(31)
1386 #define RTW89_PCI_RPP_SEQ		GENMASK(30, 16)
1387 #define RTW89_PCI_RPP_TX_STATUS		GENMASK(15, 13)
1388 #define RTW89_TX_DONE			0x0
1389 #define RTW89_TX_RETRY_LIMIT		0x1
1390 #define RTW89_TX_LIFE_TIME		0x2
1391 #define RTW89_TX_MACID_DROP		0x3
1392 #define RTW89_PCI_RPP_QSEL		GENMASK(12, 8)
1393 #define RTW89_PCI_RPP_MACID		GENMASK(7, 0)
1394 
1395 struct rtw89_pci_rpp_fmt {
1396 	__le32 dword;
1397 } __packed;
1398 
1399 struct rtw89_pci_rx_bd_32 {
1400 	__le16 buf_size;
1401 	__le16 opt;
1402 #define RTW89_PCI_RXBD_OPT_DMA_HI	GENMASK(13, 6)
1403 	__le32 dma;
1404 } __packed;
1405 
1406 #define RTW89_PCI_RXBD_FS		BIT(15)
1407 #define RTW89_PCI_RXBD_LS		BIT(14)
1408 #define RTW89_PCI_RXBD_WRITE_SIZE	GENMASK(13, 0)
1409 #define RTW89_PCI_RXBD_TAG		GENMASK(28, 16)
1410 
1411 struct rtw89_pci_rxbd_info {
1412 	__le32 dword;
1413 };
1414 
1415 struct rtw89_pci_tx_wd {
1416 	struct list_head list;
1417 	struct sk_buff_head queue;
1418 
1419 	void *vaddr;
1420 	dma_addr_t paddr;
1421 	u32 len;
1422 	u32 seq;
1423 };
1424 
1425 struct rtw89_pci_dma_ring {
1426 	void *head;
1427 	u8 desc_size;
1428 	dma_addr_t dma;
1429 
1430 	struct rtw89_pci_ch_dma_addr addr;
1431 
1432 	u32 len;
1433 	u32 wp; /* host idx */
1434 	u32 rp; /* hw idx */
1435 };
1436 
1437 struct rtw89_pci_tx_wd_ring {
1438 	void *head;
1439 	dma_addr_t dma;
1440 
1441 	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
1442 	struct list_head free_pages;
1443 
1444 	u32 page_size;
1445 	u32 page_num;
1446 	u32 curr_num;
1447 };
1448 
1449 #define RTW89_RX_TAG_MAX		0x1fff
1450 
1451 struct rtw89_pci_tx_ring {
1452 	struct rtw89_pci_tx_wd_ring wd_ring;
1453 	struct rtw89_pci_dma_ring bd_ring;
1454 	struct list_head busy_pages;
1455 	u8 txch;
1456 	bool dma_enabled;
1457 	u16 tag; /* range from 0x0001 ~ 0x1fff */
1458 
1459 	u64 tx_cnt;
1460 	u64 tx_acked;
1461 	u64 tx_retry_lmt;
1462 	u64 tx_life_time;
1463 	u64 tx_mac_id_drop;
1464 };
1465 
1466 struct rtw89_pci_rx_ring {
1467 	struct rtw89_pci_dma_ring bd_ring;
1468 	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
1469 	u32 buf_sz;
1470 	struct sk_buff *diliver_skb;
1471 	struct rtw89_rx_desc_info diliver_desc;
1472 	u32 target_rx_tag:13;
1473 };
1474 
1475 struct rtw89_pci_isrs {
1476 	u32 ind_isrs;
1477 	u32 halt_c2h_isrs;
1478 	u32 isrs[2];
1479 };
1480 
1481 struct rtw89_pci {
1482 	struct pci_dev *pdev;
1483 
1484 	/* protect HW irq related registers */
1485 	spinlock_t irq_lock;
1486 	/* protect TRX resources (exclude RXQ) */
1487 	spinlock_t trx_lock;
1488 	bool running;
1489 	bool low_power;
1490 	bool under_recovery;
1491 	bool enable_dac;
1492 	struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
1493 	struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
1494 	struct sk_buff_head h2c_queue;
1495 	struct sk_buff_head h2c_release_queue;
1496 	DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
1497 
1498 	u32 ind_intrs;
1499 	u32 halt_c2h_intrs;
1500 	u32 intrs[2];
1501 	void __iomem *mmap;
1502 };
1503 
RTW89_PCI_RX_SKB_CB(struct sk_buff * skb)1504 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
1505 {
1506 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1507 
1508 	BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) >
1509 		     sizeof(info->status.status_driver_data));
1510 
1511 	return (struct rtw89_pci_rx_info *)skb->cb;
1512 }
1513 
1514 static inline struct rtw89_pci_rx_bd_32 *
RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring * rx_ring,u32 idx)1515 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
1516 {
1517 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1518 	u8 *head = bd_ring->head;
1519 	u32 desc_size = bd_ring->desc_size;
1520 	u32 offset = idx * desc_size;
1521 
1522 	return (struct rtw89_pci_rx_bd_32 *)(head + offset);
1523 }
1524 
1525 static inline void
rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring * rx_ring,u32 cnt)1526 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
1527 {
1528 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
1529 
1530 	bd_ring->wp += cnt;
1531 
1532 	if (bd_ring->wp >= bd_ring->len)
1533 		bd_ring->wp -= bd_ring->len;
1534 }
1535 
RTW89_PCI_TX_SKB_CB(struct sk_buff * skb)1536 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
1537 {
1538 	struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb);
1539 
1540 	return (struct rtw89_pci_tx_data *)data->hci_priv;
1541 }
1542 
1543 static inline struct rtw89_pci_tx_bd_32 *
rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring * tx_ring)1544 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1545 {
1546 	struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1547 	struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1548 
1549 	head = bd_ring->head;
1550 	tx_bd = head + bd_ring->wp;
1551 
1552 	return tx_bd;
1553 }
1554 
1555 static inline struct rtw89_pci_tx_wd *
rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring * tx_ring)1556 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1557 {
1558 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1559 	struct rtw89_pci_tx_wd *txwd;
1560 
1561 	txwd = list_first_entry_or_null(&wd_ring->free_pages,
1562 					struct rtw89_pci_tx_wd, list);
1563 	if (!txwd)
1564 		return NULL;
1565 
1566 	list_del_init(&txwd->list);
1567 	txwd->len = 0;
1568 	wd_ring->curr_num--;
1569 
1570 	return txwd;
1571 }
1572 
1573 static inline void
rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring * tx_ring,struct rtw89_pci_tx_wd * txwd)1574 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1575 		       struct rtw89_pci_tx_wd *txwd)
1576 {
1577 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1578 
1579 	memset(txwd->vaddr, 0, wd_ring->page_size);
1580 	list_add_tail(&txwd->list, &wd_ring->free_pages);
1581 	wd_ring->curr_num++;
1582 }
1583 
rtw89_pci_ltr_is_err_reg_val(u32 val)1584 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1585 {
1586 	return val == 0xffffffff || val == 0xeaeaeaea;
1587 }
1588 
1589 extern const struct dev_pm_ops rtw89_pm_ops;
1590 extern const struct dev_pm_ops rtw89_pm_ops_be;
1591 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1592 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1593 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be;
1594 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM];
1595 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM];
1596 extern const struct rtw89_pci_gen_def rtw89_pci_gen_ax;
1597 extern const struct rtw89_pci_gen_def rtw89_pci_gen_be;
1598 
1599 struct pci_device_id;
1600 
1601 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1602 void rtw89_pci_remove(struct pci_dev *pdev);
1603 void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev);
1604 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1605 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1606 int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en);
1607 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1608 			       void *txaddr_info_addr, u32 total_len,
1609 			       dma_addr_t dma, u8 *add_info_nr);
1610 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1611 				  void *txaddr_info_addr, u32 total_len,
1612 				  dma_addr_t dma, u8 *add_info_nr);
1613 void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
1614 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1615 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1616 void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev);
1617 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1618 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1619 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1620 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1621 void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1622 void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1623 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1624 			       struct rtw89_pci *rtwpci,
1625 			       struct rtw89_pci_isrs *isrs);
1626 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1627 				  struct rtw89_pci *rtwpci,
1628 				  struct rtw89_pci_isrs *isrs);
1629 void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
1630 				  struct rtw89_pci *rtwpci,
1631 				  struct rtw89_pci_isrs *isrs);
1632 
1633 static inline
rtw89_chip_fill_txaddr_info(struct rtw89_dev * rtwdev,void * txaddr_info_addr,u32 total_len,dma_addr_t dma,u8 * add_info_nr)1634 u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1635 				void *txaddr_info_addr, u32 total_len,
1636 				dma_addr_t dma, u8 *add_info_nr)
1637 {
1638 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1639 
1640 	return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1641 				      dma, add_info_nr);
1642 }
1643 
rtw89_chip_config_intr_mask(struct rtw89_dev * rtwdev,enum rtw89_pci_intr_mask_cfg cfg)1644 static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1645 					       enum rtw89_pci_intr_mask_cfg cfg)
1646 {
1647 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1648 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1649 
1650 	switch (cfg) {
1651 	default:
1652 	case RTW89_PCI_INTR_MASK_RESET:
1653 		rtwpci->low_power = false;
1654 		rtwpci->under_recovery = false;
1655 		break;
1656 	case RTW89_PCI_INTR_MASK_NORMAL:
1657 		rtwpci->low_power = false;
1658 		break;
1659 	case RTW89_PCI_INTR_MASK_LOW_POWER:
1660 		rtwpci->low_power = true;
1661 		break;
1662 	case RTW89_PCI_INTR_MASK_RECOVERY_START:
1663 		rtwpci->under_recovery = true;
1664 		break;
1665 	case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1666 		rtwpci->under_recovery = false;
1667 		break;
1668 	}
1669 
1670 	rtw89_debug(rtwdev, RTW89_DBG_HCI,
1671 		    "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1672 		    rtwpci->low_power, rtwpci->under_recovery);
1673 
1674 	info->config_intr_mask(rtwdev);
1675 }
1676 
1677 static inline
rtw89_chip_enable_intr(struct rtw89_dev * rtwdev,struct rtw89_pci * rtwpci)1678 void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1679 {
1680 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1681 
1682 	info->enable_intr(rtwdev, rtwpci);
1683 }
1684 
1685 static inline
rtw89_chip_disable_intr(struct rtw89_dev * rtwdev,struct rtw89_pci * rtwpci)1686 void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1687 {
1688 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1689 
1690 	info->disable_intr(rtwdev, rtwpci);
1691 }
1692 
1693 static inline
rtw89_chip_recognize_intrs(struct rtw89_dev * rtwdev,struct rtw89_pci * rtwpci,struct rtw89_pci_isrs * isrs)1694 void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1695 				struct rtw89_pci *rtwpci,
1696 				struct rtw89_pci_isrs *isrs)
1697 {
1698 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1699 
1700 	info->recognize_intrs(rtwdev, rtwpci, isrs);
1701 }
1702 
rtw89_pci_ops_mac_pre_init(struct rtw89_dev * rtwdev)1703 static inline int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
1704 {
1705 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1706 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1707 
1708 	return gen_def->mac_pre_init(rtwdev);
1709 }
1710 
rtw89_pci_ops_mac_pre_deinit(struct rtw89_dev * rtwdev)1711 static inline int rtw89_pci_ops_mac_pre_deinit(struct rtw89_dev *rtwdev)
1712 {
1713 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1714 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1715 
1716 	if (!gen_def->mac_pre_deinit)
1717 		return 0;
1718 
1719 	return gen_def->mac_pre_deinit(rtwdev);
1720 }
1721 
rtw89_pci_ops_mac_post_init(struct rtw89_dev * rtwdev)1722 static inline int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev)
1723 {
1724 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1725 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1726 
1727 	return gen_def->mac_post_init(rtwdev);
1728 }
1729 
rtw89_pci_clr_idx_all(struct rtw89_dev * rtwdev)1730 static inline void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev)
1731 {
1732 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1733 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1734 
1735 	gen_def->clr_idx_all(rtwdev);
1736 }
1737 
rtw89_pci_reset_bdram(struct rtw89_dev * rtwdev)1738 static inline int rtw89_pci_reset_bdram(struct rtw89_dev *rtwdev)
1739 {
1740 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1741 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1742 
1743 	return gen_def->rst_bdram(rtwdev);
1744 }
1745 
rtw89_pci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)1746 static inline void rtw89_pci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
1747 {
1748 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1749 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1750 
1751 	return gen_def->ctrl_txdma_ch(rtwdev, enable);
1752 }
1753 
rtw89_pci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)1754 static inline void rtw89_pci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
1755 {
1756 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1757 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1758 
1759 	return gen_def->ctrl_txdma_fw_ch(rtwdev, enable);
1760 }
1761 
rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)1762 static inline int rtw89_pci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
1763 {
1764 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1765 	const struct rtw89_pci_gen_def *gen_def = info->gen_def;
1766 
1767 	return gen_def->poll_txdma_ch_idle(rtwdev);
1768 }
1769 #endif
1770