xref: /linux/include/linux/mfd/rz-mtu3.h (revision 03c11eb3b16dc0058589751dfd91f254be2be613)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2022 Renesas Electronics Corporation
4  */
5 #ifndef __MFD_RZ_MTU3_H__
6 #define __MFD_RZ_MTU3_H__
7 
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/mutex.h>
11 
12 /* 8-bit shared register offsets macros */
13 #define RZ_MTU3_TSTRA	0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB	0x880 /* Timer start register B */
15 
16 /* 16-bit shared register offset macros */
17 #define RZ_MTU3_TDDRA	0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB	0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA	0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB	0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA	0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB	0x822 /* Timer cycle buffer register B */
23 #define RZ_MTU3_TCNTSA	0x020 /* Timer subcounter A */
24 #define RZ_MTU3_TCNTSB	0x820 /* Timer subcounter B */
25 
26 /*
27  * MTU5 contains 3 timer counter registers and is totaly different
28  * from other channels, so we must separate its offset
29  */
30 
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
32 #define RZ_MTU3_TIER	0 /* Timer interrupt register */
33 #define RZ_MTU3_NFCR	1 /* Noise filter control register */
34 #define RZ_MTU3_TSR	2 /* Timer status register */
35 #define RZ_MTU3_TCR	3 /* Timer control register */
36 #define RZ_MTU3_TCR2	4 /* Timer control register 2 */
37 
38 /* Timer mode register 1 */
39 #define RZ_MTU3_TMDR1	5
40 #define RZ_MTU3_TMDR1_MD		GENMASK(3, 0)
41 #define RZ_MTU3_TMDR1_MD_NORMAL		FIELD_PREP(RZ_MTU3_TMDR1_MD, 0)
42 #define RZ_MTU3_TMDR1_MD_PWMMODE1	FIELD_PREP(RZ_MTU3_TMDR1_MD, 2)
43 
44 #define RZ_MTU3_TIOR	6 /* Timer I/O control register */
45 #define RZ_MTU3_TIORH	6 /* Timer I/O control register H */
46 #define RZ_MTU3_TIORL	7 /* Timer I/O control register L */
47 /* Only MTU3/4/6/7 have TBTM registers */
48 #define RZ_MTU3_TBTM	8 /* Timer buffer operation transfer mode register */
49 
50 /* 8-bit MTU5 register offset macros */
51 #define RZ_MTU3_TSTR		2 /* MTU5 Timer start register */
52 #define RZ_MTU3_TCNTCMPCLR	3 /* MTU5 Timer compare match clear register */
53 #define RZ_MTU3_TCRU		4 /* Timer control register U */
54 #define RZ_MTU3_TCR2U		5 /* Timer control register 2U */
55 #define RZ_MTU3_TIORU		6 /* Timer I/O control register U */
56 #define RZ_MTU3_TCRV		7 /* Timer control register V */
57 #define RZ_MTU3_TCR2V		8 /* Timer control register 2V */
58 #define RZ_MTU3_TIORV		9 /* Timer I/O control register V */
59 #define RZ_MTU3_TCRW		10 /* Timer control register W */
60 #define RZ_MTU3_TCR2W		11 /* Timer control register 2W */
61 #define RZ_MTU3_TIORW		12 /* Timer I/O control register W */
62 
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
64 #define RZ_MTU3_TCNT		0 /* Timer counter */
65 #define RZ_MTU3_TGRA		1 /* Timer general register A */
66 #define RZ_MTU3_TGRB		2 /* Timer general register B */
67 #define RZ_MTU3_TGRC		3 /* Timer general register C */
68 #define RZ_MTU3_TGRD		4 /* Timer general register D */
69 #define RZ_MTU3_TGRE		5 /* Timer general register E */
70 #define RZ_MTU3_TGRF		6 /* Timer general register F */
71 /* Timer A/D converter start request registers */
72 #define RZ_MTU3_TADCR		7 /* control register */
73 #define RZ_MTU3_TADCORA		8 /* cycle set register A */
74 #define RZ_MTU3_TADCORB		9 /* cycle set register B */
75 #define RZ_MTU3_TADCOBRA	10 /* cycle set buffer register A */
76 #define RZ_MTU3_TADCOBRB	11 /* cycle set buffer register B */
77 
78 /* 16-bit MTU5 register offset macros */
79 #define RZ_MTU3_TCNTU		0 /* MTU5 Timer counter U */
80 #define RZ_MTU3_TGRU		1 /* MTU5 Timer general register U */
81 #define RZ_MTU3_TCNTV		2 /* MTU5 Timer counter V */
82 #define RZ_MTU3_TGRV		3 /* MTU5 Timer general register V */
83 #define RZ_MTU3_TCNTW		4 /* MTU5 Timer counter W */
84 #define RZ_MTU3_TGRW		5 /* MTU5 Timer general register W */
85 
86 /* 32-bit register offset */
87 #define RZ_MTU3_TCNTLW		0 /* Timer longword counter */
88 #define RZ_MTU3_TGRALW		1 /* Timer longword general register A */
89 #define RZ_MTU3_TGRBLW		2 /* Timer longowrd general register B */
90 
91 #define RZ_MTU3_TMDR3		0x191 /* MTU1 Timer Mode Register 3 */
92 
93 /* Macros for setting registers */
94 #define RZ_MTU3_TCR_CCLR	GENMASK(7, 5)
95 #define RZ_MTU3_TCR_CKEG	GENMASK(4, 3)
96 #define RZ_MTU3_TCR_TPCS	GENMASK(2, 0)
97 #define RZ_MTU3_TCR_CCLR_TGRA	BIT(5)
98 #define RZ_MTU3_TCR_CCLR_TGRC	FIELD_PREP(RZ_MTU3_TCR_CCLR, 5)
99 #define RZ_MTU3_TCR_CKEG_RISING	FIELD_PREP(RZ_MTU3_TCR_CKEG, 0)
100 
101 #define RZ_MTU3_TIOR_IOB			GENMASK(7, 4)
102 #define RZ_MTU3_TIOR_IOA			GENMASK(3, 0)
103 #define RZ_MTU3_TIOR_OC_RETAIN			0
104 #define RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT	2
105 #define RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT	7
106 
107 #define RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH \
108 	FIELD_PREP(RZ_MTU3_TIOR_IOA, RZ_MTU3_TIOR_OC_INIT_OUT_LO_HI_OUT)
109 #define RZ_MTU3_TIOR_OC_IOB_TOGGLE \
110 	FIELD_PREP(RZ_MTU3_TIOR_IOB, RZ_MTU3_TIOR_OC_INIT_OUT_HI_TOGGLE_OUT)
111 
112 enum rz_mtu3_channels {
113 	RZ_MTU3_CHAN_0,
114 	RZ_MTU3_CHAN_1,
115 	RZ_MTU3_CHAN_2,
116 	RZ_MTU3_CHAN_3,
117 	RZ_MTU3_CHAN_4,
118 	RZ_MTU3_CHAN_5,
119 	RZ_MTU3_CHAN_6,
120 	RZ_MTU3_CHAN_7,
121 	RZ_MTU3_CHAN_8,
122 	RZ_MTU_NUM_CHANNELS
123 };
124 
125 /**
126  * struct rz_mtu3_channel - MTU3 channel private data
127  *
128  * @dev: device handle
129  * @channel_number: channel number
130  * @lock: Lock to protect channel state
131  * @is_busy: channel state
132  */
133 struct rz_mtu3_channel {
134 	struct device *dev;
135 	unsigned int channel_number;
136 	struct mutex lock;
137 	bool is_busy;
138 };
139 
140 /**
141  * struct rz_mtu3 - MTU3 core private data
142  *
143  * @clk: MTU3 module clock
144  * @rz_mtu3_channel: HW channels
145  * @priv_data: MTU3 core driver private data
146  */
147 struct rz_mtu3 {
148 	struct clk *clk;
149 	struct rz_mtu3_channel channels[RZ_MTU_NUM_CHANNELS];
150 
151 	void *priv_data;
152 };
153 
rz_mtu3_request_channel(struct rz_mtu3_channel * ch)154 static inline bool rz_mtu3_request_channel(struct rz_mtu3_channel *ch)
155 {
156 	mutex_lock(&ch->lock);
157 	if (ch->is_busy) {
158 		mutex_unlock(&ch->lock);
159 		return false;
160 	}
161 
162 	ch->is_busy = true;
163 	mutex_unlock(&ch->lock);
164 
165 	return true;
166 }
167 
rz_mtu3_release_channel(struct rz_mtu3_channel * ch)168 static inline void rz_mtu3_release_channel(struct rz_mtu3_channel *ch)
169 {
170 	mutex_lock(&ch->lock);
171 	ch->is_busy = false;
172 	mutex_unlock(&ch->lock);
173 }
174 
175 bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch);
176 void rz_mtu3_disable(struct rz_mtu3_channel *ch);
177 int rz_mtu3_enable(struct rz_mtu3_channel *ch);
178 
179 u8 rz_mtu3_8bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
180 u16 rz_mtu3_16bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
181 u32 rz_mtu3_32bit_ch_read(struct rz_mtu3_channel *ch, u16 off);
182 u16 rz_mtu3_shared_reg_read(struct rz_mtu3_channel *ch, u16 off);
183 
184 void rz_mtu3_8bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u8 val);
185 void rz_mtu3_16bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
186 void rz_mtu3_32bit_ch_write(struct rz_mtu3_channel *ch, u16 off, u32 val);
187 void rz_mtu3_shared_reg_write(struct rz_mtu3_channel *ch, u16 off, u16 val);
188 void rz_mtu3_shared_reg_update_bit(struct rz_mtu3_channel *ch, u16 off,
189 				   u16 pos, u8 val);
190 
191 #endif /* __MFD_RZ_MTU3_H__ */
192