1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * RZ/G2L Display Unit DRM driver 4 * 5 * Copyright (C) 2023 Renesas Electronics Corporation 6 * 7 * Based on rcar_du_drv.h 8 */ 9 10 #ifndef __RZG2L_DU_DRV_H__ 11 #define __RZG2L_DU_DRV_H__ 12 13 #include <linux/kernel.h> 14 15 #include <drm/drm_device.h> 16 17 #include "rzg2l_du_crtc.h" 18 #include "rzg2l_du_vsp.h" 19 20 struct device; 21 struct drm_property; 22 23 enum rzg2l_du_output { 24 RZG2L_DU_OUTPUT_DSI0, 25 RZG2L_DU_OUTPUT_DPAD0, 26 RZG2L_DU_OUTPUT_MAX, 27 }; 28 29 /* 30 * struct rzg2l_du_output_routing - Output routing specification 31 * @possible_outputs: bitmask of possible outputs 32 * @port: device tree port number corresponding to this output route 33 * 34 * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data 35 * specify the valid SoC outputs, which CRTC can drive the output, and the type 36 * of in-SoC encoder for the output. 37 */ 38 struct rzg2l_du_output_routing { 39 unsigned int possible_outputs; 40 unsigned int port; 41 }; 42 43 /* 44 * struct rzg2l_du_device_info - DU model-specific information 45 * @channels_mask: bit mask of available DU channels 46 * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*) 47 */ 48 struct rzg2l_du_device_info { 49 unsigned int channels_mask; 50 struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; 51 }; 52 53 #define RZG2L_DU_MAX_CRTCS 1 54 #define RZG2L_DU_MAX_VSPS 1 55 #define RZG2L_DU_MAX_DSI 1 56 57 struct rzg2l_du_device { 58 struct device *dev; 59 const struct rzg2l_du_device_info *info; 60 61 void __iomem *mmio; 62 63 struct drm_device ddev; 64 65 struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS]; 66 unsigned int num_crtcs; 67 68 struct rzg2l_du_vsp vsps[RZG2L_DU_MAX_VSPS]; 69 }; 70 to_rzg2l_du_device(struct drm_device * dev)71static inline struct rzg2l_du_device *to_rzg2l_du_device(struct drm_device *dev) 72 { 73 return container_of(dev, struct rzg2l_du_device, ddev); 74 } 75 76 const char *rzg2l_du_output_name(enum rzg2l_du_output output); 77 78 #endif /* __RZG2L_DU_DRV_H__ */ 79