1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #ifndef BNXT_H
12 #define BNXT_H
13
14 #define DRV_MODULE_NAME "bnxt_en"
15
16 /* DO NOT CHANGE DRV_VER_* defines
17 * FIXME: Delete them
18 */
19 #define DRV_VER_MAJ 1
20 #define DRV_VER_MIN 10
21 #define DRV_VER_UPD 3
22
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <linux/auxiliary_bus.h>
28 #include <net/devlink.h>
29 #include <net/dst_metadata.h>
30 #include <net/xdp.h>
31 #include <linux/dim.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #ifdef CONFIG_TEE_BNXT_FW
34 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
35 #endif
36
37 #define BNXT_DEFAULT_RX_COPYBREAK 256
38 #define BNXT_MAX_RX_COPYBREAK 1024
39
40 extern struct list_head bnxt_block_cb_list;
41
42 struct page_pool;
43
44 struct tx_bd {
45 __le32 tx_bd_len_flags_type;
46 #define TX_BD_TYPE (0x3f << 0)
47 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
48 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
49 #define TX_BD_FLAGS_PACKET_END (1 << 6)
50 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
51 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
52 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
53 #define TX_BD_FLAGS_LHINT (3 << 13)
54 #define TX_BD_FLAGS_LHINT_SHIFT 13
55 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
56 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
57 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
58 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
59 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
60 #define TX_BD_LEN (0xffff << 16)
61 #define TX_BD_LEN_SHIFT 16
62
63 u32 tx_bd_opaque;
64 __le64 tx_bd_haddr;
65 } __packed;
66
67 #define TX_OPAQUE_IDX_MASK 0x0000ffff
68 #define TX_OPAQUE_BDS_MASK 0x00ff0000
69 #define TX_OPAQUE_BDS_SHIFT 16
70 #define TX_OPAQUE_RING_MASK 0xff000000
71 #define TX_OPAQUE_RING_SHIFT 24
72
73 #define SET_TX_OPAQUE(bp, txr, idx, bds) \
74 (((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) | \
75 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bp)->tx_ring_mask))
76
77 #define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)
78 #define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \
79 TX_OPAQUE_RING_SHIFT)
80 #define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \
81 TX_OPAQUE_BDS_SHIFT)
82 #define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
83 (bp)->tx_ring_mask)
84
85 #define TX_BD_CNT(n) (((n) << TX_BD_FLAGS_BD_CNT_SHIFT) & TX_BD_FLAGS_BD_CNT)
86
87 #define TX_MAX_BD_CNT 32
88
89 #define TX_MAX_FRAGS (TX_MAX_BD_CNT - 2)
90
91 struct tx_bd_ext {
92 __le32 tx_bd_hsize_lflags;
93 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
94 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
95 #define TX_BD_FLAGS_NO_CRC (1 << 2)
96 #define TX_BD_FLAGS_STAMP (1 << 3)
97 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
98 #define TX_BD_FLAGS_LSO (1 << 5)
99 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
100 #define TX_BD_FLAGS_T_IPID (1 << 7)
101 #define TX_BD_HSIZE (0xff << 16)
102 #define TX_BD_HSIZE_SHIFT 16
103
104 __le32 tx_bd_mss;
105 __le32 tx_bd_cfa_action;
106 #define TX_BD_CFA_ACTION (0xffff << 16)
107 #define TX_BD_CFA_ACTION_SHIFT 16
108
109 __le32 tx_bd_cfa_meta;
110 #define TX_BD_CFA_META_MASK 0xfffffff
111 #define TX_BD_CFA_META_VID_MASK 0xfff
112 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
113 #define TX_BD_CFA_META_PRI_SHIFT 12
114 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
115 #define TX_BD_CFA_META_TPID_SHIFT 16
116 #define TX_BD_CFA_META_KEY (0xf << 28)
117 #define TX_BD_CFA_META_KEY_SHIFT 28
118 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
119 };
120
121 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
122
123 struct rx_bd {
124 __le32 rx_bd_len_flags_type;
125 #define RX_BD_TYPE (0x3f << 0)
126 #define RX_BD_TYPE_RX_PACKET_BD 0x4
127 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
128 #define RX_BD_TYPE_RX_AGG_BD 0x6
129 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
130 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
131 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
132 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
133 #define RX_BD_FLAGS_SOP (1 << 6)
134 #define RX_BD_FLAGS_EOP (1 << 7)
135 #define RX_BD_FLAGS_BUFFERS (3 << 8)
136 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
137 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
138 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
139 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
140 #define RX_BD_LEN (0xffff << 16)
141 #define RX_BD_LEN_SHIFT 16
142
143 u32 rx_bd_opaque;
144 __le64 rx_bd_haddr;
145 };
146
147 struct tx_cmp {
148 __le32 tx_cmp_flags_type;
149 #define CMP_TYPE (0x3f << 0)
150 #define CMP_TYPE_TX_L2_CMP 0
151 #define CMP_TYPE_TX_L2_COAL_CMP 2
152 #define CMP_TYPE_TX_L2_PKT_TS_CMP 4
153 #define CMP_TYPE_RX_L2_CMP 17
154 #define CMP_TYPE_RX_AGG_CMP 18
155 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
156 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
157 #define CMP_TYPE_RX_TPA_AGG_CMP 22
158 #define CMP_TYPE_RX_L2_V3_CMP 23
159 #define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25
160 #define CMP_TYPE_STATUS_CMP 32
161 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
162 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
163 #define CMP_TYPE_ERROR_STATUS 48
164 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
165 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
166 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
167 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
168 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
169
170 #define TX_CMP_FLAGS_ERROR (1 << 6)
171 #define TX_CMP_FLAGS_PUSH (1 << 7)
172
173 u32 tx_cmp_opaque;
174 __le32 tx_cmp_errors_v;
175 #define TX_CMP_V (1 << 0)
176 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
177 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
178 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
179 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
180 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
181 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
182 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
183 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
184 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
185
186 __le32 sq_cons_idx;
187 #define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff
188 };
189
190 #define TX_CMP_SQ_CONS_IDX(txcmp) \
191 (le32_to_cpu((txcmp)->sq_cons_idx) & TX_CMP_SQ_CONS_IDX_MASK)
192
193 struct tx_ts_cmp {
194 __le32 tx_ts_cmp_flags_type;
195 #define TX_TS_CMP_FLAGS_ERROR (1 << 6)
196 #define TX_TS_CMP_FLAGS_TS_TYPE (1 << 7)
197 #define TX_TS_CMP_FLAGS_TS_TYPE_PM (0 << 7)
198 #define TX_TS_CMP_FLAGS_TS_TYPE_PA (1 << 7)
199 #define TX_TS_CMP_FLAGS_TS_FALLBACK (1 << 8)
200 #define TX_TS_CMP_TS_SUB_NS (0xf << 12)
201 #define TX_TS_CMP_TS_NS_MID (0xffff << 16)
202 #define TX_TS_CMP_TS_NS_MID_SFT 16
203 u32 tx_ts_cmp_opaque;
204 __le32 tx_ts_cmp_errors_v;
205 #define TX_TS_CMP_V (1 << 0)
206 #define TX_TS_CMP_TS_INVALID_ERR (1 << 10)
207 __le32 tx_ts_cmp_ts_ns_lo;
208 };
209
210 #define BNXT_GET_TX_TS_48B_NS(tscmp) \
211 (le32_to_cpu((tscmp)->tx_ts_cmp_ts_ns_lo) | \
212 ((u64)(le32_to_cpu((tscmp)->tx_ts_cmp_flags_type) & \
213 TX_TS_CMP_TS_NS_MID) << TX_TS_CMP_TS_NS_MID_SFT))
214
215 #define BNXT_TX_TS_ERR(tscmp) \
216 (((tscmp)->tx_ts_cmp_flags_type & cpu_to_le32(TX_TS_CMP_FLAGS_ERROR)) &&\
217 ((tscmp)->tx_ts_cmp_errors_v & cpu_to_le32(TX_TS_CMP_TS_INVALID_ERR)))
218
219 struct rx_cmp {
220 __le32 rx_cmp_len_flags_type;
221 #define RX_CMP_CMP_TYPE (0x3f << 0)
222 #define RX_CMP_FLAGS_ERROR (1 << 6)
223 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
224 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
225 #define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)
226 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
227 #define RX_CMP_FLAGS_ITYPES_MASK 0xf000
228 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
229 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
230 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
231 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
232 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
233 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
234 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
235 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
236 #define RX_CMP_LEN (0xffff << 16)
237 #define RX_CMP_LEN_SHIFT 16
238
239 u32 rx_cmp_opaque;
240 __le32 rx_cmp_misc_v1;
241 #define RX_CMP_V1 (1 << 0)
242 #define RX_CMP_AGG_BUFS (0x1f << 1)
243 #define RX_CMP_AGG_BUFS_SHIFT 1
244 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
245 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
246 #define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)
247 #define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12
248 #define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)
249 #define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8
250 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
251 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
252 #define RX_CMP_SUB_NS_TS (0xf << 16)
253 #define RX_CMP_SUB_NS_TS_SHIFT 16
254 #define RX_CMP_METADATA1 (0xf << 28)
255 #define RX_CMP_METADATA1_SHIFT 28
256 #define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)
257 #define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)
258 #define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)
259 #define RX_CMP_METADATA1_VALID (0x8 << 28)
260
261 __le32 rx_cmp_rss_hash;
262 };
263
264 #define BNXT_PTP_RX_TS_VALID(flags) \
265 (((flags) & RX_CMP_FLAGS_ITYPES_MASK) == RX_CMP_FLAGS_ITYPE_PTP_W_TS)
266
267 #define BNXT_ALL_RX_TS_VALID(flags) \
268 !((flags) & RX_CMP_FLAGS_PKT_METADATA_PRESENT)
269
270 #define RX_CMP_HASH_VALID(rxcmp) \
271 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
272
273 #define RSS_PROFILE_ID_MASK 0x1f
274
275 #define RX_CMP_HASH_TYPE(rxcmp) \
276 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
277 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
278
279 #define RX_CMP_ITYPES(rxcmp) \
280 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_FLAGS_ITYPES_MASK)
281
282 #define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \
283 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_LEGACY) >>\
284 RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT)
285
286 #define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \
287 ((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_V3_RSS_EXT_OP_NEW) >>\
288 RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT)
289
290 #define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \
291 (((bp)->rss_cap & BNXT_RSS_CAP_RSS_TCAM) ? \
292 RX_CMP_V3_HASH_TYPE_NEW(rxcmp) : \
293 RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp))
294
295 #define EXT_OP_INNER_4 0x0
296 #define EXT_OP_OUTER_4 0x2
297 #define EXT_OP_INNFL_3 0x8
298 #define EXT_OP_OUTFL_3 0xa
299
300 #define RX_CMP_VLAN_VALID(rxcmp) \
301 ((rxcmp)->rx_cmp_misc_v1 & cpu_to_le32(RX_CMP_METADATA1_VALID))
302
303 #define RX_CMP_VLAN_TPID_SEL(rxcmp) \
304 (le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_METADATA1_TPID_SEL)
305
306 struct rx_cmp_ext {
307 __le32 rx_cmp_flags2;
308 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
309 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
310 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
311 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
312 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
313 __le32 rx_cmp_meta_data;
314 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
315 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
316 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
317 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
318 __le32 rx_cmp_cfa_code_errors_v2;
319 #define RX_CMP_V (1 << 0)
320 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
321 #define RX_CMPL_ERRORS_SFT 1
322 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
323 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
324 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
325 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
326 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
327 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
328 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
329 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
330 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
331 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
332 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
333 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
334 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
335 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
336 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
337 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
338 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
339 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
340 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
341 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
342 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
343 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
344 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
345 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
346 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
347 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
348 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
349 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
350
351 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
352 #define RX_CMPL_CFA_CODE_SFT 16
353 #define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)
354 #define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)
355 #define RX_CMPL_METADATA0_SFT 16
356
357 __le32 rx_cmp_timestamp;
358 };
359
360 #define RX_CMP_L2_ERRORS \
361 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
362
363 #define RX_CMP_L4_CS_BITS \
364 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
365
366 #define RX_CMP_L4_CS_ERR_BITS \
367 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
368
369 #define RX_CMP_L4_CS_OK(rxcmp1) \
370 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
371 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
372
373 #define RX_CMP_ENCAP(rxcmp1) \
374 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
375 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
376
377 #define RX_CMP_CFA_CODE(rxcmpl1) \
378 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
379 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
380
381 #define RX_CMP_METADATA0_TCI(rxcmp1) \
382 ((le32_to_cpu((rxcmp1)->rx_cmp_cfa_code_errors_v2) & \
383 RX_CMPL_METADATA0_TCI_MASK) >> RX_CMPL_METADATA0_SFT)
384
385 struct rx_agg_cmp {
386 __le32 rx_agg_cmp_len_flags_type;
387 #define RX_AGG_CMP_TYPE (0x3f << 0)
388 #define RX_AGG_CMP_LEN (0xffff << 16)
389 #define RX_AGG_CMP_LEN_SHIFT 16
390 u32 rx_agg_cmp_opaque;
391 __le32 rx_agg_cmp_v;
392 #define RX_AGG_CMP_V (1 << 0)
393 #define RX_AGG_CMP_AGG_ID (0x0fff << 16)
394 #define RX_AGG_CMP_AGG_ID_SHIFT 16
395 __le32 rx_agg_cmp_unused;
396 };
397
398 #define TPA_AGG_AGG_ID(rx_agg) \
399 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
400 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
401
402 struct rx_tpa_start_cmp {
403 __le32 rx_tpa_start_cmp_len_flags_type;
404 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
405 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
406 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
407 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
408 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
409 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
410 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
411 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
412 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
413 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
414 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
415 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
416 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
417 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
418 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
419 #define RX_TPA_START_CMP_LEN (0xffff << 16)
420 #define RX_TPA_START_CMP_LEN_SHIFT 16
421
422 u32 rx_tpa_start_cmp_opaque;
423 __le32 rx_tpa_start_cmp_misc_v1;
424 #define RX_TPA_START_CMP_V1 (0x1 << 0)
425 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
426 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
427 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)
428 #define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7
429 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
430 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
431 #define RX_TPA_START_CMP_AGG_ID_P5 (0x0fff << 16)
432 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
433 #define RX_TPA_START_CMP_METADATA1 (0xf << 28)
434 #define RX_TPA_START_CMP_METADATA1_SHIFT 28
435 #define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)
436 #define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)
437 #define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)
438 #define RX_TPA_START_METADATA1_VALID (0x8 << 28)
439
440 __le32 rx_tpa_start_cmp_rss_hash;
441 };
442
443 #define TPA_START_HASH_VALID(rx_tpa_start) \
444 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
445 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
446
447 #define TPA_START_HASH_TYPE(rx_tpa_start) \
448 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
449 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
450 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
451
452 #define TPA_START_V3_HASH_TYPE(rx_tpa_start) \
453 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
454 RX_TPA_START_CMP_V3_RSS_HASH_TYPE) >> \
455 RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
456
457 #define TPA_START_AGG_ID(rx_tpa_start) \
458 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
459 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
460
461 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
462 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
463 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
464
465 #define TPA_START_ERROR(rx_tpa_start) \
466 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
467 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
468
469 #define TPA_START_VLAN_VALID(rx_tpa_start) \
470 ((rx_tpa_start)->rx_tpa_start_cmp_misc_v1 & \
471 cpu_to_le32(RX_TPA_START_METADATA1_VALID))
472
473 #define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \
474 (le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
475 RX_TPA_START_METADATA1_TPID_SEL)
476
477 struct rx_tpa_start_cmp_ext {
478 __le32 rx_tpa_start_cmp_flags2;
479 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
480 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
481 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
482 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
483 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
484 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
485 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
486 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
487 #define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)
488 #define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)
489 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
490 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
491
492 __le32 rx_tpa_start_cmp_metadata;
493 __le32 rx_tpa_start_cmp_cfa_code_v2;
494 #define RX_TPA_START_CMP_V2 (0x1 << 0)
495 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
496 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
497 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
498 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
499 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
500 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
501 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
502 #define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)
503 #define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)
504 #define RX_TPA_START_CMP_METADATA0_SFT 16
505 __le32 rx_tpa_start_cmp_hdr_info;
506 };
507
508 #define TPA_START_CFA_CODE(rx_tpa_start) \
509 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
510 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
511
512 #define TPA_START_IS_IPV6(rx_tpa_start) \
513 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
514 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
515
516 #define TPA_START_ERROR_CODE(rx_tpa_start) \
517 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
518 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
519 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
520
521 #define TPA_START_METADATA0_TCI(rx_tpa_start) \
522 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
523 RX_TPA_START_CMP_METADATA0_TCI_MASK) >> \
524 RX_TPA_START_CMP_METADATA0_SFT)
525
526 struct rx_tpa_end_cmp {
527 __le32 rx_tpa_end_cmp_len_flags_type;
528 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
529 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
530 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
531 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
532 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
533 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
534 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
535 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
536 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
537 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
538 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
539 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
540 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
541 #define RX_TPA_END_CMP_LEN (0xffff << 16)
542 #define RX_TPA_END_CMP_LEN_SHIFT 16
543
544 u32 rx_tpa_end_cmp_opaque;
545 __le32 rx_tpa_end_cmp_misc_v1;
546 #define RX_TPA_END_CMP_V1 (0x1 << 0)
547 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
548 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
549 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
550 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
551 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
552 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
553 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
554 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
555 #define RX_TPA_END_CMP_AGG_ID_P5 (0x0fff << 16)
556 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
557
558 __le32 rx_tpa_end_cmp_tsdelta;
559 #define RX_TPA_END_GRO_TS (0x1 << 31)
560 };
561
562 #define TPA_END_AGG_ID(rx_tpa_end) \
563 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
564 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
565
566 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
567 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
568 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
569
570 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
571 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
572 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
573
574 #define TPA_END_AGG_BUFS(rx_tpa_end) \
575 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
576 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
577
578 #define TPA_END_TPA_SEGS(rx_tpa_end) \
579 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
580 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
581
582 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
583 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
584 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
585
586 #define TPA_END_GRO(rx_tpa_end) \
587 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
588 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
589
590 #define TPA_END_GRO_TS(rx_tpa_end) \
591 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
592 cpu_to_le32(RX_TPA_END_GRO_TS)))
593
594 struct rx_tpa_end_cmp_ext {
595 __le32 rx_tpa_end_cmp_dup_acks;
596 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
597 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
598 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
599 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
600 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
601
602 __le32 rx_tpa_end_cmp_seg_len;
603 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
604
605 __le32 rx_tpa_end_cmp_errors_v2;
606 #define RX_TPA_END_CMP_V2 (0x1 << 0)
607 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
608 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
609 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
610 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
611 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
612 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
613 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
614 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
615
616 u32 rx_tpa_end_cmp_start_opaque;
617 };
618
619 #define TPA_END_ERRORS(rx_tpa_end_ext) \
620 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
621 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
622
623 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
624 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
625 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
626 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
627
628 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
629 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
630 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
631
632 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
633 (((data1) & \
634 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
635 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
636
637 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
638 (((data1) & \
639 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
640 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
641
642 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
643 ((data2) & \
644 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
645
646 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
647 !!((data1) & \
648 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
649
650 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
651 !!((data1) & \
652 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
653
654 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
655 (((data1) & \
656 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
657 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
658
659 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
660 (((data2) & \
661 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
662 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
663
664 struct nqe_cn {
665 __le16 type;
666 #define NQ_CN_TYPE_MASK 0x3fUL
667 #define NQ_CN_TYPE_SFT 0
668 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
669 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
670 #define NQ_CN_TOGGLE_MASK 0xc0UL
671 #define NQ_CN_TOGGLE_SFT 6
672 __le16 reserved16;
673 __le32 cq_handle_low;
674 __le32 v;
675 #define NQ_CN_V 0x1UL
676 __le32 cq_handle_high;
677 };
678
679 #define BNXT_NQ_HDL_IDX_MASK 0x00ffffff
680 #define BNXT_NQ_HDL_TYPE_MASK 0xff000000
681 #define BNXT_NQ_HDL_TYPE_SHIFT 24
682 #define BNXT_NQ_HDL_TYPE_RX 0x00
683 #define BNXT_NQ_HDL_TYPE_TX 0x01
684
685 #define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)
686 #define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \
687 BNXT_NQ_HDL_TYPE_SHIFT)
688
689 #define BNXT_SET_NQ_HDL(cpr) \
690 (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx)
691
692 #define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)
693 #define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \
694 NQ_CN_TOGGLE_SFT)
695
696 #define DB_IDX_MASK 0xffffff
697 #define DB_IDX_VALID (0x1 << 26)
698 #define DB_IRQ_DIS (0x1 << 27)
699 #define DB_KEY_TX (0x0 << 28)
700 #define DB_KEY_RX (0x1 << 28)
701 #define DB_KEY_CP (0x2 << 28)
702 #define DB_KEY_ST (0x3 << 28)
703 #define DB_KEY_TX_PUSH (0x4 << 28)
704 #define DB_LONG_TX_PUSH (0x2 << 24)
705
706 #define BNXT_MIN_ROCE_CP_RINGS 2
707 #define BNXT_MIN_ROCE_STAT_CTXS 1
708
709 /* 64-bit doorbell */
710 #define DBR_INDEX_MASK 0x0000000000ffffffULL
711 #define DBR_EPOCH_MASK 0x01000000UL
712 #define DBR_EPOCH_SFT 24
713 #define DBR_TOGGLE_MASK 0x06000000UL
714 #define DBR_TOGGLE_SFT 25
715 #define DBR_XID_MASK 0x000fffff00000000ULL
716 #define DBR_XID_SFT 32
717 #define DBR_PATH_L2 (0x1ULL << 56)
718 #define DBR_VALID (0x1ULL << 58)
719 #define DBR_TYPE_SQ (0x0ULL << 60)
720 #define DBR_TYPE_RQ (0x1ULL << 60)
721 #define DBR_TYPE_SRQ (0x2ULL << 60)
722 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
723 #define DBR_TYPE_CQ (0x4ULL << 60)
724 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
725 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
726 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
727 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
728 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
729 #define DBR_TYPE_NQ (0xaULL << 60)
730 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
731 #define DBR_TYPE_NQ_MASK (0xeULL << 60)
732 #define DBR_TYPE_NULL (0xfULL << 60)
733
734 #define DB_PF_OFFSET_P5 0x10000
735 #define DB_VF_OFFSET_P5 0x4000
736
737 #define INVALID_HW_RING_ID ((u16)-1)
738
739 /* The hardware supports certain page sizes. Use the supported page sizes
740 * to allocate the rings.
741 */
742 #if (PAGE_SHIFT < 12)
743 #define BNXT_PAGE_SHIFT 12
744 #elif (PAGE_SHIFT <= 13)
745 #define BNXT_PAGE_SHIFT PAGE_SHIFT
746 #elif (PAGE_SHIFT < 16)
747 #define BNXT_PAGE_SHIFT 13
748 #else
749 #define BNXT_PAGE_SHIFT 16
750 #endif
751
752 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
753
754 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
755 #if (PAGE_SHIFT > 15)
756 #define BNXT_RX_PAGE_SHIFT 15
757 #else
758 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
759 #endif
760
761 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
762
763 #define BNXT_MAX_MTU 9500
764
765 /* First RX buffer page in XDP multi-buf mode
766 *
767 * +-------------------------------------------------------------------------+
768 * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info|
769 * | (bp->rx_dma_offset) | | |
770 * +-------------------------------------------------------------------------+
771 */
772 #define BNXT_MAX_PAGE_MODE_MTU_SBUF \
773 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
774 XDP_PACKET_HEADROOM)
775 #define BNXT_MAX_PAGE_MODE_MTU \
776 (BNXT_MAX_PAGE_MODE_MTU_SBUF - \
777 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
778
779 #define BNXT_MIN_PKT_SIZE 52
780
781 #define BNXT_DEFAULT_RX_RING_SIZE 511
782 #define BNXT_DEFAULT_TX_RING_SIZE 511
783
784 #define MAX_TPA 64
785 #define MAX_TPA_P5 256
786 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
787 #define MAX_TPA_SEGS_P5 0x3f
788
789 #if (BNXT_PAGE_SHIFT == 16)
790 #define MAX_RX_PAGES_AGG_ENA 1
791 #define MAX_RX_PAGES 4
792 #define MAX_RX_AGG_PAGES 4
793 #define MAX_TX_PAGES 1
794 #define MAX_CP_PAGES 16
795 #else
796 #define MAX_RX_PAGES_AGG_ENA 8
797 #define MAX_RX_PAGES 32
798 #define MAX_RX_AGG_PAGES 32
799 #define MAX_TX_PAGES 8
800 #define MAX_CP_PAGES 128
801 #endif
802
803 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
804 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
805 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
806
807 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
808 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
809
810 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
811
812 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
813 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
814
815 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
816
817 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
818 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
819 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
820 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
821
822 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra
823 * BD because the first TX BD is always a long BD.
824 */
825 #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)
826
827 #define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
828 #define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \
829 (BNXT_PAGE_SHIFT - 4))
830 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
831
832 #define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))
833 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
834
835 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
836 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
837
838 #define TX_CMP_VALID(txcmp, raw_cons) \
839 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
840 !((raw_cons) & bp->cp_bit))
841
842 #define RX_CMP_VALID(rxcmp1, raw_cons) \
843 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
844 !((raw_cons) & bp->cp_bit))
845
846 #define RX_AGG_CMP_VALID(agg, raw_cons) \
847 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
848 !((raw_cons) & bp->cp_bit))
849
850 #define NQ_CMP_VALID(nqcmp, raw_cons) \
851 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
852
853 #define TX_CMP_TYPE(txcmp) \
854 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
855
856 #define RX_CMP_TYPE(rxcmp) \
857 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
858
859 #define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)
860 #define NEXT_RX(idx) ((idx) + 1)
861
862 #define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)
863 #define NEXT_RX_AGG(idx) ((idx) + 1)
864
865 #define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)
866 #define NEXT_TX(idx) ((idx) + 1)
867
868 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
869 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
870 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
871 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
872
873 #define DFLT_HWRM_CMD_TIMEOUT 500
874
875 #define BNXT_RX_EVENT 1
876 #define BNXT_AGG_EVENT 2
877 #define BNXT_TX_EVENT 4
878 #define BNXT_REDIRECT_EVENT 8
879 #define BNXT_TX_CMP_EVENT 0x10
880
881 struct bnxt_sw_tx_bd {
882 union {
883 struct sk_buff *skb;
884 struct xdp_frame *xdpf;
885 };
886 DEFINE_DMA_UNMAP_ADDR(mapping);
887 DEFINE_DMA_UNMAP_LEN(len);
888 struct page *page;
889 u8 is_ts_pkt;
890 u8 is_push;
891 u8 action;
892 unsigned short nr_frags;
893 union {
894 u16 rx_prod;
895 u16 txts_prod;
896 };
897 };
898
899 struct bnxt_sw_rx_bd {
900 void *data;
901 u8 *data_ptr;
902 dma_addr_t mapping;
903 };
904
905 struct bnxt_sw_rx_agg_bd {
906 struct page *page;
907 unsigned int offset;
908 dma_addr_t mapping;
909 };
910
911 struct bnxt_ring_mem_info {
912 int nr_pages;
913 int page_size;
914 u16 flags;
915 #define BNXT_RMEM_VALID_PTE_FLAG 1
916 #define BNXT_RMEM_RING_PTE_FLAG 2
917 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
918
919 u16 depth;
920 struct bnxt_ctx_mem_type *ctx_mem;
921
922 void **pg_arr;
923 dma_addr_t *dma_arr;
924
925 __le64 *pg_tbl;
926 dma_addr_t pg_tbl_map;
927
928 int vmem_size;
929 void **vmem;
930 };
931
932 struct bnxt_ring_struct {
933 struct bnxt_ring_mem_info ring_mem;
934
935 u16 fw_ring_id; /* Ring id filled by Chimp FW */
936 union {
937 u16 grp_idx;
938 u16 map_idx; /* Used by cmpl rings */
939 };
940 u32 handle;
941 u8 queue_id;
942 };
943
944 struct tx_push_bd {
945 __le32 doorbell;
946 __le32 tx_bd_len_flags_type;
947 u32 tx_bd_opaque;
948 struct tx_bd_ext txbd2;
949 };
950
951 struct tx_push_buffer {
952 struct tx_push_bd push_bd;
953 u32 data[25];
954 };
955
956 struct bnxt_db_info {
957 void __iomem *doorbell;
958 union {
959 u64 db_key64;
960 u32 db_key32;
961 };
962 u32 db_ring_mask;
963 u32 db_epoch_mask;
964 u8 db_epoch_shift;
965 };
966
967 #define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \
968 ((db)->db_epoch_shift))
969
970 #define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)
971
972 #define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \
973 DB_EPOCH(db, idx))
974
975 struct bnxt_tx_ring_info {
976 struct bnxt_napi *bnapi;
977 struct bnxt_cp_ring_info *tx_cpr;
978 u16 tx_prod;
979 u16 tx_cons;
980 u16 tx_hw_cons;
981 u16 txq_index;
982 u8 tx_napi_idx;
983 u8 kick_pending;
984 struct bnxt_db_info tx_db;
985
986 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
987 struct bnxt_sw_tx_bd *tx_buf_ring;
988
989 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
990
991 struct tx_push_buffer *tx_push;
992 dma_addr_t tx_push_mapping;
993 __le64 data_mapping;
994
995 #define BNXT_DEV_STATE_CLOSING 0x1
996 u32 dev_state;
997
998 struct bnxt_ring_struct tx_ring_struct;
999 /* Synchronize simultaneous xdp_xmit on same ring */
1000 spinlock_t xdp_tx_lock;
1001 };
1002
1003 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
1004 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
1005 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
1006 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
1007 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
1008 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
1009 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
1010 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
1011 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
1012 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
1013
1014 #define BNXT_COAL_CMPL_ENABLES \
1015 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
1016 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
1017 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
1018 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
1019
1020 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
1021 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
1022
1023 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
1024 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
1025
1026 struct bnxt_coal_cap {
1027 u32 cmpl_params;
1028 u32 nq_params;
1029 u16 num_cmpl_dma_aggr_max;
1030 u16 num_cmpl_dma_aggr_during_int_max;
1031 u16 cmpl_aggr_dma_tmr_max;
1032 u16 cmpl_aggr_dma_tmr_during_int_max;
1033 u16 int_lat_tmr_min_max;
1034 u16 int_lat_tmr_max_max;
1035 u16 num_cmpl_aggr_int_max;
1036 u16 timer_units;
1037 };
1038
1039 struct bnxt_coal {
1040 u16 coal_ticks;
1041 u16 coal_ticks_irq;
1042 u16 coal_bufs;
1043 u16 coal_bufs_irq;
1044 /* RING_IDLE enabled when coal ticks < idle_thresh */
1045 u16 idle_thresh;
1046 u8 bufs_per_record;
1047 u8 budget;
1048 u16 flags;
1049 };
1050
1051 struct bnxt_tpa_info {
1052 void *data;
1053 u8 *data_ptr;
1054 dma_addr_t mapping;
1055 u16 len;
1056 unsigned short gso_type;
1057 u32 flags2;
1058 u32 metadata;
1059 enum pkt_hash_types hash_type;
1060 u32 rss_hash;
1061 u32 hdr_info;
1062
1063 #define BNXT_TPA_L4_SIZE(hdr_info) \
1064 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
1065
1066 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
1067 (((hdr_info) >> 18) & 0x1ff)
1068
1069 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
1070 (((hdr_info) >> 9) & 0x1ff)
1071
1072 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
1073 ((hdr_info) & 0x1ff)
1074
1075 u16 cfa_code; /* cfa_code in TPA start compl */
1076 u8 agg_count;
1077 u8 vlan_valid:1;
1078 u8 cfa_code_valid:1;
1079 struct rx_agg_cmp *agg_arr;
1080 };
1081
1082 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
1083
1084 struct bnxt_tpa_idx_map {
1085 u16 agg_id_tbl[1024];
1086 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
1087 };
1088
1089 struct bnxt_rx_ring_info {
1090 struct bnxt_napi *bnapi;
1091 struct bnxt_cp_ring_info *rx_cpr;
1092 u16 rx_prod;
1093 u16 rx_agg_prod;
1094 u16 rx_sw_agg_prod;
1095 u16 rx_next_cons;
1096 struct bnxt_db_info rx_db;
1097 struct bnxt_db_info rx_agg_db;
1098
1099 struct bpf_prog *xdp_prog;
1100
1101 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
1102 struct bnxt_sw_rx_bd *rx_buf_ring;
1103
1104 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
1105 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
1106
1107 unsigned long *rx_agg_bmap;
1108 u16 rx_agg_bmap_size;
1109
1110 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
1111 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
1112
1113 struct bnxt_tpa_info *rx_tpa;
1114 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
1115
1116 struct bnxt_ring_struct rx_ring_struct;
1117 struct bnxt_ring_struct rx_agg_ring_struct;
1118 struct xdp_rxq_info xdp_rxq;
1119 struct page_pool *page_pool;
1120 struct page_pool *head_pool;
1121 };
1122
1123 struct bnxt_rx_sw_stats {
1124 u64 rx_l4_csum_errors;
1125 u64 rx_resets;
1126 u64 rx_buf_errors;
1127 u64 rx_oom_discards;
1128 u64 rx_netpoll_discards;
1129 };
1130
1131 struct bnxt_tx_sw_stats {
1132 u64 tx_resets;
1133 };
1134
1135 struct bnxt_cmn_sw_stats {
1136 u64 missed_irqs;
1137 };
1138
1139 struct bnxt_sw_stats {
1140 struct bnxt_rx_sw_stats rx;
1141 struct bnxt_tx_sw_stats tx;
1142 struct bnxt_cmn_sw_stats cmn;
1143 };
1144
1145 struct bnxt_total_ring_err_stats {
1146 u64 rx_total_l4_csum_errors;
1147 u64 rx_total_resets;
1148 u64 rx_total_buf_errors;
1149 u64 rx_total_oom_discards;
1150 u64 rx_total_netpoll_discards;
1151 u64 rx_total_ring_discards;
1152 u64 tx_total_resets;
1153 u64 tx_total_ring_discards;
1154 u64 total_missed_irqs;
1155 };
1156
1157 struct bnxt_stats_mem {
1158 u64 *sw_stats;
1159 u64 *hw_masks;
1160 void *hw_stats;
1161 dma_addr_t hw_stats_map;
1162 int len;
1163 };
1164
1165 struct bnxt_cp_ring_info {
1166 struct bnxt_napi *bnapi;
1167 u32 cp_raw_cons;
1168 struct bnxt_db_info cp_db;
1169
1170 u8 had_work_done:1;
1171 u8 has_more_work:1;
1172 u8 had_nqe_notify:1;
1173 u8 toggle;
1174
1175 u8 cp_ring_type;
1176 u8 cp_idx;
1177
1178 u32 last_cp_raw_cons;
1179
1180 struct bnxt_coal rx_ring_coal;
1181 u64 rx_packets;
1182 u64 rx_bytes;
1183 u64 event_ctr;
1184
1185 struct dim dim;
1186
1187 union {
1188 struct tx_cmp **cp_desc_ring;
1189 struct nqe_cn **nq_desc_ring;
1190 };
1191
1192 dma_addr_t *cp_desc_mapping;
1193
1194 struct bnxt_stats_mem stats;
1195 u32 hw_stats_ctx_id;
1196
1197 struct bnxt_sw_stats *sw_stats;
1198
1199 struct bnxt_ring_struct cp_ring_struct;
1200
1201 int cp_ring_count;
1202 struct bnxt_cp_ring_info *cp_ring_arr;
1203 };
1204
1205 #define BNXT_MAX_QUEUE 8
1206 #define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE
1207
1208 #define bnxt_for_each_napi_tx(iter, bnapi, txr) \
1209 for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \
1210 txr = (iter < BNXT_MAX_TXR_PER_NAPI - 1) ? \
1211 (bnapi)->tx_ring[++iter] : NULL)
1212
1213 struct bnxt_napi {
1214 struct napi_struct napi;
1215 struct bnxt *bp;
1216
1217 int index;
1218 struct bnxt_cp_ring_info cp_ring;
1219 struct bnxt_rx_ring_info *rx_ring;
1220 struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];
1221
1222 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
1223 int budget);
1224 u8 events;
1225 u8 tx_fault:1;
1226
1227 u32 flags;
1228 #define BNXT_NAPI_FLAG_XDP 0x1
1229
1230 bool in_reset;
1231 };
1232
1233 /* "TxRx", 2 hypens, plus maximum integer */
1234 #define BNXT_IRQ_NAME_EXTRA 17
1235
1236 struct bnxt_irq {
1237 irq_handler_t handler;
1238 unsigned int vector;
1239 u8 requested:1;
1240 u8 have_cpumask:1;
1241 char name[IFNAMSIZ + BNXT_IRQ_NAME_EXTRA];
1242 cpumask_var_t cpu_mask;
1243
1244 struct bnxt *bp;
1245 int msix_nr;
1246 int ring_nr;
1247 struct irq_affinity_notify affinity_notify;
1248 };
1249
1250 #define HWRM_RING_ALLOC_TX 0x1
1251 #define HWRM_RING_ALLOC_RX 0x2
1252 #define HWRM_RING_ALLOC_AGG 0x4
1253 #define HWRM_RING_ALLOC_CMPL 0x8
1254 #define HWRM_RING_ALLOC_NQ 0x10
1255
1256 #define INVALID_STATS_CTX_ID -1
1257
1258 struct bnxt_ring_grp_info {
1259 u16 fw_stats_ctx;
1260 u16 fw_grp_id;
1261 u16 rx_fw_ring_id;
1262 u16 agg_fw_ring_id;
1263 u16 cp_fw_ring_id;
1264 };
1265
1266 #define BNXT_VNIC_DEFAULT 0
1267 #define BNXT_VNIC_NTUPLE 1
1268
1269 struct bnxt_vnic_info {
1270 u16 fw_vnic_id; /* returned by Chimp during alloc */
1271 #define BNXT_MAX_CTX_PER_VNIC 8
1272 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1273 u16 fw_l2_ctx_id;
1274 u16 mru;
1275 #define BNXT_MAX_UC_ADDRS 4
1276 struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];
1277 /* index 0 always dev_addr */
1278 u16 uc_filter_count;
1279 u8 *uc_list;
1280
1281 u16 *fw_grp_ids;
1282 dma_addr_t rss_table_dma_addr;
1283 __le16 *rss_table;
1284 dma_addr_t rss_hash_key_dma_addr;
1285 u64 *rss_hash_key;
1286 int rss_table_size;
1287 #define BNXT_RSS_TABLE_ENTRIES_P5 64
1288 #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1289 #define BNXT_RSS_TABLE_MAX_TBL_P5 8
1290 #define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1291 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1292 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1293 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1294
1295 u32 rx_mask;
1296
1297 u8 *mc_list;
1298 int mc_list_size;
1299 int mc_list_count;
1300 dma_addr_t mc_list_mapping;
1301 #define BNXT_MAX_MC_ADDRS 16
1302
1303 u32 flags;
1304 #define BNXT_VNIC_RSS_FLAG 1
1305 #define BNXT_VNIC_RFS_FLAG 2
1306 #define BNXT_VNIC_MCAST_FLAG 4
1307 #define BNXT_VNIC_UCAST_FLAG 8
1308 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1309 #define BNXT_VNIC_NTUPLE_FLAG 0x20
1310 #define BNXT_VNIC_RSSCTX_FLAG 0x40
1311 struct ethtool_rxfh_context *rss_ctx;
1312 u32 vnic_id;
1313 };
1314
1315 struct bnxt_rss_ctx {
1316 struct bnxt_vnic_info vnic;
1317 u8 index;
1318 };
1319
1320 #define BNXT_MAX_ETH_RSS_CTX 32
1321 #define BNXT_VNIC_ID_INVALID 0xffffffff
1322
1323 struct bnxt_hw_rings {
1324 int tx;
1325 int rx;
1326 int grp;
1327 int cp;
1328 int cp_p5;
1329 int stat;
1330 int vnic;
1331 int rss_ctx;
1332 };
1333
1334 struct bnxt_hw_resc {
1335 u16 min_rsscos_ctxs;
1336 u16 max_rsscos_ctxs;
1337 u16 resv_rsscos_ctxs;
1338 u16 min_cp_rings;
1339 u16 max_cp_rings;
1340 u16 resv_cp_rings;
1341 u16 min_tx_rings;
1342 u16 max_tx_rings;
1343 u16 resv_tx_rings;
1344 u16 max_tx_sch_inputs;
1345 u16 min_rx_rings;
1346 u16 max_rx_rings;
1347 u16 resv_rx_rings;
1348 u16 min_hw_ring_grps;
1349 u16 max_hw_ring_grps;
1350 u16 resv_hw_ring_grps;
1351 u16 min_l2_ctxs;
1352 u16 max_l2_ctxs;
1353 u16 min_vnics;
1354 u16 max_vnics;
1355 u16 resv_vnics;
1356 u16 min_stat_ctxs;
1357 u16 max_stat_ctxs;
1358 u16 resv_stat_ctxs;
1359 u16 max_nqs;
1360 u16 max_irqs;
1361 u16 resv_irqs;
1362 u32 max_encap_records;
1363 u32 max_decap_records;
1364 u32 max_tx_em_flows;
1365 u32 max_tx_wm_flows;
1366 u32 max_rx_em_flows;
1367 u32 max_rx_wm_flows;
1368 };
1369
1370 #if defined(CONFIG_BNXT_SRIOV)
1371 struct bnxt_vf_info {
1372 u16 fw_fid;
1373 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1374 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1375 * stored by PF.
1376 */
1377 u16 vlan;
1378 u16 func_qcfg_flags;
1379 u32 flags;
1380 #define BNXT_VF_SPOOFCHK 0x2
1381 #define BNXT_VF_LINK_FORCED 0x4
1382 #define BNXT_VF_LINK_UP 0x8
1383 #define BNXT_VF_TRUST 0x10
1384 u32 min_tx_rate;
1385 u32 max_tx_rate;
1386 void *hwrm_cmd_req_addr;
1387 dma_addr_t hwrm_cmd_req_dma_addr;
1388 };
1389 #endif
1390
1391 struct bnxt_pf_info {
1392 #define BNXT_FIRST_PF_FID 1
1393 #define BNXT_FIRST_VF_FID 128
1394 u16 fw_fid;
1395 u16 port_id;
1396 u8 mac_addr[ETH_ALEN];
1397 u32 first_vf_id;
1398 u16 active_vfs;
1399 u16 registered_vfs;
1400 u16 max_vfs;
1401 unsigned long *vf_event_bmap;
1402 u16 hwrm_cmd_req_pages;
1403 u8 vf_resv_strategy;
1404 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1405 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1406 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1407 void *hwrm_cmd_req_addr[4];
1408 dma_addr_t hwrm_cmd_req_dma_addr[4];
1409 struct bnxt_vf_info *vf;
1410 };
1411
1412 struct bnxt_filter_base {
1413 struct hlist_node hash;
1414 struct list_head list;
1415 __le64 filter_id;
1416 u8 type;
1417 #define BNXT_FLTR_TYPE_NTUPLE 1
1418 #define BNXT_FLTR_TYPE_L2 2
1419 u8 flags;
1420 #define BNXT_ACT_DROP 1
1421 #define BNXT_ACT_RING_DST 2
1422 #define BNXT_ACT_FUNC_DST 4
1423 #define BNXT_ACT_NO_AGING 8
1424 #define BNXT_ACT_RSS_CTX 0x10
1425 u16 sw_id;
1426 u16 rxq;
1427 u16 fw_vnic_id;
1428 u16 vf_idx;
1429 unsigned long state;
1430 #define BNXT_FLTR_VALID 0
1431 #define BNXT_FLTR_INSERTED 1
1432 #define BNXT_FLTR_FW_DELETED 2
1433
1434 struct rcu_head rcu;
1435 };
1436
1437 struct bnxt_flow_masks {
1438 struct flow_dissector_key_ports ports;
1439 struct flow_dissector_key_addrs addrs;
1440 };
1441
1442 extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE;
1443 extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL;
1444 extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL;
1445
1446 struct bnxt_ntuple_filter {
1447 /* base filter must be the first member */
1448 struct bnxt_filter_base base;
1449 struct flow_keys fkeys;
1450 struct bnxt_flow_masks fmasks;
1451 struct bnxt_l2_filter *l2_fltr;
1452 u32 flow_id;
1453 };
1454
1455 struct bnxt_l2_key {
1456 union {
1457 struct {
1458 u8 dst_mac_addr[ETH_ALEN];
1459 u16 vlan;
1460 };
1461 u32 filter_key;
1462 };
1463 };
1464
1465 struct bnxt_ipv4_tuple {
1466 struct flow_dissector_key_ipv4_addrs v4addrs;
1467 struct flow_dissector_key_ports ports;
1468 };
1469
1470 struct bnxt_ipv6_tuple {
1471 struct flow_dissector_key_ipv6_addrs v6addrs;
1472 struct flow_dissector_key_ports ports;
1473 };
1474
1475 #define BNXT_L2_KEY_SIZE (sizeof(struct bnxt_l2_key) / 4)
1476
1477 struct bnxt_l2_filter {
1478 /* base filter must be the first member */
1479 struct bnxt_filter_base base;
1480 struct bnxt_l2_key l2_key;
1481 atomic_t refcnt;
1482 };
1483
1484 /* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes. The
1485 * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h.
1486 * The last valid byte in the compat version is different.
1487 */
1488 struct hwrm_port_phy_qcfg_output_compat {
1489 __le16 error_code;
1490 __le16 req_type;
1491 __le16 seq_id;
1492 __le16 resp_len;
1493 u8 link;
1494 u8 active_fec_signal_mode;
1495 __le16 link_speed;
1496 u8 duplex_cfg;
1497 u8 pause;
1498 __le16 support_speeds;
1499 __le16 force_link_speed;
1500 u8 auto_mode;
1501 u8 auto_pause;
1502 __le16 auto_link_speed;
1503 __le16 auto_link_speed_mask;
1504 u8 wirespeed;
1505 u8 lpbk;
1506 u8 force_pause;
1507 u8 module_status;
1508 __le32 preemphasis;
1509 u8 phy_maj;
1510 u8 phy_min;
1511 u8 phy_bld;
1512 u8 phy_type;
1513 u8 media_type;
1514 u8 xcvr_pkg_type;
1515 u8 eee_config_phy_addr;
1516 u8 parallel_detect;
1517 __le16 link_partner_adv_speeds;
1518 u8 link_partner_adv_auto_mode;
1519 u8 link_partner_adv_pause;
1520 __le16 adv_eee_link_speed_mask;
1521 __le16 link_partner_adv_eee_link_speed_mask;
1522 __le32 xcvr_identifier_type_tx_lpi_timer;
1523 __le16 fec_cfg;
1524 u8 duplex_state;
1525 u8 option_flags;
1526 char phy_vendor_name[16];
1527 char phy_vendor_partnumber[16];
1528 __le16 support_pam4_speeds;
1529 __le16 force_pam4_link_speed;
1530 __le16 auto_pam4_link_speed_mask;
1531 u8 link_partner_pam4_adv_speeds;
1532 u8 valid;
1533 };
1534
1535 struct bnxt_link_info {
1536 u8 phy_type;
1537 u8 media_type;
1538 u8 transceiver;
1539 u8 phy_addr;
1540 u8 phy_link_status;
1541 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1542 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1543 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1544 u8 wire_speed;
1545 u8 phy_state;
1546 #define BNXT_PHY_STATE_ENABLED 0
1547 #define BNXT_PHY_STATE_DISABLED 1
1548
1549 u8 link_state;
1550 #define BNXT_LINK_STATE_UNKNOWN 0
1551 #define BNXT_LINK_STATE_DOWN 1
1552 #define BNXT_LINK_STATE_UP 2
1553 #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1554 u8 active_lanes;
1555 u8 duplex;
1556 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1557 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1558 u8 pause;
1559 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1560 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1561 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1562 PORT_PHY_QCFG_RESP_PAUSE_TX)
1563 u8 lp_pause;
1564 u8 auto_pause_setting;
1565 u8 force_pause_setting;
1566 u8 duplex_setting;
1567 u8 auto_mode;
1568 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1569 (mode) <= BNXT_LINK_AUTO_MSK)
1570 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1571 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1572 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1573 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1574 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1575 #define PHY_VER_LEN 3
1576 u8 phy_ver[PHY_VER_LEN];
1577 u16 link_speed;
1578 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1579 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1580 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1581 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1582 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1583 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1584 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1585 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1586 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1587 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1588 #define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
1589 #define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB
1590 u16 support_speeds;
1591 u16 support_pam4_speeds;
1592 u16 support_speeds2;
1593
1594 u16 auto_link_speeds; /* fw adv setting */
1595 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1596 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1597 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1598 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1599 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1600 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1601 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1602 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1603 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1604 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1605 u16 auto_pam4_link_speeds;
1606 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1607 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1608 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1609 u16 auto_link_speeds2;
1610 #define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB
1611 #define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB
1612 #define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB
1613 #define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB
1614 #define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB
1615 #define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB
1616 #define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \
1617 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56
1618 #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \
1619 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56
1620 #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \
1621 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56
1622 #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \
1623 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56
1624 #define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \
1625 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112
1626 #define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \
1627 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112
1628 #define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \
1629 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112
1630
1631 u16 support_auto_speeds;
1632 u16 support_pam4_auto_speeds;
1633 u16 support_auto_speeds2;
1634
1635 u16 lp_auto_link_speeds;
1636 u16 lp_auto_pam4_link_speeds;
1637 u16 force_link_speed;
1638 u16 force_pam4_link_speed;
1639 u16 force_link_speed2;
1640 #define BNXT_LINK_SPEED_50GB_PAM4 \
1641 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
1642 #define BNXT_LINK_SPEED_100GB_PAM4 \
1643 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
1644 #define BNXT_LINK_SPEED_200GB_PAM4 \
1645 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
1646 #define BNXT_LINK_SPEED_400GB_PAM4 \
1647 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
1648 #define BNXT_LINK_SPEED_100GB_PAM4_112 \
1649 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
1650 #define BNXT_LINK_SPEED_200GB_PAM4_112 \
1651 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
1652 #define BNXT_LINK_SPEED_400GB_PAM4_112 \
1653 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
1654
1655 u32 preemphasis;
1656 u8 module_status;
1657 u8 active_fec_sig_mode;
1658 u16 fec_cfg;
1659 #define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1660 #define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1661 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1662 #define BNXT_FEC_ENC_BASE_R_CAP \
1663 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1664 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1665 #define BNXT_FEC_ENC_RS_CAP \
1666 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1667 #define BNXT_FEC_ENC_LLRS_CAP \
1668 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
1669 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1670 #define BNXT_FEC_ENC_RS \
1671 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
1672 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
1673 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1674 #define BNXT_FEC_ENC_LLRS \
1675 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
1676 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1677
1678 /* copy of requested setting from ethtool cmd */
1679 u8 autoneg;
1680 #define BNXT_AUTONEG_SPEED 1
1681 #define BNXT_AUTONEG_FLOW_CTRL 2
1682 u8 req_signal_mode;
1683 #define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1684 #define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1685 #define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112
1686 #define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)
1687 u8 req_duplex;
1688 u8 req_flow_ctrl;
1689 u16 req_link_speed;
1690 u16 advertising; /* user adv setting */
1691 u16 advertising_pam4;
1692 bool force_link_chng;
1693
1694 bool phy_retry;
1695 unsigned long phy_retry_expires;
1696
1697 /* a copy of phy_qcfg output used to report link
1698 * info to VF
1699 */
1700 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1701 };
1702
1703 #define BNXT_FEC_RS544_ON \
1704 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
1705 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1706
1707 #define BNXT_FEC_RS544_OFF \
1708 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
1709 PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1710
1711 #define BNXT_FEC_RS272_ON \
1712 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
1713 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1714
1715 #define BNXT_FEC_RS272_OFF \
1716 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
1717 PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1718
1719 #define BNXT_PAM4_SUPPORTED(link_info) \
1720 ((link_info)->support_pam4_speeds)
1721
1722 #define BNXT_FEC_RS_ON(link_info) \
1723 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1724 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1725 (BNXT_PAM4_SUPPORTED(link_info) ? \
1726 (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1727
1728 #define BNXT_FEC_LLRS_ON \
1729 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
1730 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1731 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1732
1733 #define BNXT_FEC_RS_OFF(link_info) \
1734 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
1735 (BNXT_PAM4_SUPPORTED(link_info) ? \
1736 (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1737
1738 #define BNXT_FEC_BASE_R_ON(link_info) \
1739 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
1740 BNXT_FEC_RS_OFF(link_info))
1741
1742 #define BNXT_FEC_ALL_OFF(link_info) \
1743 (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
1744 BNXT_FEC_RS_OFF(link_info))
1745
1746 struct bnxt_queue_info {
1747 u8 queue_id;
1748 u8 queue_profile;
1749 };
1750
1751 #define BNXT_MAX_LED 4
1752
1753 struct bnxt_led_info {
1754 u8 led_id;
1755 u8 led_type;
1756 u8 led_group_id;
1757 u8 unused;
1758 __le16 led_state_caps;
1759 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1760 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1761
1762 __le16 led_color_caps;
1763 };
1764
1765 #define BNXT_MAX_TEST 8
1766
1767 struct bnxt_test_info {
1768 u8 offline_mask;
1769 u16 timeout;
1770 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1771 };
1772
1773 #define CHIMP_REG_VIEW_ADDR \
1774 ((bp->flags & BNXT_FLAG_CHIP_P5_PLUS) ? 0x80000000 : 0xb1000000)
1775
1776 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1777 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1778 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1779
1780 #define BNXT_GRC_REG_STATUS_P5 0x520
1781
1782 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1783 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1784
1785 #define BNXT_GRC_REG_CHIP_NUM 0x48
1786 #define BNXT_GRC_REG_BASE 0x260000
1787
1788 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
1789 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
1790
1791 #define BNXT_GRC_BASE_MASK 0xfffff000
1792 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1793
1794 struct bnxt_tc_flow_stats {
1795 u64 packets;
1796 u64 bytes;
1797 };
1798
1799 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1800 struct bnxt_flower_indr_block_cb_priv {
1801 struct net_device *tunnel_netdev;
1802 struct bnxt *bp;
1803 struct list_head list;
1804 };
1805 #endif
1806
1807 struct bnxt_tc_info {
1808 bool enabled;
1809
1810 /* hash table to store TC offloaded flows */
1811 struct rhashtable flow_table;
1812 struct rhashtable_params flow_ht_params;
1813
1814 /* hash table to store L2 keys of TC flows */
1815 struct rhashtable l2_table;
1816 struct rhashtable_params l2_ht_params;
1817 /* hash table to store L2 keys for TC tunnel decap */
1818 struct rhashtable decap_l2_table;
1819 struct rhashtable_params decap_l2_ht_params;
1820 /* hash table to store tunnel decap entries */
1821 struct rhashtable decap_table;
1822 struct rhashtable_params decap_ht_params;
1823 /* hash table to store tunnel encap entries */
1824 struct rhashtable encap_table;
1825 struct rhashtable_params encap_ht_params;
1826
1827 /* lock to atomically add/del an l2 node when a flow is
1828 * added or deleted.
1829 */
1830 struct mutex lock;
1831
1832 /* Fields used for batching stats query */
1833 struct rhashtable_iter iter;
1834 #define BNXT_FLOW_STATS_BATCH_MAX 10
1835 struct bnxt_tc_stats_batch {
1836 void *flow_node;
1837 struct bnxt_tc_flow_stats hw_stats;
1838 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1839
1840 /* Stat counter mask (width) */
1841 u64 bytes_mask;
1842 u64 packets_mask;
1843 };
1844
1845 struct bnxt_vf_rep_stats {
1846 u64 packets;
1847 u64 bytes;
1848 u64 dropped;
1849 };
1850
1851 struct bnxt_vf_rep {
1852 struct bnxt *bp;
1853 struct net_device *dev;
1854 struct metadata_dst *dst;
1855 u16 vf_idx;
1856 u16 tx_cfa_action;
1857 u16 rx_cfa_code;
1858
1859 struct bnxt_vf_rep_stats rx_stats;
1860 struct bnxt_vf_rep_stats tx_stats;
1861 };
1862
1863 #define PTU_PTE_VALID 0x1UL
1864 #define PTU_PTE_LAST 0x2UL
1865 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1866
1867 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1868 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1869 #define MAX_CTX_BYTES ((size_t)MAX_CTX_TOTAL_PAGES * BNXT_PAGE_SIZE)
1870 #define MAX_CTX_BYTES_MASK (MAX_CTX_BYTES - 1)
1871
1872 struct bnxt_ctx_pg_info {
1873 u32 entries;
1874 u32 nr_pages;
1875 void *ctx_pg_arr[MAX_CTX_PAGES];
1876 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1877 struct bnxt_ring_mem_info ring_mem;
1878 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1879 };
1880
1881 #define BNXT_MAX_TQM_SP_RINGS 1
1882 #define BNXT_MAX_TQM_FP_RINGS 8
1883 #define BNXT_MAX_TQM_RINGS \
1884 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1885
1886 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
1887
1888 #define BNXT_SET_CTX_PAGE_ATTR(attr) \
1889 do { \
1890 if (BNXT_PAGE_SIZE == 0x2000) \
1891 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
1892 else if (BNXT_PAGE_SIZE == 0x10000) \
1893 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
1894 else \
1895 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
1896 } while (0)
1897
1898 struct bnxt_ctx_mem_type {
1899 u16 type;
1900 u16 entry_size;
1901 u32 flags;
1902 #define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
1903 #define BNXT_CTX_MEM_FW_TRACE \
1904 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE
1905 #define BNXT_CTX_MEM_FW_BIN_TRACE \
1906 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE
1907 #define BNXT_CTX_MEM_PERSIST \
1908 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET
1909
1910 u32 instance_bmap;
1911 u8 init_value;
1912 u8 entry_multiple;
1913 u16 init_offset;
1914 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
1915 u32 max_entries;
1916 u32 min_entries;
1917 u8 last:1;
1918 u8 mem_valid:1;
1919 u8 split_entry_cnt;
1920 #define BNXT_MAX_SPLIT_ENTRY 4
1921 union {
1922 struct {
1923 u32 qp_l2_entries;
1924 u32 qp_qp1_entries;
1925 u32 qp_fast_qpmd_entries;
1926 };
1927 u32 srq_l2_entries;
1928 u32 cq_l2_entries;
1929 u32 vnic_entries;
1930 struct {
1931 u32 mrav_av_entries;
1932 u32 mrav_num_entries_units;
1933 };
1934 u32 split[BNXT_MAX_SPLIT_ENTRY];
1935 };
1936 struct bnxt_ctx_pg_info *pg_info;
1937 };
1938
1939 #define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0
1940
1941 #define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
1942 #define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
1943 #define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
1944 #define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
1945 #define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
1946 #define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
1947 #define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
1948 #define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
1949 #define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
1950 #define BNXT_CTX_TCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK
1951 #define BNXT_CTX_RCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK
1952 #define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
1953 #define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
1954 #define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
1955 #define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
1956 #define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
1957 #define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE
1958 #define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION
1959 #define BNXT_CTX_SRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE
1960 #define BNXT_CTX_SRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE
1961 #define BNXT_CTX_CRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE
1962 #define BNXT_CTX_CRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE
1963 #define BNXT_CTX_RIGP0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE
1964 #define BNXT_CTX_L2HWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE
1965 #define BNXT_CTX_REHWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE
1966 #define BNXT_CTX_CA0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE
1967 #define BNXT_CTX_CA1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE
1968 #define BNXT_CTX_CA2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE
1969 #define BNXT_CTX_RIGP1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE
1970
1971 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
1972 #define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)
1973 #define BNXT_CTX_V2_MAX (BNXT_CTX_RIGP1 + 1)
1974 #define BNXT_CTX_INV ((u16)-1)
1975
1976 struct bnxt_ctx_mem_info {
1977 u8 tqm_fp_rings_count;
1978
1979 u32 flags;
1980 #define BNXT_CTX_FLAG_INITED 0x01
1981 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];
1982 };
1983
1984 enum bnxt_health_severity {
1985 SEVERITY_NORMAL = 0,
1986 SEVERITY_WARNING,
1987 SEVERITY_RECOVERABLE,
1988 SEVERITY_FATAL,
1989 };
1990
1991 enum bnxt_health_remedy {
1992 REMEDY_DEVLINK_RECOVER,
1993 REMEDY_POWER_CYCLE_DEVICE,
1994 REMEDY_POWER_CYCLE_HOST,
1995 REMEDY_FW_UPDATE,
1996 REMEDY_HW_REPLACE,
1997 };
1998
1999 struct bnxt_fw_health {
2000 u32 flags;
2001 u32 polling_dsecs;
2002 u32 master_func_wait_dsecs;
2003 u32 normal_func_wait_dsecs;
2004 u32 post_reset_wait_dsecs;
2005 u32 post_reset_max_wait_dsecs;
2006 u32 regs[4];
2007 u32 mapped_regs[4];
2008 #define BNXT_FW_HEALTH_REG 0
2009 #define BNXT_FW_HEARTBEAT_REG 1
2010 #define BNXT_FW_RESET_CNT_REG 2
2011 #define BNXT_FW_RESET_INPROG_REG 3
2012 u32 fw_reset_inprog_reg_mask;
2013 u32 last_fw_heartbeat;
2014 u32 last_fw_reset_cnt;
2015 u8 enabled:1;
2016 u8 primary:1;
2017 u8 status_reliable:1;
2018 u8 resets_reliable:1;
2019 u8 tmr_multiplier;
2020 u8 tmr_counter;
2021 u8 fw_reset_seq_cnt;
2022 u32 fw_reset_seq_regs[16];
2023 u32 fw_reset_seq_vals[16];
2024 u32 fw_reset_seq_delay_msec[16];
2025 u32 echo_req_data1;
2026 u32 echo_req_data2;
2027 struct devlink_health_reporter *fw_reporter;
2028 /* Protects severity and remedy */
2029 struct mutex lock;
2030 enum bnxt_health_severity severity;
2031 enum bnxt_health_remedy remedy;
2032 u32 arrests;
2033 u32 discoveries;
2034 u32 survivals;
2035 u32 fatalities;
2036 u32 diagnoses;
2037 };
2038
2039 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
2040 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
2041 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
2042 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
2043 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
2044
2045 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
2046 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
2047
2048 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
2049 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
2050
2051 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
2052 ((reg) & BNXT_GRC_OFFSET_MASK))
2053
2054 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff
2055 #define BNXT_FW_STATUS_HEALTHY 0x8000
2056 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
2057 #define BNXT_FW_STATUS_RECOVERING 0x400000
2058
2059 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
2060 BNXT_FW_STATUS_HEALTHY)
2061
2062 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
2063 BNXT_FW_STATUS_HEALTHY)
2064
2065 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
2066 BNXT_FW_STATUS_HEALTHY)
2067
2068 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
2069 ((sts) & BNXT_FW_STATUS_RECOVERING))
2070
2071 #define BNXT_FW_RETRY 5
2072 #define BNXT_FW_IF_RETRY 10
2073 #define BNXT_FW_SLOT_RESET_RETRY 4
2074
2075 struct bnxt_aux_priv {
2076 struct auxiliary_device aux_dev;
2077 struct bnxt_en_dev *edev;
2078 int id;
2079 };
2080
2081 enum board_idx {
2082 BCM57301,
2083 BCM57302,
2084 BCM57304,
2085 BCM57417_NPAR,
2086 BCM58700,
2087 BCM57311,
2088 BCM57312,
2089 BCM57402,
2090 BCM57404,
2091 BCM57406,
2092 BCM57402_NPAR,
2093 BCM57407,
2094 BCM57412,
2095 BCM57414,
2096 BCM57416,
2097 BCM57417,
2098 BCM57412_NPAR,
2099 BCM57314,
2100 BCM57417_SFP,
2101 BCM57416_SFP,
2102 BCM57404_NPAR,
2103 BCM57406_NPAR,
2104 BCM57407_SFP,
2105 BCM57407_NPAR,
2106 BCM57414_NPAR,
2107 BCM57416_NPAR,
2108 BCM57452,
2109 BCM57454,
2110 BCM5745x_NPAR,
2111 BCM57508,
2112 BCM57504,
2113 BCM57502,
2114 BCM57508_NPAR,
2115 BCM57504_NPAR,
2116 BCM57502_NPAR,
2117 BCM57608,
2118 BCM57604,
2119 BCM57602,
2120 BCM57601,
2121 BCM58802,
2122 BCM58804,
2123 BCM58808,
2124 NETXTREME_E_VF,
2125 NETXTREME_C_VF,
2126 NETXTREME_S_VF,
2127 NETXTREME_C_VF_HV,
2128 NETXTREME_E_VF_HV,
2129 NETXTREME_E_P5_VF,
2130 NETXTREME_E_P5_VF_HV,
2131 NETXTREME_E_P7_VF,
2132 };
2133
2134 #define BNXT_TRACE_BUF_MAGIC_BYTE ((u8)0xbc)
2135 #define BNXT_TRACE_MAX 11
2136
2137 struct bnxt_bs_trace_info {
2138 u8 *magic_byte;
2139 u32 last_offset;
2140 u8 wrapped:1;
2141 u16 ctx_type;
2142 u16 trace_type;
2143 };
2144
bnxt_bs_trace_check_wrap(struct bnxt_bs_trace_info * bs_trace,u32 offset)2145 static inline void bnxt_bs_trace_check_wrap(struct bnxt_bs_trace_info *bs_trace,
2146 u32 offset)
2147 {
2148 if (!bs_trace->wrapped &&
2149 *bs_trace->magic_byte != BNXT_TRACE_BUF_MAGIC_BYTE)
2150 bs_trace->wrapped = 1;
2151 bs_trace->last_offset = offset;
2152 }
2153
2154 struct bnxt {
2155 void __iomem *bar0;
2156 void __iomem *bar1;
2157 void __iomem *bar2;
2158
2159 u32 reg_base;
2160 u16 chip_num;
2161 #define CHIP_NUM_57301 0x16c8
2162 #define CHIP_NUM_57302 0x16c9
2163 #define CHIP_NUM_57304 0x16ca
2164 #define CHIP_NUM_58700 0x16cd
2165 #define CHIP_NUM_57402 0x16d0
2166 #define CHIP_NUM_57404 0x16d1
2167 #define CHIP_NUM_57406 0x16d2
2168 #define CHIP_NUM_57407 0x16d5
2169
2170 #define CHIP_NUM_57311 0x16ce
2171 #define CHIP_NUM_57312 0x16cf
2172 #define CHIP_NUM_57314 0x16df
2173 #define CHIP_NUM_57317 0x16e0
2174 #define CHIP_NUM_57412 0x16d6
2175 #define CHIP_NUM_57414 0x16d7
2176 #define CHIP_NUM_57416 0x16d8
2177 #define CHIP_NUM_57417 0x16d9
2178 #define CHIP_NUM_57412L 0x16da
2179 #define CHIP_NUM_57414L 0x16db
2180
2181 #define CHIP_NUM_5745X 0xd730
2182 #define CHIP_NUM_57452 0xc452
2183 #define CHIP_NUM_57454 0xc454
2184
2185 #define CHIP_NUM_57508 0x1750
2186 #define CHIP_NUM_57504 0x1751
2187 #define CHIP_NUM_57502 0x1752
2188
2189 #define CHIP_NUM_57608 0x1760
2190
2191 #define CHIP_NUM_58802 0xd802
2192 #define CHIP_NUM_58804 0xd804
2193 #define CHIP_NUM_58808 0xd808
2194
2195 u8 chip_rev;
2196
2197 #define BNXT_CHIP_NUM_5730X(chip_num) \
2198 ((chip_num) >= CHIP_NUM_57301 && \
2199 (chip_num) <= CHIP_NUM_57304)
2200
2201 #define BNXT_CHIP_NUM_5740X(chip_num) \
2202 (((chip_num) >= CHIP_NUM_57402 && \
2203 (chip_num) <= CHIP_NUM_57406) || \
2204 (chip_num) == CHIP_NUM_57407)
2205
2206 #define BNXT_CHIP_NUM_5731X(chip_num) \
2207 ((chip_num) == CHIP_NUM_57311 || \
2208 (chip_num) == CHIP_NUM_57312 || \
2209 (chip_num) == CHIP_NUM_57314 || \
2210 (chip_num) == CHIP_NUM_57317)
2211
2212 #define BNXT_CHIP_NUM_5741X(chip_num) \
2213 ((chip_num) >= CHIP_NUM_57412 && \
2214 (chip_num) <= CHIP_NUM_57414L)
2215
2216 #define BNXT_CHIP_NUM_58700(chip_num) \
2217 ((chip_num) == CHIP_NUM_58700)
2218
2219 #define BNXT_CHIP_NUM_5745X(chip_num) \
2220 ((chip_num) == CHIP_NUM_5745X || \
2221 (chip_num) == CHIP_NUM_57452 || \
2222 (chip_num) == CHIP_NUM_57454)
2223
2224
2225 #define BNXT_CHIP_NUM_57X0X(chip_num) \
2226 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
2227
2228 #define BNXT_CHIP_NUM_57X1X(chip_num) \
2229 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
2230
2231 #define BNXT_CHIP_NUM_588XX(chip_num) \
2232 ((chip_num) == CHIP_NUM_58802 || \
2233 (chip_num) == CHIP_NUM_58804 || \
2234 (chip_num) == CHIP_NUM_58808)
2235
2236 #define BNXT_VPD_FLD_LEN 32
2237 char board_partno[BNXT_VPD_FLD_LEN];
2238 char board_serialno[BNXT_VPD_FLD_LEN];
2239
2240 struct net_device *dev;
2241 struct pci_dev *pdev;
2242
2243 atomic_t intr_sem;
2244
2245 u32 flags;
2246 #define BNXT_FLAG_CHIP_P5_PLUS 0x1
2247 #define BNXT_FLAG_VF 0x2
2248 #define BNXT_FLAG_LRO 0x4
2249 #ifdef CONFIG_INET
2250 #define BNXT_FLAG_GRO 0x8
2251 #else
2252 /* Cannot support hardware GRO if CONFIG_INET is not set */
2253 #define BNXT_FLAG_GRO 0x0
2254 #endif
2255 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
2256 #define BNXT_FLAG_JUMBO 0x10
2257 #define BNXT_FLAG_STRIP_VLAN 0x20
2258 #define BNXT_FLAG_RFS 0x100
2259 #define BNXT_FLAG_SHARED_RINGS 0x200
2260 #define BNXT_FLAG_PORT_STATS 0x400
2261 #define BNXT_FLAG_WOL_CAP 0x4000
2262 #define BNXT_FLAG_ROCEV1_CAP 0x8000
2263 #define BNXT_FLAG_ROCEV2_CAP 0x10000
2264 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
2265 BNXT_FLAG_ROCEV2_CAP)
2266 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
2267 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
2268 #define BNXT_FLAG_CHIP_P7 0x80000
2269 #define BNXT_FLAG_MULTI_HOST 0x100000
2270 #define BNXT_FLAG_DSN_VALID 0x200000
2271 #define BNXT_FLAG_DOUBLE_DB 0x400000
2272 #define BNXT_FLAG_UDP_GSO_CAP 0x800000
2273 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
2274 #define BNXT_FLAG_DIM 0x2000000
2275 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
2276 #define BNXT_FLAG_TX_COAL_CMPL 0x8000000
2277 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
2278 #define BNXT_FLAG_HDS 0x20000000
2279 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
2280 BNXT_FLAG_LRO | BNXT_FLAG_HDS)
2281
2282 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
2283 BNXT_FLAG_RFS | \
2284 BNXT_FLAG_STRIP_VLAN)
2285
2286 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
2287 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
2288 #ifdef CONFIG_BNXT_SRIOV
2289 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->vf.flags & BNXT_VF_TRUST)
2290 #else
2291 #define BNXT_VF_IS_TRUSTED(bp) 0
2292 #endif
2293 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
2294 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
2295 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
2296 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) && \
2297 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
2298 #define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
2299 BNXT_SH_PORT_CFG_OK(bp)) && \
2300 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
2301 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
2302 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
2303 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
2304 (!((bp)->flags & BNXT_FLAG_CHIP_P5_PLUS) ||\
2305 (bp)->max_tpa_v2) && !is_kdump_kernel())
2306 #define BNXT_RX_JUMBO_MODE(bp) ((bp)->flags & BNXT_FLAG_JUMBO)
2307
2308 #define BNXT_CHIP_P7(bp) \
2309 ((bp)->chip_num == CHIP_NUM_57608)
2310
2311 #define BNXT_CHIP_P5(bp) \
2312 ((bp)->chip_num == CHIP_NUM_57508 || \
2313 (bp)->chip_num == CHIP_NUM_57504 || \
2314 (bp)->chip_num == CHIP_NUM_57502)
2315
2316 /* Chip class phase 5 */
2317 #define BNXT_CHIP_P5_PLUS(bp) \
2318 (BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp))
2319
2320 /* Chip class phase 4.x */
2321 #define BNXT_CHIP_P4(bp) \
2322 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
2323 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
2324 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
2325 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
2326 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
2327
2328 /* Chip class phase 3.x */
2329 #define BNXT_CHIP_P3(bp) \
2330 (BNXT_CHIP_NUM_57X0X((bp)->chip_num) || \
2331 BNXT_CHIP_TYPE_NITRO_A0(bp))
2332
2333 #define BNXT_CHIP_P4_PLUS(bp) \
2334 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))
2335
2336 #define BNXT_CHIP_P5_AND_MINUS(bp) \
2337 (BNXT_CHIP_P3(bp) || BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
2338
2339 struct bnxt_aux_priv *aux_priv;
2340 struct bnxt_en_dev *edev;
2341
2342 struct bnxt_napi **bnapi;
2343
2344 struct bnxt_rx_ring_info *rx_ring;
2345 struct bnxt_tx_ring_info *tx_ring;
2346 u16 *tx_ring_map;
2347
2348 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
2349 struct sk_buff *);
2350
2351 struct sk_buff * (*rx_skb_func)(struct bnxt *,
2352 struct bnxt_rx_ring_info *,
2353 u16, void *, u8 *, dma_addr_t,
2354 unsigned int);
2355
2356 u16 max_tpa_v2;
2357 u16 max_tpa;
2358 u32 rx_buf_size;
2359 u32 rx_buf_use_size; /* useable size */
2360 u16 rx_offset;
2361 u16 rx_dma_offset;
2362 enum dma_data_direction rx_dir;
2363 u32 rx_ring_size;
2364 u32 rx_agg_ring_size;
2365 u32 rx_copybreak;
2366 u32 rx_ring_mask;
2367 u32 rx_agg_ring_mask;
2368 int rx_nr_pages;
2369 int rx_agg_nr_pages;
2370 int rx_nr_rings;
2371 int rsscos_nr_ctxs;
2372
2373 u32 tx_ring_size;
2374 u32 tx_ring_mask;
2375 int tx_nr_pages;
2376 int tx_nr_rings;
2377 int tx_nr_rings_per_tc;
2378 int tx_nr_rings_xdp;
2379
2380 int tx_wake_thresh;
2381 int tx_push_thresh;
2382 int tx_push_size;
2383
2384 u32 cp_ring_size;
2385 u32 cp_ring_mask;
2386 u32 cp_bit;
2387 int cp_nr_pages;
2388 int cp_nr_rings;
2389
2390 /* grp_info indexed by completion ring index */
2391 struct bnxt_ring_grp_info *grp_info;
2392 struct bnxt_vnic_info *vnic_info;
2393 u32 num_rss_ctx;
2394 int nr_vnics;
2395 u32 *rss_indir_tbl;
2396 u16 rss_indir_tbl_entries;
2397 u32 rss_hash_cfg;
2398 u32 rss_hash_delta;
2399 u32 rss_cap;
2400 #define BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA BIT(0)
2401 #define BNXT_RSS_CAP_UDP_RSS_CAP BIT(1)
2402 #define BNXT_RSS_CAP_NEW_RSS_CAP BIT(2)
2403 #define BNXT_RSS_CAP_RSS_TCAM BIT(3)
2404 #define BNXT_RSS_CAP_AH_V4_RSS_CAP BIT(4)
2405 #define BNXT_RSS_CAP_AH_V6_RSS_CAP BIT(5)
2406 #define BNXT_RSS_CAP_ESP_V4_RSS_CAP BIT(6)
2407 #define BNXT_RSS_CAP_ESP_V6_RSS_CAP BIT(7)
2408 #define BNXT_RSS_CAP_MULTI_RSS_CTX BIT(8)
2409
2410 u8 rss_hash_key[HW_HASH_KEY_SIZE];
2411 u8 rss_hash_key_valid:1;
2412 u8 rss_hash_key_updated:1;
2413
2414 u16 max_mtu;
2415 u16 tso_max_segs;
2416 u8 max_tc;
2417 u8 max_lltc; /* lossless TCs */
2418 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
2419 u8 tc_to_qidx[BNXT_MAX_QUEUE];
2420 u8 q_ids[BNXT_MAX_QUEUE];
2421 u8 max_q;
2422 u8 num_tc;
2423
2424 u8 tph_mode;
2425
2426 unsigned int current_interval;
2427 #define BNXT_TIMER_INTERVAL HZ
2428
2429 struct timer_list timer;
2430
2431 unsigned long state;
2432 #define BNXT_STATE_OPEN 0
2433 #define BNXT_STATE_IN_SP_TASK 1
2434 #define BNXT_STATE_READ_STATS 2
2435 #define BNXT_STATE_FW_RESET_DET 3
2436 #define BNXT_STATE_IN_FW_RESET 4
2437 #define BNXT_STATE_ABORT_ERR 5
2438 #define BNXT_STATE_FW_FATAL_COND 6
2439 #define BNXT_STATE_DRV_REGISTERED 7
2440 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
2441 #define BNXT_STATE_NAPI_DISABLED 9
2442 #define BNXT_STATE_L2_FILTER_RETRY 10
2443 #define BNXT_STATE_FW_ACTIVATE 11
2444 #define BNXT_STATE_RECOVER 12
2445 #define BNXT_STATE_FW_NON_FATAL_COND 13
2446 #define BNXT_STATE_FW_ACTIVATE_RESET 14
2447 #define BNXT_STATE_HALF_OPEN 15 /* For offline ethtool tests */
2448
2449 #define BNXT_NO_FW_ACCESS(bp) \
2450 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
2451 pci_channel_offline((bp)->pdev))
2452
2453 struct bnxt_irq *irq_tbl;
2454 int total_irqs;
2455 int ulp_num_msix_want;
2456 u8 mac_addr[ETH_ALEN];
2457
2458 #ifdef CONFIG_BNXT_DCB
2459 struct ieee_pfc *ieee_pfc;
2460 struct ieee_ets *ieee_ets;
2461 u8 dcbx_cap;
2462 u8 default_pri;
2463 u8 max_dscp_value;
2464 #endif /* CONFIG_BNXT_DCB */
2465
2466 u32 msg_enable;
2467
2468 u64 fw_cap;
2469 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
2470 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
2471 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
2472 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
2473 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
2474 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(5)
2475 #define BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED BIT_ULL(6)
2476 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
2477 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
2478 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
2479 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
2480 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
2481 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
2482 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
2483 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
2484 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
2485 #define BNXT_FW_CAP_TX_TS_CMP BIT_ULL(19)
2486 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
2487 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
2488 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(22)
2489 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(23)
2490 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
2491 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
2492 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
2493 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(27)
2494 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(28)
2495 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(29)
2496 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
2497 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(31)
2498 #define BNXT_FW_CAP_PTP BIT_ULL(32)
2499 #define BNXT_FW_CAP_THRESHOLD_TEMP_SUPPORTED BIT_ULL(33)
2500 #define BNXT_FW_CAP_DFLT_VLAN_TPID_PCP BIT_ULL(34)
2501 #define BNXT_FW_CAP_PRE_RESV_VNICS BIT_ULL(35)
2502 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(36)
2503 #define BNXT_FW_CAP_VNIC_TUNNEL_TPA BIT_ULL(37)
2504 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(38)
2505 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 BIT_ULL(39)
2506 #define BNXT_FW_CAP_VNIC_RE_FLUSH BIT_ULL(40)
2507 #define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(41)
2508 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(42)
2509
2510 u32 fw_dbg_cap;
2511
2512 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
2513 #define BNXT_PTP_USE_RTC(bp) (!BNXT_MH(bp) && \
2514 ((bp)->fw_cap & BNXT_FW_CAP_PTP_RTC))
2515 #define BNXT_SUPPORTS_NTUPLE_VNIC(bp) \
2516 (BNXT_PF(bp) && ((bp)->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V3))
2517
2518 #define BNXT_SUPPORTS_MULTI_RSS_CTX(bp) \
2519 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
2520 ((bp)->rss_cap & BNXT_RSS_CAP_MULTI_RSS_CTX))
2521 #define BNXT_SUPPORTS_QUEUE_API(bp) \
2522 (BNXT_PF(bp) && BNXT_SUPPORTS_NTUPLE_VNIC(bp) && \
2523 ((bp)->fw_cap & BNXT_FW_CAP_VNIC_RE_FLUSH))
2524 #define BNXT_RDMA_SRIOV_EN(bp) \
2525 ((bp)->fw_cap & BNXT_FW_CAP_ENABLE_RDMA_SRIOV)
2526 #define BNXT_ROCE_VF_RESC_CAP(bp) \
2527 ((bp)->fw_cap & BNXT_FW_CAP_ROCE_VF_RESC_MGMT_SUPPORTED)
2528 #define BNXT_SW_RES_LMT(bp) \
2529 ((bp)->fw_cap & BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS)
2530
2531 u32 hwrm_spec_code;
2532 u16 hwrm_cmd_seq;
2533 u16 hwrm_cmd_kong_seq;
2534 struct dma_pool *hwrm_dma_pool;
2535 struct hlist_head hwrm_pending_list;
2536
2537 struct rtnl_link_stats64 net_stats_prev;
2538 struct bnxt_stats_mem port_stats;
2539 struct bnxt_stats_mem rx_port_stats_ext;
2540 struct bnxt_stats_mem tx_port_stats_ext;
2541 u16 fw_rx_stats_ext_size;
2542 u16 fw_tx_stats_ext_size;
2543 u16 hw_ring_stats_size;
2544 u8 pri2cos_idx[8];
2545 u8 pri2cos_valid;
2546
2547 struct bnxt_total_ring_err_stats ring_err_stats_prev;
2548
2549 u16 hwrm_max_req_len;
2550 u16 hwrm_max_ext_req_len;
2551 unsigned int hwrm_cmd_timeout;
2552 unsigned int hwrm_cmd_max_timeout;
2553 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
2554 struct hwrm_ver_get_output ver_resp;
2555 #define FW_VER_STR_LEN 32
2556 #define BC_HWRM_STR_LEN 21
2557 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2558 char fw_ver_str[FW_VER_STR_LEN];
2559 char hwrm_ver_supp[FW_VER_STR_LEN];
2560 char nvm_cfg_ver[FW_VER_STR_LEN];
2561 u64 fw_ver_code;
2562 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
2563 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2564 #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
2565 #define BNXT_FW_BLD(bp) (((bp)->fw_ver_code >> 16) & 0xffff)
2566
2567 u16 vxlan_fw_dst_port_id;
2568 u16 nge_fw_dst_port_id;
2569 u16 vxlan_gpe_fw_dst_port_id;
2570 __be16 vxlan_port;
2571 __be16 nge_port;
2572 __be16 vxlan_gpe_port;
2573 u8 port_partition_type;
2574 u8 port_count;
2575 u16 br_mode;
2576
2577 struct bnxt_coal_cap coal_cap;
2578 struct bnxt_coal rx_coal;
2579 struct bnxt_coal tx_coal;
2580
2581 u32 stats_coal_ticks;
2582 #define BNXT_DEF_STATS_COAL_TICKS 1000000
2583 #define BNXT_MIN_STATS_COAL_TICKS 250000
2584 #define BNXT_MAX_STATS_COAL_TICKS 1000000
2585
2586 struct work_struct sp_task;
2587 unsigned long sp_event;
2588 #define BNXT_RX_MASK_SP_EVENT 0
2589 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
2590 #define BNXT_LINK_CHNG_SP_EVENT 2
2591 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
2592 #define BNXT_RESET_TASK_SP_EVENT 6
2593 #define BNXT_RST_RING_SP_EVENT 7
2594 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
2595 #define BNXT_PERIODIC_STATS_SP_EVENT 9
2596 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
2597 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
2598 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
2599 #define BNXT_FLOW_STATS_SP_EVENT 15
2600 #define BNXT_UPDATE_PHY_SP_EVENT 16
2601 #define BNXT_RING_COAL_NOW_SP_EVENT 17
2602 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
2603 #define BNXT_FW_EXCEPTION_SP_EVENT 19
2604 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
2605 #define BNXT_THERMAL_THRESHOLD_SP_EVENT 22
2606 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
2607 #define BNXT_RESTART_ULP_SP_EVENT 24
2608
2609 struct delayed_work fw_reset_task;
2610 int fw_reset_state;
2611 #define BNXT_FW_RESET_STATE_POLL_VF 1
2612 #define BNXT_FW_RESET_STATE_RESET_FW 2
2613 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
2614 #define BNXT_FW_RESET_STATE_POLL_FW 4
2615 #define BNXT_FW_RESET_STATE_OPENING 5
2616 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
2617
2618 u16 fw_reset_min_dsecs;
2619 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
2620 u16 fw_reset_max_dsecs;
2621 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
2622 unsigned long fw_reset_timestamp;
2623
2624 struct bnxt_fw_health *fw_health;
2625
2626 struct bnxt_hw_resc hw_resc;
2627 struct bnxt_pf_info pf;
2628 struct bnxt_ctx_mem_info *ctx;
2629 #ifdef CONFIG_BNXT_SRIOV
2630 int nr_vfs;
2631 struct bnxt_vf_info vf;
2632 wait_queue_head_t sriov_cfg_wait;
2633 bool sriov_cfg;
2634 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
2635 #endif
2636
2637 #if BITS_PER_LONG == 32
2638 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2639 spinlock_t db_lock;
2640 #endif
2641 int db_offset; /* db_offset within db_size */
2642 int db_size;
2643
2644 #define BNXT_NTP_FLTR_MAX_FLTR 4096
2645 #define BNXT_MAX_FLTR (BNXT_NTP_FLTR_MAX_FLTR + BNXT_L2_FLTR_MAX_FLTR)
2646 #define BNXT_NTP_FLTR_HASH_SIZE 512
2647 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2648 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2649 spinlock_t ntp_fltr_lock; /* for hash table add, del */
2650
2651 unsigned long *ntp_fltr_bmap;
2652 int ntp_fltr_count;
2653 int max_fltr;
2654
2655 #define BNXT_L2_FLTR_MAX_FLTR 1024
2656 #define BNXT_L2_FLTR_HASH_SIZE 32
2657 #define BNXT_L2_FLTR_HASH_MASK (BNXT_L2_FLTR_HASH_SIZE - 1)
2658 struct hlist_head l2_fltr_hash_tbl[BNXT_L2_FLTR_HASH_SIZE];
2659
2660 u32 hash_seed;
2661 u64 toeplitz_prefix;
2662
2663 struct list_head usr_fltr_list;
2664
2665 /* To protect link related settings during link changes and
2666 * ethtool settings changes.
2667 */
2668 struct mutex link_lock;
2669 struct bnxt_link_info link_info;
2670 struct ethtool_keee eee;
2671 u32 lpi_tmr_lo;
2672 u32 lpi_tmr_hi;
2673
2674 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2675 u32 phy_flags;
2676 #define BNXT_PHY_FL_EEE_CAP PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2677 #define BNXT_PHY_FL_EXT_LPBK PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2678 #define BNXT_PHY_FL_AN_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2679 #define BNXT_PHY_FL_SHARED_PORT_CFG PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2680 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2681 #define BNXT_PHY_FL_NO_PHY_LPBK PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2682 #define BNXT_PHY_FL_FW_MANAGED_LKDN PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2683 #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2684 #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2685 #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2686 #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8)
2687 #define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8)
2688
2689 /* copied from flags in hwrm_port_mac_qcaps_output */
2690 u8 mac_flags;
2691 #define BNXT_MAC_FL_NO_MAC_LPBK \
2692 PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2693
2694 u8 num_tests;
2695 struct bnxt_test_info *test_info;
2696
2697 u8 wol_filter_id;
2698 u8 wol;
2699
2700 u8 num_leds;
2701 struct bnxt_led_info leds[BNXT_MAX_LED];
2702 u16 dump_flag;
2703 #define BNXT_DUMP_LIVE 0
2704 #define BNXT_DUMP_CRASH 1
2705 #define BNXT_DUMP_DRIVER 2
2706 #define BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE 3
2707
2708 struct bpf_prog *xdp_prog;
2709
2710 struct bnxt_ptp_cfg *ptp_cfg;
2711 u8 ptp_all_rx_tstamp;
2712
2713 /* devlink interface and vf-rep structs */
2714 struct devlink *dl;
2715 struct devlink_port dl_port;
2716 enum devlink_eswitch_mode eswitch_mode;
2717 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
2718 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
2719 u8 dsn[8];
2720 struct bnxt_tc_info *tc_info;
2721 struct list_head tc_indr_block_list;
2722 struct dentry *debugfs_pdev;
2723 #ifdef CONFIG_BNXT_HWMON
2724 struct device *hwmon_dev;
2725 u8 warn_thresh_temp;
2726 u8 crit_thresh_temp;
2727 u8 fatal_thresh_temp;
2728 u8 shutdown_thresh_temp;
2729 #endif
2730 u32 thermal_threshold_type;
2731 enum board_idx board_idx;
2732
2733 struct bnxt_ctx_pg_info *fw_crash_mem;
2734 u32 fw_crash_len;
2735 struct bnxt_bs_trace_info bs_trace[BNXT_TRACE_MAX];
2736 };
2737
2738 #define BNXT_NUM_RX_RING_STATS 8
2739 #define BNXT_NUM_TX_RING_STATS 8
2740 #define BNXT_NUM_TPA_RING_STATS 4
2741 #define BNXT_NUM_TPA_RING_STATS_P5 5
2742 #define BNXT_NUM_TPA_RING_STATS_P7 6
2743
2744 #define BNXT_RING_STATS_SIZE_P5 \
2745 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2746 BNXT_NUM_TPA_RING_STATS_P5) * 8)
2747
2748 #define BNXT_RING_STATS_SIZE_P7 \
2749 ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
2750 BNXT_NUM_TPA_RING_STATS_P7) * 8)
2751
2752 #define BNXT_GET_RING_STATS64(sw, counter) \
2753 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2754
2755 #define BNXT_GET_RX_PORT_STATS64(sw, counter) \
2756 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2757
2758 #define BNXT_GET_TX_PORT_STATS64(sw, counter) \
2759 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2760
2761 #define BNXT_PORT_STATS_SIZE \
2762 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2763
2764 #define BNXT_TX_PORT_STATS_BYTE_OFFSET \
2765 (sizeof(struct rx_port_stats) + 512)
2766
2767 #define BNXT_RX_STATS_OFFSET(counter) \
2768 (offsetof(struct rx_port_stats, counter) / 8)
2769
2770 #define BNXT_TX_STATS_OFFSET(counter) \
2771 ((offsetof(struct tx_port_stats, counter) + \
2772 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2773
2774 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
2775 (offsetof(struct rx_port_stats_ext, counter) / 8)
2776
2777 #define BNXT_RX_STATS_EXT_NUM_LEGACY \
2778 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2779
2780 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
2781 (offsetof(struct tx_port_stats_ext, counter) / 8)
2782
2783 #define BNXT_HW_FEATURE_VLAN_ALL_RX \
2784 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2785 #define BNXT_HW_FEATURE_VLAN_ALL_TX \
2786 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2787
2788 #define I2C_DEV_ADDR_A0 0xa0
2789 #define I2C_DEV_ADDR_A2 0xa2
2790 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
2791 #define SFF_MODULE_ID_SFP 0x3
2792 #define SFF_MODULE_ID_QSFP 0xc
2793 #define SFF_MODULE_ID_QSFP_PLUS 0xd
2794 #define SFF_MODULE_ID_QSFP28 0x11
2795 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
2796
2797 #define BNXT_HDS_THRESHOLD_MAX 1023
2798
bnxt_tx_avail(struct bnxt * bp,const struct bnxt_tx_ring_info * txr)2799 static inline u32 bnxt_tx_avail(struct bnxt *bp,
2800 const struct bnxt_tx_ring_info *txr)
2801 {
2802 u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);
2803
2804 return bp->tx_ring_size - (used & bp->tx_ring_mask);
2805 }
2806
bnxt_writeq(struct bnxt * bp,u64 val,volatile void __iomem * addr)2807 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2808 volatile void __iomem *addr)
2809 {
2810 #if BITS_PER_LONG == 32
2811 spin_lock(&bp->db_lock);
2812 lo_hi_writeq(val, addr);
2813 spin_unlock(&bp->db_lock);
2814 #else
2815 writeq(val, addr);
2816 #endif
2817 }
2818
bnxt_writeq_relaxed(struct bnxt * bp,u64 val,volatile void __iomem * addr)2819 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2820 volatile void __iomem *addr)
2821 {
2822 #if BITS_PER_LONG == 32
2823 spin_lock(&bp->db_lock);
2824 lo_hi_writeq_relaxed(val, addr);
2825 spin_unlock(&bp->db_lock);
2826 #else
2827 writeq_relaxed(val, addr);
2828 #endif
2829 }
2830
2831 /* For TX and RX ring doorbells with no ordering guarantee*/
bnxt_db_write_relaxed(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2832 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2833 struct bnxt_db_info *db, u32 idx)
2834 {
2835 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2836 bnxt_writeq_relaxed(bp, db->db_key64 | DB_RING_IDX(db, idx),
2837 db->doorbell);
2838 } else {
2839 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2840
2841 writel_relaxed(db_val, db->doorbell);
2842 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2843 writel_relaxed(db_val, db->doorbell);
2844 }
2845 }
2846
2847 /* For TX and RX ring doorbells */
bnxt_db_write(struct bnxt * bp,struct bnxt_db_info * db,u32 idx)2848 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2849 u32 idx)
2850 {
2851 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
2852 bnxt_writeq(bp, db->db_key64 | DB_RING_IDX(db, idx),
2853 db->doorbell);
2854 } else {
2855 u32 db_val = db->db_key32 | DB_RING_IDX(db, idx);
2856
2857 writel(db_val, db->doorbell);
2858 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2859 writel(db_val, db->doorbell);
2860 }
2861 }
2862
2863 /* Must hold rtnl_lock */
bnxt_sriov_cfg(struct bnxt * bp)2864 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2865 {
2866 #if defined(CONFIG_BNXT_SRIOV)
2867 return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2868 #else
2869 return false;
2870 #endif
2871 }
2872
2873 extern const u16 bnxt_bstore_to_trace[];
2874 extern const u16 bnxt_lhint_arr[];
2875
2876 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2877 u16 prod, gfp_t gfp);
2878 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2879 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2880 bool bnxt_bs_trace_avail(struct bnxt *bp, u16 type);
2881 void bnxt_set_tpa_flags(struct bnxt *bp);
2882 void bnxt_set_ring_params(struct bnxt *);
2883 void bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2884 void bnxt_insert_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
2885 void bnxt_del_one_usr_fltr(struct bnxt *bp, struct bnxt_filter_base *fltr);
2886 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2887 int bmap_size, bool async_only);
2888 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2889 void bnxt_del_l2_filter(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2890 struct bnxt_l2_filter *bnxt_alloc_new_l2_filter(struct bnxt *bp,
2891 struct bnxt_l2_key *key,
2892 u16 flags);
2893 int bnxt_hwrm_l2_filter_free(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2894 int bnxt_hwrm_l2_filter_alloc(struct bnxt *bp, struct bnxt_l2_filter *fltr);
2895 int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2896 struct bnxt_ntuple_filter *fltr);
2897 int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2898 struct bnxt_ntuple_filter *fltr);
2899 int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2900 u32 tpa_flags);
2901 void bnxt_fill_ipv6_mask(__be32 mask[4]);
2902 void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp,
2903 struct ethtool_rxfh_context *rss_ctx);
2904 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2905 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2906 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2907 unsigned int start_rx_ring_idx,
2908 unsigned int nr_rings);
2909 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2910 int bnxt_nq_rings_in_use(struct bnxt *bp);
2911 int bnxt_hwrm_set_coal(struct bnxt *);
2912 size_t bnxt_copy_ctx_mem(struct bnxt *bp, struct bnxt_ctx_mem_type *ctxm,
2913 void *buf, size_t offset);
2914 void bnxt_free_ctx_mem(struct bnxt *bp, bool force);
2915 int bnxt_num_tx_to_cp(struct bnxt *bp, int tx);
2916 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2917 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2918 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2919 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2920 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2921 void bnxt_tx_disable(struct bnxt *bp);
2922 void bnxt_tx_enable(struct bnxt *bp);
2923 void bnxt_sched_reset_txr(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
2924 u16 curr);
2925 void bnxt_report_link(struct bnxt *bp);
2926 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2927 int bnxt_hwrm_set_pause(struct bnxt *);
2928 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2929 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2930 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2931 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2932 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2933 int bnxt_hwrm_func_qcaps(struct bnxt *bp);
2934 int bnxt_hwrm_fw_set_time(struct bnxt *);
2935 int bnxt_hwrm_vnic_update(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2936 u8 valid);
2937 int bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2938 int __bnxt_setup_vnic_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);
2939 void bnxt_del_one_rss_ctx(struct bnxt *bp, struct bnxt_rss_ctx *rss_ctx,
2940 bool all);
2941 int bnxt_open_nic(struct bnxt *, bool, bool);
2942 int bnxt_half_open_nic(struct bnxt *bp);
2943 void bnxt_half_close_nic(struct bnxt *bp);
2944 void bnxt_reenable_sriov(struct bnxt *bp);
2945 void bnxt_close_nic(struct bnxt *, bool, bool);
2946 void bnxt_get_ring_err_stats(struct bnxt *bp,
2947 struct bnxt_total_ring_err_stats *stats);
2948 bool bnxt_rfs_capable(struct bnxt *bp, bool new_rss_ctx);
2949 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2950 u32 *reg_buf);
2951 void bnxt_fw_exception(struct bnxt *bp);
2952 void bnxt_fw_reset(struct bnxt *bp);
2953 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2954 int tx_xdp);
2955 int bnxt_fw_init_one(struct bnxt *bp);
2956 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2957 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2958 struct bnxt_ntuple_filter *bnxt_lookup_ntp_filter_from_idx(struct bnxt *bp,
2959 struct bnxt_ntuple_filter *fltr, u32 idx);
2960 u32 bnxt_get_ntp_filter_idx(struct bnxt *bp, struct flow_keys *fkeys,
2961 const struct sk_buff *skb);
2962 int bnxt_insert_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr,
2963 u32 idx);
2964 void bnxt_del_ntp_filter(struct bnxt *bp, struct bnxt_ntuple_filter *fltr);
2965 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2966 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2967 int bnxt_get_port_parent_id(struct net_device *dev,
2968 struct netdev_phys_item_id *ppid);
2969 void bnxt_dim_work(struct work_struct *work);
2970 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2971 void bnxt_print_device_info(struct bnxt *bp);
2972 #endif
2973