1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 *
7 */
8
9 #ifndef _UFS_EXYNOS_H_
10 #define _UFS_EXYNOS_H_
11
12 /*
13 * Component registers
14 */
15
16 #define COMP_CLK_PERIOD 0x44
17
18 /*
19 * UNIPRO registers
20 */
21 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE 0x150
22
23 /*
24 * MIBs for PA debug registers
25 */
26 #define PA_DBG_CLK_PERIOD 0x9514
27 #define PA_DBG_TXPHY_CFGUPDT 0x9518
28 #define PA_DBG_RXPHY_CFGUPDT 0x9519
29 #define PA_DBG_MODE 0x9529
30 #define PA_DBG_SKIP_RESET_PHY 0x9539
31 #define PA_DBG_AUTOMODE_THLD 0x9536
32 #define PA_DBG_OV_TM 0x9540
33 #define PA_DBG_SKIP_LINE_RESET 0x9541
34 #define PA_DBG_LINE_RESET_REQ 0x9543
35 #define PA_DBG_OPTION_SUITE 0x9564
36 #define PA_DBG_OPTION_SUITE_DYN 0x9565
37
38 /*
39 * Note: GS101_DBG_OPTION offsets below differ from the TRM
40 * but match the downstream driver. Following the TRM
41 * results in non-functioning UFS.
42 */
43 #define PA_GS101_DBG_OPTION_SUITE1 0x956a
44 #define PA_GS101_DBG_OPTION_SUITE2 0x956d
45
46 /*
47 * MIBs for Transport Layer debug registers
48 */
49 #define T_DBG_SKIP_INIT_HIBERN8_EXIT 0xc001
50
51 /*
52 * Exynos MPHY attributes
53 */
54 #define TX_LINERESET_N_VAL 0x0277
55 #define TX_LINERESET_N(v) (((v) >> 10) & 0xFF)
56 #define TX_LINERESET_P_VAL 0x027D
57 #define TX_LINERESET_P(v) (((v) >> 12) & 0xFF)
58 #define TX_OV_SLEEP_CNT_TIMER 0x028E
59 #define TX_OV_H8_ENTER_EN (1 << 7)
60 #define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F)
61 #define TX_HIGH_Z_CNT_11_08 0x028C
62 #define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF)
63 #define TX_HIGH_Z_CNT_07_00 0x028D
64 #define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF)
65 #define TX_BASE_NVAL_07_00 0x0293
66 #define TX_BASE_NVAL_L(v) ((v) & 0xFF)
67 #define TX_BASE_NVAL_15_08 0x0294
68 #define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
69 #define TX_GRAN_NVAL_07_00 0x0295
70 #define TX_GRAN_NVAL_L(v) ((v) & 0xFF)
71 #define TX_GRAN_NVAL_10_08 0x0296
72 #define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
73
74 #define VND_TX_CLK_PRD 0xAA
75 #define VND_TX_CLK_PRD_EN 0xA9
76 #define VND_TX_LINERESET_PVALUE0 0xAD
77 #define VND_TX_LINERESET_PVALUE1 0xAC
78 #define VND_TX_LINERESET_PVALUE2 0xAB
79
80 #define TX_LINE_RESET_TIME 3200
81
82 #define VND_RX_CLK_PRD 0x12
83 #define VND_RX_CLK_PRD_EN 0x11
84 #define VND_RX_LINERESET_VALUE0 0x1D
85 #define VND_RX_LINERESET_VALUE1 0x1C
86 #define VND_RX_LINERESET_VALUE2 0x1B
87
88 #define RX_LINE_RESET_TIME 1000
89
90 #define RX_FILLER_ENABLE 0x0316
91 #define RX_FILLER_EN (1 << 1)
92 #define RX_LINERESET_VAL 0x0317
93 #define RX_LINERESET(v) (((v) >> 12) & 0xFF)
94 #define RX_LCC_IGNORE 0x0318
95 #define RX_SYNC_MASK_LENGTH 0x0321
96 #define RX_HIBERN8_WAIT_VAL_BIT_20_16 0x0331
97 #define RX_HIBERN8_WAIT_VAL_BIT_15_08 0x0332
98 #define RX_HIBERN8_WAIT_VAL_BIT_07_00 0x0333
99 #define RX_OV_SLEEP_CNT_TIMER 0x0340
100 #define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F)
101 #define RX_OV_STALL_CNT_TIMER 0x0341
102 #define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF)
103 #define RX_BASE_NVAL_07_00 0x0355
104 #define RX_BASE_NVAL_L(v) ((v) & 0xFF)
105 #define RX_BASE_NVAL_15_08 0x0354
106 #define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
107 #define RX_GRAN_NVAL_07_00 0x0353
108 #define RX_GRAN_NVAL_L(v) ((v) & 0xFF)
109 #define RX_GRAN_NVAL_10_08 0x0352
110 #define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
111
112 #define CMN_PWM_CLK_CTRL 0x0402
113 #define PWM_CLK_CTRL_MASK 0x3
114
115 #define IATOVAL_NSEC 20000 /* unit: ns */
116 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
117
118 struct exynos_ufs;
119
120 /* vendor specific pre-defined parameters */
121 #define SLOW 1
122 #define FAST 2
123
124 #define RX_ADV_FINE_GRAN_SUP_EN 0x1
125 #define RX_ADV_FINE_GRAN_STEP_VAL 0x3
126 #define RX_ADV_MIN_ACTV_TIME_CAP 0x9
127
128 #define PA_GRANULARITY_VAL 0x6
129 #define PA_TACTIVATE_VAL 0x3
130 #define PA_HIBERN8TIME_VAL 0x20
131
132 #define PCLK_AVAIL_MIN 70000000
133 #define PCLK_AVAIL_MAX 267000000
134
135 struct exynos_ufs_uic_attr {
136 /* TX Attributes */
137 unsigned int tx_trailingclks;
138 unsigned int tx_dif_p_nsec;
139 unsigned int tx_dif_n_nsec;
140 unsigned int tx_high_z_cnt_nsec;
141 unsigned int tx_base_unit_nsec;
142 unsigned int tx_gran_unit_nsec;
143 unsigned int tx_sleep_cnt;
144 unsigned int tx_min_activatetime;
145 /* RX Attributes */
146 unsigned int rx_filler_enable;
147 unsigned int rx_dif_p_nsec;
148 unsigned int rx_hibern8_wait_nsec;
149 unsigned int rx_base_unit_nsec;
150 unsigned int rx_gran_unit_nsec;
151 unsigned int rx_sleep_cnt;
152 unsigned int rx_stall_cnt;
153 unsigned int rx_hs_g1_sync_len_cap;
154 unsigned int rx_hs_g2_sync_len_cap;
155 unsigned int rx_hs_g3_sync_len_cap;
156 unsigned int rx_hs_g1_prep_sync_len_cap;
157 unsigned int rx_hs_g2_prep_sync_len_cap;
158 unsigned int rx_hs_g3_prep_sync_len_cap;
159 /* Common Attributes */
160 unsigned int cmn_pwm_clk_ctrl;
161 /* Internal Attributes */
162 unsigned int pa_dbg_clk_period_off;
163 unsigned int pa_dbg_opt_suite1_val;
164 unsigned int pa_dbg_opt_suite1_off;
165 unsigned int pa_dbg_opt_suite2_val;
166 unsigned int pa_dbg_opt_suite2_off;
167 /* Changeable Attributes */
168 unsigned int rx_adv_fine_gran_sup_en;
169 unsigned int rx_adv_fine_gran_step;
170 unsigned int rx_min_actv_time_cap;
171 unsigned int rx_hibern8_time_cap;
172 unsigned int rx_adv_min_actv_time_cap;
173 unsigned int rx_adv_hibern8_time_cap;
174 unsigned int pa_granularity;
175 unsigned int pa_tactivate;
176 unsigned int pa_hibern8time;
177 };
178
179 struct exynos_ufs_drv_data {
180 const struct ufs_hba_variant_ops *vops;
181 struct exynos_ufs_uic_attr *uic_attr;
182 unsigned int quirks;
183 unsigned int opts;
184 /* SoC's specific operations */
185 int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
186 int (*pre_link)(struct exynos_ufs *ufs);
187 int (*post_link)(struct exynos_ufs *ufs);
188 int (*pre_pwr_change)(struct exynos_ufs *ufs,
189 struct ufs_pa_layer_attr *pwr);
190 int (*post_pwr_change)(struct exynos_ufs *ufs,
191 struct ufs_pa_layer_attr *pwr);
192 int (*pre_hce_enable)(struct exynos_ufs *ufs);
193 int (*post_hce_enable)(struct exynos_ufs *ufs);
194 };
195
196 struct ufs_phy_time_cfg {
197 u32 tx_linereset_p;
198 u32 tx_linereset_n;
199 u32 tx_high_z_cnt;
200 u32 tx_base_n_val;
201 u32 tx_gran_n_val;
202 u32 tx_sleep_cnt;
203 u32 rx_linereset;
204 u32 rx_hibern8_wait;
205 u32 rx_base_n_val;
206 u32 rx_gran_n_val;
207 u32 rx_sleep_cnt;
208 u32 rx_stall_cnt;
209 };
210
211 struct exynos_ufs {
212 struct ufs_hba *hba;
213 struct phy *phy;
214 void __iomem *reg_hci;
215 void __iomem *reg_unipro;
216 void __iomem *reg_ufsp;
217 struct clk *clk_hci_core;
218 struct clk *clk_unipro_main;
219 struct clk *clk_apb;
220 u32 pclk_rate;
221 u32 pclk_div;
222 u32 pclk_avail_min;
223 u32 pclk_avail_max;
224 unsigned long mclk_rate;
225 int avail_ln_rx;
226 int avail_ln_tx;
227 int rx_sel_idx;
228 struct ufs_pa_layer_attr dev_req_params;
229 struct ufs_phy_time_cfg t_cfg;
230 ktime_t entry_hibern8_t;
231 const struct exynos_ufs_drv_data *drv_data;
232 struct regmap *sysreg;
233 u32 shareability_reg_offset;
234
235 u32 opts;
236 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL BIT(0)
237 #define EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB BIT(1)
238 #define EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL BIT(2)
239 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
240 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
241 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
242 #define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
243 #define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7)
244 };
245
246 #define for_each_ufs_rx_lane(ufs, i) \
247 for (i = (ufs)->rx_sel_idx; \
248 i < (ufs)->rx_sel_idx + (ufs)->avail_ln_rx; i++)
249 #define for_each_ufs_tx_lane(ufs, i) \
250 for (i = 0; i < (ufs)->avail_ln_tx; i++)
251
252 #define EXYNOS_UFS_MMIO_FUNC(name) \
253 static inline void name##_writel(struct exynos_ufs *ufs, u32 val, u32 reg)\
254 { \
255 writel(val, ufs->reg_##name + reg); \
256 } \
257 \
258 static inline u32 name##_readl(struct exynos_ufs *ufs, u32 reg) \
259 { \
260 return readl(ufs->reg_##name + reg); \
261 }
262
263 EXYNOS_UFS_MMIO_FUNC(hci);
264 EXYNOS_UFS_MMIO_FUNC(unipro);
265 EXYNOS_UFS_MMIO_FUNC(ufsp);
266 #undef EXYNOS_UFS_MMIO_FUNC
267
268 long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long);
269
exynos_ufs_enable_ov_tm(struct ufs_hba * hba)270 static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba)
271 {
272 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true);
273 }
274
exynos_ufs_disable_ov_tm(struct ufs_hba * hba)275 static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba)
276 {
277 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false);
278 }
279
exynos_ufs_enable_dbg_mode(struct ufs_hba * hba)280 static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba)
281 {
282 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true);
283 }
284
exynos_ufs_disable_dbg_mode(struct ufs_hba * hba)285 static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba)
286 {
287 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false);
288 }
289
290 #endif /* _UFS_EXYNOS_H_ */
291