1 // SPDX-License-Identifier: GPL-2.0 2 /* BPF JIT compiler for RV64G 3 * 4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com> 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bpf.h> 10 #include <linux/filter.h> 11 #include <linux/memory.h> 12 #include <linux/stop_machine.h> 13 #include <asm/text-patching.h> 14 #include <asm/cfi.h> 15 #include <asm/percpu.h> 16 #include "bpf_jit.h" 17 18 #define RV_MAX_REG_ARGS 8 19 #define RV_FENTRY_NINSNS 2 20 #define RV_FENTRY_NBYTES (RV_FENTRY_NINSNS * 4) 21 #define RV_KCFI_NINSNS (IS_ENABLED(CONFIG_CFI) ? 1 : 0) 22 /* imm that allows emit_imm to emit max count insns */ 23 #define RV_MAX_COUNT_IMM 0x7FFF7FF7FF7FF7FF 24 25 #define RV_REG_TCC RV_REG_A6 26 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ 27 #define RV_REG_ARENA RV_REG_S7 /* For storing arena_vm_start */ 28 29 static const int regmap[] = { 30 [BPF_REG_0] = RV_REG_A5, 31 [BPF_REG_1] = RV_REG_A0, 32 [BPF_REG_2] = RV_REG_A1, 33 [BPF_REG_3] = RV_REG_A2, 34 [BPF_REG_4] = RV_REG_A3, 35 [BPF_REG_5] = RV_REG_A4, 36 [BPF_REG_6] = RV_REG_S1, 37 [BPF_REG_7] = RV_REG_S2, 38 [BPF_REG_8] = RV_REG_S3, 39 [BPF_REG_9] = RV_REG_S4, 40 [BPF_REG_FP] = RV_REG_S5, 41 [BPF_REG_AX] = RV_REG_T0, 42 }; 43 44 static const int pt_regmap[] = { 45 [RV_REG_A0] = offsetof(struct pt_regs, a0), 46 [RV_REG_A1] = offsetof(struct pt_regs, a1), 47 [RV_REG_A2] = offsetof(struct pt_regs, a2), 48 [RV_REG_A3] = offsetof(struct pt_regs, a3), 49 [RV_REG_A4] = offsetof(struct pt_regs, a4), 50 [RV_REG_A5] = offsetof(struct pt_regs, a5), 51 [RV_REG_S1] = offsetof(struct pt_regs, s1), 52 [RV_REG_S2] = offsetof(struct pt_regs, s2), 53 [RV_REG_S3] = offsetof(struct pt_regs, s3), 54 [RV_REG_S4] = offsetof(struct pt_regs, s4), 55 [RV_REG_S5] = offsetof(struct pt_regs, s5), 56 [RV_REG_T0] = offsetof(struct pt_regs, t0), 57 }; 58 59 enum { 60 RV_CTX_F_SEEN_TAIL_CALL = 0, 61 RV_CTX_F_SEEN_CALL = RV_REG_RA, 62 RV_CTX_F_SEEN_S1 = RV_REG_S1, 63 RV_CTX_F_SEEN_S2 = RV_REG_S2, 64 RV_CTX_F_SEEN_S3 = RV_REG_S3, 65 RV_CTX_F_SEEN_S4 = RV_REG_S4, 66 RV_CTX_F_SEEN_S5 = RV_REG_S5, 67 RV_CTX_F_SEEN_S6 = RV_REG_S6, 68 }; 69 70 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) 71 { 72 u8 reg = regmap[bpf_reg]; 73 74 switch (reg) { 75 case RV_CTX_F_SEEN_S1: 76 case RV_CTX_F_SEEN_S2: 77 case RV_CTX_F_SEEN_S3: 78 case RV_CTX_F_SEEN_S4: 79 case RV_CTX_F_SEEN_S5: 80 case RV_CTX_F_SEEN_S6: 81 __set_bit(reg, &ctx->flags); 82 } 83 return reg; 84 }; 85 86 static bool seen_reg(int reg, struct rv_jit_context *ctx) 87 { 88 switch (reg) { 89 case RV_CTX_F_SEEN_CALL: 90 case RV_CTX_F_SEEN_S1: 91 case RV_CTX_F_SEEN_S2: 92 case RV_CTX_F_SEEN_S3: 93 case RV_CTX_F_SEEN_S4: 94 case RV_CTX_F_SEEN_S5: 95 case RV_CTX_F_SEEN_S6: 96 return test_bit(reg, &ctx->flags); 97 } 98 return false; 99 } 100 101 static void mark_fp(struct rv_jit_context *ctx) 102 { 103 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); 104 } 105 106 static void mark_call(struct rv_jit_context *ctx) 107 { 108 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 109 } 110 111 static bool seen_call(struct rv_jit_context *ctx) 112 { 113 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 114 } 115 116 static void mark_tail_call(struct rv_jit_context *ctx) 117 { 118 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 119 } 120 121 static bool seen_tail_call(struct rv_jit_context *ctx) 122 { 123 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 124 } 125 126 static u8 rv_tail_call_reg(struct rv_jit_context *ctx) 127 { 128 mark_tail_call(ctx); 129 130 if (seen_call(ctx)) { 131 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); 132 return RV_REG_S6; 133 } 134 return RV_REG_A6; 135 } 136 137 static bool is_32b_int(s64 val) 138 { 139 return -(1L << 31) <= val && val < (1L << 31); 140 } 141 142 static bool in_auipc_jalr_range(s64 val) 143 { 144 /* 145 * auipc+jalr can reach any signed PC-relative offset in the range 146 * [-2^31 - 2^11, 2^31 - 2^11). 147 */ 148 return (-(1L << 31) - (1L << 11)) <= val && 149 val < ((1L << 31) - (1L << 11)); 150 } 151 152 /* Modify rd pointer to alternate reg to avoid corrupting original reg */ 153 static void emit_sextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) 154 { 155 emit_sextw(ra, *rd, ctx); 156 *rd = ra; 157 } 158 159 static void emit_zextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) 160 { 161 emit_zextw(ra, *rd, ctx); 162 *rd = ra; 163 } 164 165 /* Emit fixed-length instructions for address */ 166 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) 167 { 168 /* 169 * Use the ro_insns(RX) to calculate the offset as the BPF program will 170 * finally run from this memory region. 171 */ 172 u64 ip = (u64)(ctx->ro_insns + ctx->ninsns); 173 s64 off = addr - ip; 174 s64 upper = (off + (1 << 11)) >> 12; 175 s64 lower = off & 0xfff; 176 177 if (extra_pass && !in_auipc_jalr_range(off)) { 178 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off); 179 return -ERANGE; 180 } 181 182 emit(rv_auipc(rd, upper), ctx); 183 emit(rv_addi(rd, rd, lower), ctx); 184 return 0; 185 } 186 187 /* Emit variable-length instructions for 32-bit and 64-bit imm */ 188 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) 189 { 190 /* Note that the immediate from the add is sign-extended, 191 * which means that we need to compensate this by adding 2^12, 192 * when the 12th bit is set. A simpler way of doing this, and 193 * getting rid of the check, is to just add 2**11 before the 194 * shift. The "Loading a 32-Bit constant" example from the 195 * "Computer Organization and Design, RISC-V edition" book by 196 * Patterson/Hennessy highlights this fact. 197 * 198 * This also means that we need to process LSB to MSB. 199 */ 200 s64 upper = (val + (1 << 11)) >> 12; 201 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, 202 * and addi are signed and RVC checks will perform signed comparisons. 203 */ 204 s64 lower = ((val & 0xfff) << 52) >> 52; 205 int shift; 206 207 if (is_32b_int(val)) { 208 if (upper) 209 emit_lui(rd, upper, ctx); 210 211 if (!upper) { 212 emit_li(rd, lower, ctx); 213 return; 214 } 215 216 emit_addiw(rd, rd, lower, ctx); 217 return; 218 } 219 220 shift = __ffs(upper); 221 upper >>= shift; 222 shift += 12; 223 224 emit_imm(rd, upper, ctx); 225 226 emit_slli(rd, rd, shift, ctx); 227 if (lower) 228 emit_addi(rd, rd, lower, ctx); 229 } 230 231 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) 232 { 233 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; 234 235 if (seen_reg(RV_REG_RA, ctx)) { 236 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); 237 store_offset -= 8; 238 } 239 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); 240 store_offset -= 8; 241 if (seen_reg(RV_REG_S1, ctx)) { 242 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); 243 store_offset -= 8; 244 } 245 if (seen_reg(RV_REG_S2, ctx)) { 246 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); 247 store_offset -= 8; 248 } 249 if (seen_reg(RV_REG_S3, ctx)) { 250 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); 251 store_offset -= 8; 252 } 253 if (seen_reg(RV_REG_S4, ctx)) { 254 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); 255 store_offset -= 8; 256 } 257 if (seen_reg(RV_REG_S5, ctx)) { 258 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); 259 store_offset -= 8; 260 } 261 if (seen_reg(RV_REG_S6, ctx)) { 262 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); 263 store_offset -= 8; 264 } 265 if (ctx->arena_vm_start) { 266 emit_ld(RV_REG_ARENA, store_offset, RV_REG_SP, ctx); 267 store_offset -= 8; 268 } 269 270 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); 271 /* Set return value. */ 272 if (!is_tail_call) 273 emit_addiw(RV_REG_A0, RV_REG_A5, 0, ctx); 274 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, 275 /* kcfi, fentry and TCC init insns will be skipped on tailcall */ 276 is_tail_call ? (RV_KCFI_NINSNS + RV_FENTRY_NINSNS + 1) * 4 : 0, 277 ctx); 278 } 279 280 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, 281 struct rv_jit_context *ctx) 282 { 283 switch (cond) { 284 case BPF_JEQ: 285 emit(rv_beq(rd, rs, rvoff >> 1), ctx); 286 return; 287 case BPF_JGT: 288 emit(rv_bltu(rs, rd, rvoff >> 1), ctx); 289 return; 290 case BPF_JLT: 291 emit(rv_bltu(rd, rs, rvoff >> 1), ctx); 292 return; 293 case BPF_JGE: 294 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); 295 return; 296 case BPF_JLE: 297 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); 298 return; 299 case BPF_JNE: 300 emit(rv_bne(rd, rs, rvoff >> 1), ctx); 301 return; 302 case BPF_JSGT: 303 emit(rv_blt(rs, rd, rvoff >> 1), ctx); 304 return; 305 case BPF_JSLT: 306 emit(rv_blt(rd, rs, rvoff >> 1), ctx); 307 return; 308 case BPF_JSGE: 309 emit(rv_bge(rd, rs, rvoff >> 1), ctx); 310 return; 311 case BPF_JSLE: 312 emit(rv_bge(rs, rd, rvoff >> 1), ctx); 313 } 314 } 315 316 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, 317 struct rv_jit_context *ctx) 318 { 319 s64 upper, lower; 320 321 if (is_13b_int(rvoff)) { 322 emit_bcc(cond, rd, rs, rvoff, ctx); 323 return; 324 } 325 326 /* Adjust for jal */ 327 rvoff -= 4; 328 329 /* Transform, e.g.: 330 * bne rd,rs,foo 331 * to 332 * beq rd,rs,<.L1> 333 * (auipc foo) 334 * jal(r) foo 335 * .L1 336 */ 337 cond = invert_bpf_cond(cond); 338 if (is_21b_int(rvoff)) { 339 emit_bcc(cond, rd, rs, 8, ctx); 340 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); 341 return; 342 } 343 344 /* 32b No need for an additional rvoff adjustment, since we 345 * get that from the auipc at PC', where PC = PC' + 4. 346 */ 347 upper = (rvoff + (1 << 11)) >> 12; 348 lower = rvoff & 0xfff; 349 350 emit_bcc(cond, rd, rs, 12, ctx); 351 emit(rv_auipc(RV_REG_T1, upper), ctx); 352 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); 353 } 354 355 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) 356 { 357 int tc_ninsn, off, start_insn = ctx->ninsns; 358 u8 tcc = rv_tail_call_reg(ctx); 359 360 /* a0: &ctx 361 * a1: &array 362 * a2: index 363 * 364 * if (index >= array->map.max_entries) 365 * goto out; 366 */ 367 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : 368 ctx->offset[0]; 369 emit_zextw(RV_REG_A2, RV_REG_A2, ctx); 370 371 off = offsetof(struct bpf_array, map.max_entries); 372 if (is_12b_check(off, insn)) 373 return -1; 374 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); 375 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 376 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); 377 378 /* if (--TCC < 0) 379 * goto out; 380 */ 381 emit_addi(RV_REG_TCC, tcc, -1, ctx); 382 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 383 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); 384 385 /* prog = array->ptrs[index]; 386 * if (!prog) 387 * goto out; 388 */ 389 emit_sh3add(RV_REG_T2, RV_REG_A2, RV_REG_A1, ctx); 390 off = offsetof(struct bpf_array, ptrs); 391 if (is_12b_check(off, insn)) 392 return -1; 393 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); 394 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 395 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); 396 397 /* goto *(prog->bpf_func + 4); */ 398 off = offsetof(struct bpf_prog, bpf_func); 399 if (is_12b_check(off, insn)) 400 return -1; 401 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); 402 __build_epilogue(true, ctx); 403 return 0; 404 } 405 406 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, 407 struct rv_jit_context *ctx) 408 { 409 u8 code = insn->code; 410 411 switch (code) { 412 case BPF_JMP | BPF_JA: 413 case BPF_JMP | BPF_CALL: 414 case BPF_JMP | BPF_EXIT: 415 case BPF_JMP | BPF_TAIL_CALL: 416 break; 417 default: 418 *rd = bpf_to_rv_reg(insn->dst_reg, ctx); 419 } 420 421 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || 422 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || 423 code & BPF_LDX || code & BPF_STX) 424 *rs = bpf_to_rv_reg(insn->src_reg, ctx); 425 } 426 427 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr, 428 struct rv_jit_context *ctx) 429 { 430 s64 upper, lower; 431 432 if (rvoff && fixed_addr && is_21b_int(rvoff)) { 433 emit(rv_jal(rd, rvoff >> 1), ctx); 434 return 0; 435 } else if (in_auipc_jalr_range(rvoff)) { 436 upper = (rvoff + (1 << 11)) >> 12; 437 lower = rvoff & 0xfff; 438 emit(rv_auipc(RV_REG_T1, upper), ctx); 439 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); 440 return 0; 441 } 442 443 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); 444 return -ERANGE; 445 } 446 447 static bool is_signed_bpf_cond(u8 cond) 448 { 449 return cond == BPF_JSGT || cond == BPF_JSLT || 450 cond == BPF_JSGE || cond == BPF_JSLE; 451 } 452 453 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx) 454 { 455 s64 off = 0; 456 u64 ip; 457 458 if (addr && ctx->insns && ctx->ro_insns) { 459 /* 460 * Use the ro_insns(RX) to calculate the offset as the BPF 461 * program will finally run from this memory region. 462 */ 463 ip = (u64)(long)(ctx->ro_insns + ctx->ninsns); 464 off = addr - ip; 465 } 466 467 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx); 468 } 469 470 static inline void emit_kcfi(u32 hash, struct rv_jit_context *ctx) 471 { 472 if (IS_ENABLED(CONFIG_CFI)) 473 emit(hash, ctx); 474 } 475 476 static void emit_ldx_insn(u8 rd, s16 off, u8 rs, u8 size, bool sign_ext, 477 struct rv_jit_context *ctx) 478 { 479 switch (size) { 480 case BPF_B: 481 emit(sign_ext ? rv_lb(rd, off, rs) : rv_lbu(rd, off, rs), ctx); 482 break; 483 case BPF_H: 484 emit(sign_ext ? rv_lh(rd, off, rs) : rv_lhu(rd, off, rs), ctx); 485 break; 486 case BPF_W: 487 emit(sign_ext ? rv_lw(rd, off, rs) : rv_lwu(rd, off, rs), ctx); 488 break; 489 case BPF_DW: 490 emit_ld(rd, off, rs, ctx); 491 break; 492 } 493 494 } 495 496 static void emit_stx_insn(u8 rd, s16 off, u8 rs, u8 size, struct rv_jit_context *ctx) 497 { 498 switch (size) { 499 case BPF_B: 500 emit(rv_sb(rd, off, rs), ctx); 501 break; 502 case BPF_H: 503 emit(rv_sh(rd, off, rs), ctx); 504 break; 505 case BPF_W: 506 emit_sw(rd, off, rs, ctx); 507 break; 508 case BPF_DW: 509 emit_sd(rd, off, rs, ctx); 510 break; 511 } 512 } 513 514 static void emit_ldx(u8 rd, s16 off, u8 rs, u8 size, bool sign_ext, 515 struct rv_jit_context *ctx) 516 { 517 if (is_12b_int(off)) { 518 ctx->ex_insn_off = ctx->ninsns; 519 emit_ldx_insn(rd, off, rs, size, sign_ext, ctx); 520 ctx->ex_jmp_off = ctx->ninsns; 521 return; 522 } 523 524 emit_imm(RV_REG_T1, off, ctx); 525 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 526 ctx->ex_insn_off = ctx->ninsns; 527 emit_ldx_insn(rd, 0, RV_REG_T1, size, sign_ext, ctx); 528 ctx->ex_jmp_off = ctx->ninsns; 529 } 530 531 static void emit_st(u8 rd, s16 off, s32 imm, u8 size, struct rv_jit_context *ctx) 532 { 533 emit_imm(RV_REG_T1, imm, ctx); 534 if (is_12b_int(off)) { 535 ctx->ex_insn_off = ctx->ninsns; 536 emit_stx_insn(rd, off, RV_REG_T1, size, ctx); 537 ctx->ex_jmp_off = ctx->ninsns; 538 return; 539 } 540 541 emit_imm(RV_REG_T2, off, ctx); 542 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 543 ctx->ex_insn_off = ctx->ninsns; 544 emit_stx_insn(RV_REG_T2, 0, RV_REG_T1, size, ctx); 545 ctx->ex_jmp_off = ctx->ninsns; 546 } 547 548 static void emit_stx(u8 rd, s16 off, u8 rs, u8 size, struct rv_jit_context *ctx) 549 { 550 if (is_12b_int(off)) { 551 ctx->ex_insn_off = ctx->ninsns; 552 emit_stx_insn(rd, off, rs, size, ctx); 553 ctx->ex_jmp_off = ctx->ninsns; 554 return; 555 } 556 557 emit_imm(RV_REG_T1, off, ctx); 558 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 559 ctx->ex_insn_off = ctx->ninsns; 560 emit_stx_insn(RV_REG_T1, 0, rs, size, ctx); 561 ctx->ex_jmp_off = ctx->ninsns; 562 } 563 564 static int emit_atomic_ld_st(u8 rd, u8 rs, const struct bpf_insn *insn, 565 struct rv_jit_context *ctx) 566 { 567 u8 code = insn->code; 568 s32 imm = insn->imm; 569 s16 off = insn->off; 570 571 switch (imm) { 572 /* dst_reg = load_acquire(src_reg + off16) */ 573 case BPF_LOAD_ACQ: 574 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 575 emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx); 576 rs = RV_REG_T2; 577 } 578 579 emit_ldx(rd, off, rs, BPF_SIZE(code), false, ctx); 580 emit_fence_r_rw(ctx); 581 582 /* If our next insn is a redundant zext, return 1 to tell 583 * build_body() to skip it. 584 */ 585 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 586 return 1; 587 break; 588 /* store_release(dst_reg + off16, src_reg) */ 589 case BPF_STORE_REL: 590 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 591 emit_add(RV_REG_T2, rd, RV_REG_ARENA, ctx); 592 rd = RV_REG_T2; 593 } 594 595 emit_fence_rw_w(ctx); 596 emit_stx(rd, off, rs, BPF_SIZE(code), ctx); 597 break; 598 default: 599 pr_err_once("bpf-jit: invalid atomic load/store opcode %02x\n", imm); 600 return -EINVAL; 601 } 602 603 return 0; 604 } 605 606 static int emit_atomic_rmw(u8 rd, u8 rs, const struct bpf_insn *insn, 607 struct rv_jit_context *ctx) 608 { 609 u8 code = insn->code; 610 s16 off = insn->off; 611 s32 imm = insn->imm; 612 bool is64 = BPF_SIZE(code) == BPF_DW; 613 614 if (BPF_SIZE(code) != BPF_W && BPF_SIZE(code) != BPF_DW) { 615 pr_err_once("bpf-jit: 1- and 2-byte RMW atomics are not supported\n"); 616 return -EINVAL; 617 } 618 619 if (off) { 620 if (is_12b_int(off)) { 621 emit_addi(RV_REG_T1, rd, off, ctx); 622 } else { 623 emit_imm(RV_REG_T1, off, ctx); 624 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 625 } 626 rd = RV_REG_T1; 627 } 628 629 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 630 emit_add(RV_REG_T1, rd, RV_REG_ARENA, ctx); 631 rd = RV_REG_T1; 632 } 633 634 switch (imm) { 635 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */ 636 case BPF_ADD: 637 ctx->ex_insn_off = ctx->ninsns; 638 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) : 639 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 640 ctx->ex_jmp_off = ctx->ninsns; 641 break; 642 case BPF_AND: 643 ctx->ex_insn_off = ctx->ninsns; 644 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) : 645 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 646 ctx->ex_jmp_off = ctx->ninsns; 647 break; 648 case BPF_OR: 649 ctx->ex_insn_off = ctx->ninsns; 650 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) : 651 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 652 ctx->ex_jmp_off = ctx->ninsns; 653 break; 654 case BPF_XOR: 655 ctx->ex_insn_off = ctx->ninsns; 656 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) : 657 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 658 ctx->ex_jmp_off = ctx->ninsns; 659 break; 660 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */ 661 case BPF_ADD | BPF_FETCH: 662 ctx->ex_insn_off = ctx->ninsns; 663 emit(is64 ? rv_amoadd_d(rs, rs, rd, 1, 1) : 664 rv_amoadd_w(rs, rs, rd, 1, 1), ctx); 665 ctx->ex_jmp_off = ctx->ninsns; 666 if (!is64) 667 emit_zextw(rs, rs, ctx); 668 break; 669 case BPF_AND | BPF_FETCH: 670 ctx->ex_insn_off = ctx->ninsns; 671 emit(is64 ? rv_amoand_d(rs, rs, rd, 1, 1) : 672 rv_amoand_w(rs, rs, rd, 1, 1), ctx); 673 ctx->ex_jmp_off = ctx->ninsns; 674 if (!is64) 675 emit_zextw(rs, rs, ctx); 676 break; 677 case BPF_OR | BPF_FETCH: 678 ctx->ex_insn_off = ctx->ninsns; 679 emit(is64 ? rv_amoor_d(rs, rs, rd, 1, 1) : 680 rv_amoor_w(rs, rs, rd, 1, 1), ctx); 681 ctx->ex_jmp_off = ctx->ninsns; 682 if (!is64) 683 emit_zextw(rs, rs, ctx); 684 break; 685 case BPF_XOR | BPF_FETCH: 686 ctx->ex_insn_off = ctx->ninsns; 687 emit(is64 ? rv_amoxor_d(rs, rs, rd, 1, 1) : 688 rv_amoxor_w(rs, rs, rd, 1, 1), ctx); 689 ctx->ex_jmp_off = ctx->ninsns; 690 if (!is64) 691 emit_zextw(rs, rs, ctx); 692 break; 693 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */ 694 case BPF_XCHG: 695 ctx->ex_insn_off = ctx->ninsns; 696 emit(is64 ? rv_amoswap_d(rs, rs, rd, 1, 1) : 697 rv_amoswap_w(rs, rs, rd, 1, 1), ctx); 698 ctx->ex_jmp_off = ctx->ninsns; 699 if (!is64) 700 emit_zextw(rs, rs, ctx); 701 break; 702 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ 703 case BPF_CMPXCHG: 704 emit_cmpxchg(rd, rs, regmap[BPF_REG_0], is64, ctx); 705 break; 706 default: 707 pr_err_once("bpf-jit: invalid atomic RMW opcode %02x\n", imm); 708 return -EINVAL; 709 } 710 711 return 0; 712 } 713 714 /* 715 * Sign-extend the register if necessary 716 */ 717 static int sign_extend(u8 rd, u8 rs, u8 sz, bool sign, struct rv_jit_context *ctx) 718 { 719 if (!sign && (sz == 1 || sz == 2)) { 720 if (rd != rs) 721 emit_mv(rd, rs, ctx); 722 return 0; 723 } 724 725 switch (sz) { 726 case 1: 727 emit_sextb(rd, rs, ctx); 728 break; 729 case 2: 730 emit_sexth(rd, rs, ctx); 731 break; 732 case 4: 733 emit_sextw(rd, rs, ctx); 734 break; 735 case 8: 736 if (rd != rs) 737 emit_mv(rd, rs, ctx); 738 break; 739 default: 740 pr_err("bpf-jit: invalid size %d for sign_extend\n", sz); 741 return -EINVAL; 742 } 743 744 return 0; 745 } 746 747 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) 748 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 749 #define REG_DONT_CLEAR_MARKER 0 /* RV_REG_ZERO unused in pt_regmap */ 750 751 bool ex_handler_bpf(const struct exception_table_entry *ex, 752 struct pt_regs *regs) 753 { 754 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 755 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 756 757 if (regs_offset != REG_DONT_CLEAR_MARKER) 758 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0; 759 regs->epc = (unsigned long)&ex->fixup - offset; 760 761 return true; 762 } 763 764 /* For accesses to BTF pointers, add an entry to the exception table */ 765 static int add_exception_handler(const struct bpf_insn *insn, int dst_reg, 766 struct rv_jit_context *ctx) 767 { 768 struct exception_table_entry *ex; 769 unsigned long pc; 770 off_t ins_offset; 771 off_t fixup_offset; 772 773 if (!ctx->insns || !ctx->ro_insns || !ctx->prog->aux->extable || 774 ctx->ex_insn_off <= 0 || ctx->ex_jmp_off <= 0) 775 return 0; 776 777 if (BPF_MODE(insn->code) != BPF_PROBE_MEM && 778 BPF_MODE(insn->code) != BPF_PROBE_MEMSX && 779 BPF_MODE(insn->code) != BPF_PROBE_MEM32 && 780 BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) 781 return 0; 782 783 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) 784 return -EINVAL; 785 786 if (WARN_ON_ONCE(ctx->ex_insn_off > ctx->ninsns || ctx->ex_jmp_off > ctx->ninsns)) 787 return -EINVAL; 788 789 ex = &ctx->prog->aux->extable[ctx->nexentries]; 790 pc = (unsigned long)&ctx->ro_insns[ctx->ex_insn_off]; 791 792 /* 793 * This is the relative offset of the instruction that may fault from 794 * the exception table itself. This will be written to the exception 795 * table and if this instruction faults, the destination register will 796 * be set to '0' and the execution will jump to the next instruction. 797 */ 798 ins_offset = pc - (long)&ex->insn; 799 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 800 return -ERANGE; 801 802 /* 803 * Since the extable follows the program, the fixup offset is always 804 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value 805 * to keep things simple, and put the destination register in the upper 806 * bits. We don't need to worry about buildtime or runtime sort 807 * modifying the upper bits because the table is already sorted, and 808 * isn't part of the main exception table. 809 * 810 * The fixup_offset is set to the next instruction from the instruction 811 * that may fault. The execution will jump to this after handling the 812 * fault. 813 */ 814 fixup_offset = (long)&ex->fixup - (long)&ctx->ro_insns[ctx->ex_jmp_off]; 815 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, fixup_offset)) 816 return -ERANGE; 817 818 /* 819 * The offsets above have been calculated using the RO buffer but we 820 * need to use the R/W buffer for writes. 821 * switch ex to rw buffer for writing. 822 */ 823 ex = (void *)ctx->insns + ((void *)ex - (void *)ctx->ro_insns); 824 825 ex->insn = ins_offset; 826 827 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, fixup_offset) | 828 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 829 ex->type = EX_TYPE_BPF; 830 831 ctx->ex_insn_off = 0; 832 ctx->ex_jmp_off = 0; 833 ctx->nexentries++; 834 return 0; 835 } 836 837 static int gen_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call) 838 { 839 s64 rvoff; 840 struct rv_jit_context ctx; 841 842 ctx.ninsns = 0; 843 ctx.insns = (u16 *)insns; 844 845 if (!target) { 846 emit(rv_nop(), &ctx); 847 emit(rv_nop(), &ctx); 848 return 0; 849 } 850 851 rvoff = (s64)(target - ip); 852 return emit_jump_and_link(is_call ? RV_REG_T0 : RV_REG_ZERO, rvoff, false, &ctx); 853 } 854 855 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 856 enum bpf_text_poke_type new_t, void *old_addr, 857 void *new_addr) 858 { 859 u32 old_insns[RV_FENTRY_NINSNS], new_insns[RV_FENTRY_NINSNS]; 860 bool is_call; 861 int ret; 862 863 if (!is_kernel_text((unsigned long)ip) && 864 !is_bpf_text_address((unsigned long)ip)) 865 return -ENOTSUPP; 866 867 is_call = old_t == BPF_MOD_CALL; 868 ret = gen_jump_or_nops(old_addr, ip, old_insns, is_call); 869 if (ret) 870 return ret; 871 872 if (memcmp(ip, old_insns, RV_FENTRY_NBYTES)) 873 return -EFAULT; 874 875 is_call = new_t == BPF_MOD_CALL; 876 ret = gen_jump_or_nops(new_addr, ip, new_insns, is_call); 877 if (ret) 878 return ret; 879 880 cpus_read_lock(); 881 mutex_lock(&text_mutex); 882 if (memcmp(ip, new_insns, RV_FENTRY_NBYTES)) 883 ret = patch_text(ip, new_insns, RV_FENTRY_NBYTES); 884 mutex_unlock(&text_mutex); 885 cpus_read_unlock(); 886 887 return ret; 888 } 889 890 static void store_args(int nr_arg_slots, int args_off, struct rv_jit_context *ctx) 891 { 892 int i; 893 894 for (i = 0; i < nr_arg_slots; i++) { 895 if (i < RV_MAX_REG_ARGS) { 896 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx); 897 } else { 898 /* skip slots for T0 and FP of traced function */ 899 emit_ld(RV_REG_T1, 16 + (i - RV_MAX_REG_ARGS) * 8, RV_REG_FP, ctx); 900 emit_sd(RV_REG_FP, -args_off, RV_REG_T1, ctx); 901 } 902 args_off -= 8; 903 } 904 } 905 906 static void restore_args(int nr_reg_args, int args_off, struct rv_jit_context *ctx) 907 { 908 int i; 909 910 for (i = 0; i < nr_reg_args; i++) { 911 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx); 912 args_off -= 8; 913 } 914 } 915 916 static void restore_stack_args(int nr_stack_args, int args_off, int stk_arg_off, 917 struct rv_jit_context *ctx) 918 { 919 int i; 920 921 for (i = 0; i < nr_stack_args; i++) { 922 emit_ld(RV_REG_T1, -(args_off - RV_MAX_REG_ARGS * 8), RV_REG_FP, ctx); 923 emit_sd(RV_REG_FP, -stk_arg_off, RV_REG_T1, ctx); 924 args_off -= 8; 925 stk_arg_off -= 8; 926 } 927 } 928 929 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off, 930 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx) 931 { 932 int ret, branch_off; 933 struct bpf_prog *p = l->link.prog; 934 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 935 936 if (l->cookie) { 937 emit_imm(RV_REG_T1, l->cookie, ctx); 938 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx); 939 } else { 940 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx); 941 } 942 943 /* arg1: prog */ 944 emit_imm(RV_REG_A0, (const s64)p, ctx); 945 /* arg2: &run_ctx */ 946 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx); 947 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx); 948 if (ret) 949 return ret; 950 951 /* store prog start time */ 952 emit_mv(RV_REG_S1, RV_REG_A0, ctx); 953 954 /* if (__bpf_prog_enter(prog) == 0) 955 * goto skip_exec_of_prog; 956 */ 957 branch_off = ctx->ninsns; 958 /* nop reserved for conditional jump */ 959 emit(rv_nop(), ctx); 960 961 /* arg1: &args_off */ 962 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx); 963 if (!p->jited) 964 /* arg2: progs[i]->insnsi for interpreter */ 965 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx); 966 ret = emit_call((const u64)p->bpf_func, true, ctx); 967 if (ret) 968 return ret; 969 970 if (save_ret) { 971 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 972 emit_sd(RV_REG_FP, -(retval_off - 8), regmap[BPF_REG_0], ctx); 973 } 974 975 /* update branch with beqz */ 976 if (ctx->insns) { 977 int offset = ninsns_rvoff(ctx->ninsns - branch_off); 978 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1); 979 *(u32 *)(ctx->insns + branch_off) = insn; 980 } 981 982 /* arg1: prog */ 983 emit_imm(RV_REG_A0, (const s64)p, ctx); 984 /* arg2: prog start time */ 985 emit_mv(RV_REG_A1, RV_REG_S1, ctx); 986 /* arg3: &run_ctx */ 987 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx); 988 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx); 989 990 return ret; 991 } 992 993 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, 994 const struct btf_func_model *m, 995 struct bpf_tramp_links *tlinks, 996 void *func_addr, u32 flags, 997 struct rv_jit_context *ctx) 998 { 999 int i, ret, offset; 1000 int *branches_off = NULL; 1001 int stack_size = 0, nr_arg_slots = 0; 1002 int retval_off, args_off, nregs_off, ip_off, run_ctx_off, sreg_off, stk_arg_off; 1003 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 1004 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 1005 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 1006 bool is_struct_ops = flags & BPF_TRAMP_F_INDIRECT; 1007 void *orig_call = func_addr; 1008 bool save_ret; 1009 u32 insn; 1010 1011 /* Two types of generated trampoline stack layout: 1012 * 1013 * 1. trampoline called from function entry 1014 * -------------------------------------- 1015 * FP + 8 [ RA to parent func ] return address to parent 1016 * function 1017 * FP + 0 [ FP of parent func ] frame pointer of parent 1018 * function 1019 * FP - 8 [ T0 to traced func ] return address of traced 1020 * function 1021 * FP - 16 [ FP of traced func ] frame pointer of traced 1022 * function 1023 * -------------------------------------- 1024 * 1025 * 2. trampoline called directly 1026 * -------------------------------------- 1027 * FP - 8 [ RA to caller func ] return address to caller 1028 * function 1029 * FP - 16 [ FP of caller func ] frame pointer of caller 1030 * function 1031 * -------------------------------------- 1032 * 1033 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 1034 * BPF_TRAMP_F_RET_FENTRY_RET 1035 * [ argN ] 1036 * [ ... ] 1037 * FP - args_off [ arg1 ] 1038 * 1039 * FP - nregs_off [ regs count ] 1040 * 1041 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG 1042 * 1043 * FP - run_ctx_off [ bpf_tramp_run_ctx ] 1044 * 1045 * FP - sreg_off [ callee saved reg ] 1046 * 1047 * [ pads ] pads for 16 bytes alignment 1048 * 1049 * [ stack_argN ] 1050 * [ ... ] 1051 * FP - stk_arg_off [ stack_arg1 ] BPF_TRAMP_F_CALL_ORIG 1052 */ 1053 1054 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY)) 1055 return -ENOTSUPP; 1056 1057 if (m->nr_args > MAX_BPF_FUNC_ARGS) 1058 return -ENOTSUPP; 1059 1060 for (i = 0; i < m->nr_args; i++) 1061 nr_arg_slots += round_up(m->arg_size[i], 8) / 8; 1062 1063 /* room of trampoline frame to store return address and frame pointer */ 1064 stack_size += 16; 1065 1066 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 1067 if (save_ret) 1068 stack_size += 16; /* Save both A5 (BPF R0) and A0 */ 1069 retval_off = stack_size; 1070 1071 stack_size += nr_arg_slots * 8; 1072 args_off = stack_size; 1073 1074 stack_size += 8; 1075 nregs_off = stack_size; 1076 1077 if (flags & BPF_TRAMP_F_IP_ARG) { 1078 stack_size += 8; 1079 ip_off = stack_size; 1080 } 1081 1082 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 1083 run_ctx_off = stack_size; 1084 1085 stack_size += 8; 1086 sreg_off = stack_size; 1087 1088 if ((flags & BPF_TRAMP_F_CALL_ORIG) && (nr_arg_slots - RV_MAX_REG_ARGS > 0)) 1089 stack_size += (nr_arg_slots - RV_MAX_REG_ARGS) * 8; 1090 1091 stack_size = round_up(stack_size, STACK_ALIGN); 1092 1093 /* room for args on stack must be at the top of stack */ 1094 stk_arg_off = stack_size; 1095 1096 if (!is_struct_ops) { 1097 /* For the trampoline called from function entry, 1098 * the frame of traced function and the frame of 1099 * trampoline need to be considered. 1100 */ 1101 emit_addi(RV_REG_SP, RV_REG_SP, -16, ctx); 1102 emit_sd(RV_REG_SP, 8, RV_REG_RA, ctx); 1103 emit_sd(RV_REG_SP, 0, RV_REG_FP, ctx); 1104 emit_addi(RV_REG_FP, RV_REG_SP, 16, ctx); 1105 1106 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 1107 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_T0, ctx); 1108 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 1109 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 1110 } else { 1111 /* emit kcfi hash */ 1112 emit_kcfi(cfi_get_func_hash(func_addr), ctx); 1113 /* For the trampoline called directly, just handle 1114 * the frame of trampoline. 1115 */ 1116 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 1117 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_RA, ctx); 1118 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 1119 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 1120 } 1121 1122 /* callee saved register S1 to pass start time */ 1123 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx); 1124 1125 /* store ip address of the traced function */ 1126 if (flags & BPF_TRAMP_F_IP_ARG) { 1127 emit_imm(RV_REG_T1, (const s64)func_addr, ctx); 1128 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx); 1129 } 1130 1131 emit_li(RV_REG_T1, nr_arg_slots, ctx); 1132 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx); 1133 1134 store_args(nr_arg_slots, args_off, ctx); 1135 1136 /* skip to actual body of traced function */ 1137 if (flags & BPF_TRAMP_F_ORIG_STACK) 1138 orig_call += RV_FENTRY_NINSNS * 4; 1139 1140 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1141 emit_imm(RV_REG_A0, ctx->insns ? (const s64)im : RV_MAX_COUNT_IMM, ctx); 1142 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 for (i = 0; i < fentry->nr_links; i++) { 1148 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off, 1149 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx); 1150 if (ret) 1151 return ret; 1152 } 1153 1154 if (fmod_ret->nr_links) { 1155 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL); 1156 if (!branches_off) 1157 return -ENOMEM; 1158 1159 /* cleanup to avoid garbage return value confusion */ 1160 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx); 1161 for (i = 0; i < fmod_ret->nr_links; i++) { 1162 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off, 1163 run_ctx_off, true, ctx); 1164 if (ret) 1165 goto out; 1166 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx); 1167 branches_off[i] = ctx->ninsns; 1168 /* nop reserved for conditional jump */ 1169 emit(rv_nop(), ctx); 1170 } 1171 } 1172 1173 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1174 restore_args(min_t(int, nr_arg_slots, RV_MAX_REG_ARGS), args_off, ctx); 1175 restore_stack_args(nr_arg_slots - RV_MAX_REG_ARGS, args_off, stk_arg_off, ctx); 1176 ret = emit_call((const u64)orig_call, true, ctx); 1177 if (ret) 1178 goto out; 1179 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 1180 emit_sd(RV_REG_FP, -(retval_off - 8), regmap[BPF_REG_0], ctx); 1181 im->ip_after_call = ctx->ro_insns + ctx->ninsns; 1182 /* 2 nops reserved for auipc+jalr pair */ 1183 emit(rv_nop(), ctx); 1184 emit(rv_nop(), ctx); 1185 } 1186 1187 /* update branches saved in invoke_bpf_mod_ret with bnez */ 1188 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) { 1189 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]); 1190 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1); 1191 *(u32 *)(ctx->insns + branches_off[i]) = insn; 1192 } 1193 1194 for (i = 0; i < fexit->nr_links; i++) { 1195 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off, 1196 run_ctx_off, false, ctx); 1197 if (ret) 1198 goto out; 1199 } 1200 1201 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1202 im->ip_epilogue = ctx->ro_insns + ctx->ninsns; 1203 emit_imm(RV_REG_A0, ctx->insns ? (const s64)im : RV_MAX_COUNT_IMM, ctx); 1204 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx); 1205 if (ret) 1206 goto out; 1207 } 1208 1209 if (flags & BPF_TRAMP_F_RESTORE_REGS) 1210 restore_args(min_t(int, nr_arg_slots, RV_MAX_REG_ARGS), args_off, ctx); 1211 1212 if (save_ret) { 1213 emit_ld(regmap[BPF_REG_0], -(retval_off - 8), RV_REG_FP, ctx); 1214 if (is_struct_ops) { 1215 ret = sign_extend(RV_REG_A0, regmap[BPF_REG_0], m->ret_size, 1216 m->ret_flags & BTF_FMODEL_SIGNED_ARG, ctx); 1217 if (ret) 1218 goto out; 1219 } else { 1220 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx); 1221 } 1222 } 1223 1224 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); 1225 1226 if (!is_struct_ops) { 1227 /* trampoline called from function entry */ 1228 emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); 1229 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1230 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1231 1232 emit_ld(RV_REG_RA, 8, RV_REG_SP, ctx); 1233 emit_ld(RV_REG_FP, 0, RV_REG_SP, ctx); 1234 emit_addi(RV_REG_SP, RV_REG_SP, 16, ctx); 1235 1236 if (flags & BPF_TRAMP_F_SKIP_FRAME) 1237 /* return to parent function */ 1238 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1239 else 1240 /* return to traced function */ 1241 emit_jalr(RV_REG_ZERO, RV_REG_T0, 0, ctx); 1242 } else { 1243 /* trampoline called directly */ 1244 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx); 1245 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1246 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1247 1248 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1249 } 1250 1251 ret = ctx->ninsns; 1252 out: 1253 kfree(branches_off); 1254 return ret; 1255 } 1256 1257 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 1258 struct bpf_tramp_links *tlinks, void *func_addr) 1259 { 1260 struct bpf_tramp_image im; 1261 struct rv_jit_context ctx; 1262 int ret; 1263 1264 ctx.ninsns = 0; 1265 ctx.insns = NULL; 1266 ctx.ro_insns = NULL; 1267 ret = __arch_prepare_bpf_trampoline(&im, m, tlinks, func_addr, flags, &ctx); 1268 1269 return ret < 0 ? ret : ninsns_rvoff(ctx.ninsns); 1270 } 1271 1272 void *arch_alloc_bpf_trampoline(unsigned int size) 1273 { 1274 return bpf_prog_pack_alloc(size, bpf_fill_ill_insns); 1275 } 1276 1277 void arch_free_bpf_trampoline(void *image, unsigned int size) 1278 { 1279 bpf_prog_pack_free(image, size); 1280 } 1281 1282 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, 1283 void *ro_image_end, const struct btf_func_model *m, 1284 u32 flags, struct bpf_tramp_links *tlinks, 1285 void *func_addr) 1286 { 1287 int ret; 1288 void *image, *res; 1289 struct rv_jit_context ctx; 1290 u32 size = ro_image_end - ro_image; 1291 1292 image = kvmalloc(size, GFP_KERNEL); 1293 if (!image) 1294 return -ENOMEM; 1295 1296 ctx.ninsns = 0; 1297 ctx.insns = image; 1298 ctx.ro_insns = ro_image; 1299 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1300 if (ret < 0) 1301 goto out; 1302 1303 if (WARN_ON(size < ninsns_rvoff(ctx.ninsns))) { 1304 ret = -E2BIG; 1305 goto out; 1306 } 1307 1308 res = bpf_arch_text_copy(ro_image, image, size); 1309 if (IS_ERR(res)) { 1310 ret = PTR_ERR(res); 1311 goto out; 1312 } 1313 1314 out: 1315 kvfree(image); 1316 return ret < 0 ? ret : size; 1317 } 1318 1319 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1320 bool extra_pass) 1321 { 1322 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || 1323 BPF_CLASS(insn->code) == BPF_JMP; 1324 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; 1325 struct bpf_prog_aux *aux = ctx->prog->aux; 1326 u8 rd = -1, rs = -1, code = insn->code; 1327 s16 off = insn->off; 1328 s32 imm = insn->imm; 1329 1330 init_regs(&rd, &rs, insn, ctx); 1331 1332 switch (code) { 1333 /* dst = src */ 1334 case BPF_ALU | BPF_MOV | BPF_X: 1335 case BPF_ALU64 | BPF_MOV | BPF_X: 1336 if (insn_is_cast_user(insn)) { 1337 emit_mv(RV_REG_T1, rs, ctx); 1338 emit_zextw(RV_REG_T1, RV_REG_T1, ctx); 1339 emit_imm(rd, (ctx->user_vm_start >> 32) << 32, ctx); 1340 emit(rv_beq(RV_REG_T1, RV_REG_ZERO, 4), ctx); 1341 emit_or(RV_REG_T1, rd, RV_REG_T1, ctx); 1342 emit_mv(rd, RV_REG_T1, ctx); 1343 break; 1344 } else if (insn_is_mov_percpu_addr(insn)) { 1345 if (rd != rs) 1346 emit_mv(rd, rs, ctx); 1347 #ifdef CONFIG_SMP 1348 /* Load current CPU number in T1 */ 1349 emit_lw(RV_REG_T1, offsetof(struct thread_info, cpu), 1350 RV_REG_TP, ctx); 1351 /* Load address of __per_cpu_offset array in T2 */ 1352 emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); 1353 /* Get address of __per_cpu_offset[cpu] in T1 */ 1354 emit_sh3add(RV_REG_T1, RV_REG_T1, RV_REG_T2, ctx); 1355 /* Load __per_cpu_offset[cpu] in T1 */ 1356 emit_ld(RV_REG_T1, 0, RV_REG_T1, ctx); 1357 /* Add the offset to Rd */ 1358 emit_add(rd, rd, RV_REG_T1, ctx); 1359 #endif 1360 } 1361 if (imm == 1) { 1362 /* Special mov32 for zext */ 1363 emit_zextw(rd, rd, ctx); 1364 break; 1365 } 1366 switch (insn->off) { 1367 case 0: 1368 emit_mv(rd, rs, ctx); 1369 break; 1370 case 8: 1371 emit_sextb(rd, rs, ctx); 1372 break; 1373 case 16: 1374 emit_sexth(rd, rs, ctx); 1375 break; 1376 case 32: 1377 emit_sextw(rd, rs, ctx); 1378 break; 1379 } 1380 if (!is64 && !aux->verifier_zext) 1381 emit_zextw(rd, rd, ctx); 1382 break; 1383 1384 /* dst = dst OP src */ 1385 case BPF_ALU | BPF_ADD | BPF_X: 1386 case BPF_ALU64 | BPF_ADD | BPF_X: 1387 emit_add(rd, rd, rs, ctx); 1388 if (!is64 && !aux->verifier_zext) 1389 emit_zextw(rd, rd, ctx); 1390 break; 1391 case BPF_ALU | BPF_SUB | BPF_X: 1392 case BPF_ALU64 | BPF_SUB | BPF_X: 1393 if (is64) 1394 emit_sub(rd, rd, rs, ctx); 1395 else 1396 emit_subw(rd, rd, rs, ctx); 1397 1398 if (!is64 && !aux->verifier_zext) 1399 emit_zextw(rd, rd, ctx); 1400 break; 1401 case BPF_ALU | BPF_AND | BPF_X: 1402 case BPF_ALU64 | BPF_AND | BPF_X: 1403 emit_and(rd, rd, rs, ctx); 1404 if (!is64 && !aux->verifier_zext) 1405 emit_zextw(rd, rd, ctx); 1406 break; 1407 case BPF_ALU | BPF_OR | BPF_X: 1408 case BPF_ALU64 | BPF_OR | BPF_X: 1409 emit_or(rd, rd, rs, ctx); 1410 if (!is64 && !aux->verifier_zext) 1411 emit_zextw(rd, rd, ctx); 1412 break; 1413 case BPF_ALU | BPF_XOR | BPF_X: 1414 case BPF_ALU64 | BPF_XOR | BPF_X: 1415 emit_xor(rd, rd, rs, ctx); 1416 if (!is64 && !aux->verifier_zext) 1417 emit_zextw(rd, rd, ctx); 1418 break; 1419 case BPF_ALU | BPF_MUL | BPF_X: 1420 case BPF_ALU64 | BPF_MUL | BPF_X: 1421 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); 1422 if (!is64 && !aux->verifier_zext) 1423 emit_zextw(rd, rd, ctx); 1424 break; 1425 case BPF_ALU | BPF_DIV | BPF_X: 1426 case BPF_ALU64 | BPF_DIV | BPF_X: 1427 if (off) 1428 emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx); 1429 else 1430 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); 1431 if (!is64 && !aux->verifier_zext) 1432 emit_zextw(rd, rd, ctx); 1433 break; 1434 case BPF_ALU | BPF_MOD | BPF_X: 1435 case BPF_ALU64 | BPF_MOD | BPF_X: 1436 if (off) 1437 emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx); 1438 else 1439 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); 1440 if (!is64 && !aux->verifier_zext) 1441 emit_zextw(rd, rd, ctx); 1442 break; 1443 case BPF_ALU | BPF_LSH | BPF_X: 1444 case BPF_ALU64 | BPF_LSH | BPF_X: 1445 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); 1446 if (!is64 && !aux->verifier_zext) 1447 emit_zextw(rd, rd, ctx); 1448 break; 1449 case BPF_ALU | BPF_RSH | BPF_X: 1450 case BPF_ALU64 | BPF_RSH | BPF_X: 1451 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); 1452 if (!is64 && !aux->verifier_zext) 1453 emit_zextw(rd, rd, ctx); 1454 break; 1455 case BPF_ALU | BPF_ARSH | BPF_X: 1456 case BPF_ALU64 | BPF_ARSH | BPF_X: 1457 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); 1458 if (!is64 && !aux->verifier_zext) 1459 emit_zextw(rd, rd, ctx); 1460 break; 1461 1462 /* dst = -dst */ 1463 case BPF_ALU | BPF_NEG: 1464 case BPF_ALU64 | BPF_NEG: 1465 emit_sub(rd, RV_REG_ZERO, rd, ctx); 1466 if (!is64 && !aux->verifier_zext) 1467 emit_zextw(rd, rd, ctx); 1468 break; 1469 1470 /* dst = BSWAP##imm(dst) */ 1471 case BPF_ALU | BPF_END | BPF_FROM_LE: 1472 switch (imm) { 1473 case 16: 1474 emit_zexth(rd, rd, ctx); 1475 break; 1476 case 32: 1477 if (!aux->verifier_zext) 1478 emit_zextw(rd, rd, ctx); 1479 break; 1480 case 64: 1481 /* Do nothing */ 1482 break; 1483 } 1484 break; 1485 case BPF_ALU | BPF_END | BPF_FROM_BE: 1486 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1487 emit_bswap(rd, imm, ctx); 1488 break; 1489 1490 /* dst = imm */ 1491 case BPF_ALU | BPF_MOV | BPF_K: 1492 case BPF_ALU64 | BPF_MOV | BPF_K: 1493 emit_imm(rd, imm, ctx); 1494 if (!is64 && !aux->verifier_zext) 1495 emit_zextw(rd, rd, ctx); 1496 break; 1497 1498 /* dst = dst OP imm */ 1499 case BPF_ALU | BPF_ADD | BPF_K: 1500 case BPF_ALU64 | BPF_ADD | BPF_K: 1501 if (is_12b_int(imm)) { 1502 emit_addi(rd, rd, imm, ctx); 1503 } else { 1504 emit_imm(RV_REG_T1, imm, ctx); 1505 emit_add(rd, rd, RV_REG_T1, ctx); 1506 } 1507 if (!is64 && !aux->verifier_zext) 1508 emit_zextw(rd, rd, ctx); 1509 break; 1510 case BPF_ALU | BPF_SUB | BPF_K: 1511 case BPF_ALU64 | BPF_SUB | BPF_K: 1512 if (is_12b_int(-imm)) { 1513 emit_addi(rd, rd, -imm, ctx); 1514 } else { 1515 emit_imm(RV_REG_T1, imm, ctx); 1516 emit_sub(rd, rd, RV_REG_T1, ctx); 1517 } 1518 if (!is64 && !aux->verifier_zext) 1519 emit_zextw(rd, rd, ctx); 1520 break; 1521 case BPF_ALU | BPF_AND | BPF_K: 1522 case BPF_ALU64 | BPF_AND | BPF_K: 1523 if (is_12b_int(imm)) { 1524 emit_andi(rd, rd, imm, ctx); 1525 } else { 1526 emit_imm(RV_REG_T1, imm, ctx); 1527 emit_and(rd, rd, RV_REG_T1, ctx); 1528 } 1529 if (!is64 && !aux->verifier_zext) 1530 emit_zextw(rd, rd, ctx); 1531 break; 1532 case BPF_ALU | BPF_OR | BPF_K: 1533 case BPF_ALU64 | BPF_OR | BPF_K: 1534 if (is_12b_int(imm)) { 1535 emit(rv_ori(rd, rd, imm), ctx); 1536 } else { 1537 emit_imm(RV_REG_T1, imm, ctx); 1538 emit_or(rd, rd, RV_REG_T1, ctx); 1539 } 1540 if (!is64 && !aux->verifier_zext) 1541 emit_zextw(rd, rd, ctx); 1542 break; 1543 case BPF_ALU | BPF_XOR | BPF_K: 1544 case BPF_ALU64 | BPF_XOR | BPF_K: 1545 if (is_12b_int(imm)) { 1546 emit(rv_xori(rd, rd, imm), ctx); 1547 } else { 1548 emit_imm(RV_REG_T1, imm, ctx); 1549 emit_xor(rd, rd, RV_REG_T1, ctx); 1550 } 1551 if (!is64 && !aux->verifier_zext) 1552 emit_zextw(rd, rd, ctx); 1553 break; 1554 case BPF_ALU | BPF_MUL | BPF_K: 1555 case BPF_ALU64 | BPF_MUL | BPF_K: 1556 emit_imm(RV_REG_T1, imm, ctx); 1557 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : 1558 rv_mulw(rd, rd, RV_REG_T1), ctx); 1559 if (!is64 && !aux->verifier_zext) 1560 emit_zextw(rd, rd, ctx); 1561 break; 1562 case BPF_ALU | BPF_DIV | BPF_K: 1563 case BPF_ALU64 | BPF_DIV | BPF_K: 1564 emit_imm(RV_REG_T1, imm, ctx); 1565 if (off) 1566 emit(is64 ? rv_div(rd, rd, RV_REG_T1) : 1567 rv_divw(rd, rd, RV_REG_T1), ctx); 1568 else 1569 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : 1570 rv_divuw(rd, rd, RV_REG_T1), ctx); 1571 if (!is64 && !aux->verifier_zext) 1572 emit_zextw(rd, rd, ctx); 1573 break; 1574 case BPF_ALU | BPF_MOD | BPF_K: 1575 case BPF_ALU64 | BPF_MOD | BPF_K: 1576 emit_imm(RV_REG_T1, imm, ctx); 1577 if (off) 1578 emit(is64 ? rv_rem(rd, rd, RV_REG_T1) : 1579 rv_remw(rd, rd, RV_REG_T1), ctx); 1580 else 1581 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : 1582 rv_remuw(rd, rd, RV_REG_T1), ctx); 1583 if (!is64 && !aux->verifier_zext) 1584 emit_zextw(rd, rd, ctx); 1585 break; 1586 case BPF_ALU | BPF_LSH | BPF_K: 1587 case BPF_ALU64 | BPF_LSH | BPF_K: 1588 emit_slli(rd, rd, imm, ctx); 1589 1590 if (!is64 && !aux->verifier_zext) 1591 emit_zextw(rd, rd, ctx); 1592 break; 1593 case BPF_ALU | BPF_RSH | BPF_K: 1594 case BPF_ALU64 | BPF_RSH | BPF_K: 1595 if (is64) 1596 emit_srli(rd, rd, imm, ctx); 1597 else 1598 emit(rv_srliw(rd, rd, imm), ctx); 1599 1600 if (!is64 && !aux->verifier_zext) 1601 emit_zextw(rd, rd, ctx); 1602 break; 1603 case BPF_ALU | BPF_ARSH | BPF_K: 1604 case BPF_ALU64 | BPF_ARSH | BPF_K: 1605 if (is64) 1606 emit_srai(rd, rd, imm, ctx); 1607 else 1608 emit(rv_sraiw(rd, rd, imm), ctx); 1609 1610 if (!is64 && !aux->verifier_zext) 1611 emit_zextw(rd, rd, ctx); 1612 break; 1613 1614 /* JUMP off */ 1615 case BPF_JMP | BPF_JA: 1616 case BPF_JMP32 | BPF_JA: 1617 if (BPF_CLASS(code) == BPF_JMP) 1618 rvoff = rv_offset(i, off, ctx); 1619 else 1620 rvoff = rv_offset(i, imm, ctx); 1621 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1622 if (ret) 1623 return ret; 1624 break; 1625 1626 /* IF (dst COND src) JUMP off */ 1627 case BPF_JMP | BPF_JEQ | BPF_X: 1628 case BPF_JMP32 | BPF_JEQ | BPF_X: 1629 case BPF_JMP | BPF_JGT | BPF_X: 1630 case BPF_JMP32 | BPF_JGT | BPF_X: 1631 case BPF_JMP | BPF_JLT | BPF_X: 1632 case BPF_JMP32 | BPF_JLT | BPF_X: 1633 case BPF_JMP | BPF_JGE | BPF_X: 1634 case BPF_JMP32 | BPF_JGE | BPF_X: 1635 case BPF_JMP | BPF_JLE | BPF_X: 1636 case BPF_JMP32 | BPF_JLE | BPF_X: 1637 case BPF_JMP | BPF_JNE | BPF_X: 1638 case BPF_JMP32 | BPF_JNE | BPF_X: 1639 case BPF_JMP | BPF_JSGT | BPF_X: 1640 case BPF_JMP32 | BPF_JSGT | BPF_X: 1641 case BPF_JMP | BPF_JSLT | BPF_X: 1642 case BPF_JMP32 | BPF_JSLT | BPF_X: 1643 case BPF_JMP | BPF_JSGE | BPF_X: 1644 case BPF_JMP32 | BPF_JSGE | BPF_X: 1645 case BPF_JMP | BPF_JSLE | BPF_X: 1646 case BPF_JMP32 | BPF_JSLE | BPF_X: 1647 case BPF_JMP | BPF_JSET | BPF_X: 1648 case BPF_JMP32 | BPF_JSET | BPF_X: 1649 rvoff = rv_offset(i, off, ctx); 1650 if (!is64) { 1651 s = ctx->ninsns; 1652 if (is_signed_bpf_cond(BPF_OP(code))) { 1653 emit_sextw_alt(&rs, RV_REG_T1, ctx); 1654 emit_sextw_alt(&rd, RV_REG_T2, ctx); 1655 } else { 1656 emit_zextw_alt(&rs, RV_REG_T1, ctx); 1657 emit_zextw_alt(&rd, RV_REG_T2, ctx); 1658 } 1659 e = ctx->ninsns; 1660 1661 /* Adjust for extra insns */ 1662 rvoff -= ninsns_rvoff(e - s); 1663 } 1664 1665 if (BPF_OP(code) == BPF_JSET) { 1666 /* Adjust for and */ 1667 rvoff -= 4; 1668 emit_and(RV_REG_T1, rd, rs, ctx); 1669 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1670 } else { 1671 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1672 } 1673 break; 1674 1675 /* IF (dst COND imm) JUMP off */ 1676 case BPF_JMP | BPF_JEQ | BPF_K: 1677 case BPF_JMP32 | BPF_JEQ | BPF_K: 1678 case BPF_JMP | BPF_JGT | BPF_K: 1679 case BPF_JMP32 | BPF_JGT | BPF_K: 1680 case BPF_JMP | BPF_JLT | BPF_K: 1681 case BPF_JMP32 | BPF_JLT | BPF_K: 1682 case BPF_JMP | BPF_JGE | BPF_K: 1683 case BPF_JMP32 | BPF_JGE | BPF_K: 1684 case BPF_JMP | BPF_JLE | BPF_K: 1685 case BPF_JMP32 | BPF_JLE | BPF_K: 1686 case BPF_JMP | BPF_JNE | BPF_K: 1687 case BPF_JMP32 | BPF_JNE | BPF_K: 1688 case BPF_JMP | BPF_JSGT | BPF_K: 1689 case BPF_JMP32 | BPF_JSGT | BPF_K: 1690 case BPF_JMP | BPF_JSLT | BPF_K: 1691 case BPF_JMP32 | BPF_JSLT | BPF_K: 1692 case BPF_JMP | BPF_JSGE | BPF_K: 1693 case BPF_JMP32 | BPF_JSGE | BPF_K: 1694 case BPF_JMP | BPF_JSLE | BPF_K: 1695 case BPF_JMP32 | BPF_JSLE | BPF_K: 1696 rvoff = rv_offset(i, off, ctx); 1697 s = ctx->ninsns; 1698 if (imm) 1699 emit_imm(RV_REG_T1, imm, ctx); 1700 rs = imm ? RV_REG_T1 : RV_REG_ZERO; 1701 if (!is64) { 1702 if (is_signed_bpf_cond(BPF_OP(code))) { 1703 emit_sextw_alt(&rd, RV_REG_T2, ctx); 1704 /* rs has been sign extended */ 1705 } else { 1706 emit_zextw_alt(&rd, RV_REG_T2, ctx); 1707 if (imm) 1708 emit_zextw(rs, rs, ctx); 1709 } 1710 } 1711 e = ctx->ninsns; 1712 1713 /* Adjust for extra insns */ 1714 rvoff -= ninsns_rvoff(e - s); 1715 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1716 break; 1717 1718 case BPF_JMP | BPF_JSET | BPF_K: 1719 case BPF_JMP32 | BPF_JSET | BPF_K: 1720 rvoff = rv_offset(i, off, ctx); 1721 s = ctx->ninsns; 1722 if (is_12b_int(imm)) { 1723 emit_andi(RV_REG_T1, rd, imm, ctx); 1724 } else { 1725 emit_imm(RV_REG_T1, imm, ctx); 1726 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); 1727 } 1728 /* For jset32, we should clear the upper 32 bits of t1, but 1729 * sign-extension is sufficient here and saves one instruction, 1730 * as t1 is used only in comparison against zero. 1731 */ 1732 if (!is64 && imm < 0) 1733 emit_sextw(RV_REG_T1, RV_REG_T1, ctx); 1734 e = ctx->ninsns; 1735 rvoff -= ninsns_rvoff(e - s); 1736 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1737 break; 1738 1739 /* function call */ 1740 case BPF_JMP | BPF_CALL: 1741 { 1742 bool fixed_addr; 1743 u64 addr; 1744 1745 /* Inline calls to bpf_get_smp_processor_id() 1746 * 1747 * RV_REG_TP holds the address of the current CPU's task_struct and thread_info is 1748 * at offset 0 in task_struct. 1749 * Load cpu from thread_info: 1750 * Set R0 to ((struct thread_info *)(RV_REG_TP))->cpu 1751 * 1752 * This replicates the implementation of raw_smp_processor_id() on RISCV 1753 */ 1754 if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { 1755 /* Load current CPU number in R0 */ 1756 emit_lw(bpf_to_rv_reg(BPF_REG_0, ctx), offsetof(struct thread_info, cpu), 1757 RV_REG_TP, ctx); 1758 break; 1759 } 1760 1761 mark_call(ctx); 1762 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1763 &addr, &fixed_addr); 1764 if (ret < 0) 1765 return ret; 1766 1767 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) { 1768 const struct btf_func_model *fm; 1769 int idx; 1770 1771 fm = bpf_jit_find_kfunc_model(ctx->prog, insn); 1772 if (!fm) 1773 return -EINVAL; 1774 1775 for (idx = 0; idx < fm->nr_args; idx++) { 1776 u8 reg = bpf_to_rv_reg(BPF_REG_1 + idx, ctx); 1777 1778 if (fm->arg_size[idx] == sizeof(int)) 1779 emit_sextw(reg, reg, ctx); 1780 } 1781 } 1782 1783 ret = emit_call(addr, fixed_addr, ctx); 1784 if (ret) 1785 return ret; 1786 1787 if (insn->src_reg != BPF_PSEUDO_CALL) 1788 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx); 1789 break; 1790 } 1791 /* tail call */ 1792 case BPF_JMP | BPF_TAIL_CALL: 1793 if (emit_bpf_tail_call(i, ctx)) 1794 return -1; 1795 break; 1796 1797 /* function return */ 1798 case BPF_JMP | BPF_EXIT: 1799 if (i == ctx->prog->len - 1) 1800 break; 1801 1802 rvoff = epilogue_offset(ctx); 1803 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1804 if (ret) 1805 return ret; 1806 break; 1807 1808 /* dst = imm64 */ 1809 case BPF_LD | BPF_IMM | BPF_DW: 1810 { 1811 struct bpf_insn insn1 = insn[1]; 1812 u64 imm64; 1813 1814 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1815 if (bpf_pseudo_func(insn)) { 1816 /* fixed-length insns for extra jit pass */ 1817 ret = emit_addr(rd, imm64, extra_pass, ctx); 1818 if (ret) 1819 return ret; 1820 } else { 1821 emit_imm(rd, imm64, ctx); 1822 } 1823 1824 return 1; 1825 } 1826 1827 /* LDX: dst = *(unsigned size *)(src + off) */ 1828 case BPF_LDX | BPF_MEM | BPF_B: 1829 case BPF_LDX | BPF_MEM | BPF_H: 1830 case BPF_LDX | BPF_MEM | BPF_W: 1831 case BPF_LDX | BPF_MEM | BPF_DW: 1832 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1833 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1834 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1835 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1836 /* LDSX: dst = *(signed size *)(src + off) */ 1837 case BPF_LDX | BPF_MEMSX | BPF_B: 1838 case BPF_LDX | BPF_MEMSX | BPF_H: 1839 case BPF_LDX | BPF_MEMSX | BPF_W: 1840 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1841 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1842 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1843 /* LDX | PROBE_MEM32: dst = *(unsigned size *)(src + RV_REG_ARENA + off) */ 1844 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1845 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1846 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1847 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1848 { 1849 bool sign_ext; 1850 1851 sign_ext = BPF_MODE(insn->code) == BPF_MEMSX || 1852 BPF_MODE(insn->code) == BPF_PROBE_MEMSX; 1853 1854 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1855 emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx); 1856 rs = RV_REG_T2; 1857 } 1858 1859 emit_ldx(rd, off, rs, BPF_SIZE(code), sign_ext, ctx); 1860 1861 ret = add_exception_handler(insn, rd, ctx); 1862 if (ret) 1863 return ret; 1864 1865 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 1866 return 1; 1867 break; 1868 } 1869 1870 /* speculation barrier */ 1871 case BPF_ST | BPF_NOSPEC: 1872 break; 1873 1874 /* ST: *(size *)(dst + off) = imm */ 1875 case BPF_ST | BPF_MEM | BPF_B: 1876 case BPF_ST | BPF_MEM | BPF_H: 1877 case BPF_ST | BPF_MEM | BPF_W: 1878 case BPF_ST | BPF_MEM | BPF_DW: 1879 /* ST | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = imm */ 1880 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1881 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1882 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1883 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1884 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1885 emit_add(RV_REG_T3, rd, RV_REG_ARENA, ctx); 1886 rd = RV_REG_T3; 1887 } 1888 1889 emit_st(rd, off, imm, BPF_SIZE(code), ctx); 1890 1891 ret = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx); 1892 if (ret) 1893 return ret; 1894 break; 1895 1896 /* STX: *(size *)(dst + off) = src */ 1897 case BPF_STX | BPF_MEM | BPF_B: 1898 case BPF_STX | BPF_MEM | BPF_H: 1899 case BPF_STX | BPF_MEM | BPF_W: 1900 case BPF_STX | BPF_MEM | BPF_DW: 1901 /* STX | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = src */ 1902 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1903 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1904 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1905 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1906 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1907 emit_add(RV_REG_T2, rd, RV_REG_ARENA, ctx); 1908 rd = RV_REG_T2; 1909 } 1910 1911 emit_stx(rd, off, rs, BPF_SIZE(code), ctx); 1912 1913 ret = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx); 1914 if (ret) 1915 return ret; 1916 break; 1917 1918 /* Atomics */ 1919 case BPF_STX | BPF_ATOMIC | BPF_B: 1920 case BPF_STX | BPF_ATOMIC | BPF_H: 1921 case BPF_STX | BPF_ATOMIC | BPF_W: 1922 case BPF_STX | BPF_ATOMIC | BPF_DW: 1923 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 1924 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 1925 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 1926 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 1927 if (bpf_atomic_is_load_store(insn)) 1928 ret = emit_atomic_ld_st(rd, rs, insn, ctx); 1929 else 1930 ret = emit_atomic_rmw(rd, rs, insn, ctx); 1931 1932 ret = ret ?: add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx); 1933 if (ret) 1934 return ret; 1935 break; 1936 1937 default: 1938 pr_err("bpf-jit: unknown opcode %02x\n", code); 1939 return -EINVAL; 1940 } 1941 1942 return 0; 1943 } 1944 1945 void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog) 1946 { 1947 int i, stack_adjust = 0, store_offset, bpf_stack_adjust; 1948 1949 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, STACK_ALIGN); 1950 if (bpf_stack_adjust) 1951 mark_fp(ctx); 1952 1953 if (seen_reg(RV_REG_RA, ctx)) 1954 stack_adjust += 8; 1955 stack_adjust += 8; /* RV_REG_FP */ 1956 if (seen_reg(RV_REG_S1, ctx)) 1957 stack_adjust += 8; 1958 if (seen_reg(RV_REG_S2, ctx)) 1959 stack_adjust += 8; 1960 if (seen_reg(RV_REG_S3, ctx)) 1961 stack_adjust += 8; 1962 if (seen_reg(RV_REG_S4, ctx)) 1963 stack_adjust += 8; 1964 if (seen_reg(RV_REG_S5, ctx)) 1965 stack_adjust += 8; 1966 if (seen_reg(RV_REG_S6, ctx)) 1967 stack_adjust += 8; 1968 if (ctx->arena_vm_start) 1969 stack_adjust += 8; 1970 1971 stack_adjust = round_up(stack_adjust, STACK_ALIGN); 1972 stack_adjust += bpf_stack_adjust; 1973 1974 store_offset = stack_adjust - 8; 1975 1976 /* emit kcfi type preamble immediately before the first insn */ 1977 emit_kcfi(is_subprog ? cfi_bpf_subprog_hash : cfi_bpf_hash, ctx); 1978 1979 /* nops reserved for auipc+jalr pair */ 1980 for (i = 0; i < RV_FENTRY_NINSNS; i++) 1981 emit(rv_nop(), ctx); 1982 1983 /* First instruction is always setting the tail-call-counter 1984 * (TCC) register. This instruction is skipped for tail calls. 1985 * Force using a 4-byte (non-compressed) instruction. 1986 */ 1987 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); 1988 1989 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); 1990 1991 if (seen_reg(RV_REG_RA, ctx)) { 1992 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); 1993 store_offset -= 8; 1994 } 1995 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); 1996 store_offset -= 8; 1997 if (seen_reg(RV_REG_S1, ctx)) { 1998 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); 1999 store_offset -= 8; 2000 } 2001 if (seen_reg(RV_REG_S2, ctx)) { 2002 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); 2003 store_offset -= 8; 2004 } 2005 if (seen_reg(RV_REG_S3, ctx)) { 2006 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); 2007 store_offset -= 8; 2008 } 2009 if (seen_reg(RV_REG_S4, ctx)) { 2010 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); 2011 store_offset -= 8; 2012 } 2013 if (seen_reg(RV_REG_S5, ctx)) { 2014 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); 2015 store_offset -= 8; 2016 } 2017 if (seen_reg(RV_REG_S6, ctx)) { 2018 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); 2019 store_offset -= 8; 2020 } 2021 if (ctx->arena_vm_start) { 2022 emit_sd(RV_REG_SP, store_offset, RV_REG_ARENA, ctx); 2023 store_offset -= 8; 2024 } 2025 2026 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); 2027 2028 if (bpf_stack_adjust) 2029 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); 2030 2031 /* Program contains calls and tail calls, so RV_REG_TCC need 2032 * to be saved across calls. 2033 */ 2034 if (seen_tail_call(ctx) && seen_call(ctx)) 2035 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); 2036 2037 ctx->stack_size = stack_adjust; 2038 2039 if (ctx->arena_vm_start) 2040 emit_imm(RV_REG_ARENA, ctx->arena_vm_start, ctx); 2041 } 2042 2043 void bpf_jit_build_epilogue(struct rv_jit_context *ctx) 2044 { 2045 __build_epilogue(false, ctx); 2046 } 2047 2048 bool bpf_jit_supports_kfunc_call(void) 2049 { 2050 return true; 2051 } 2052 2053 bool bpf_jit_supports_ptr_xchg(void) 2054 { 2055 return true; 2056 } 2057 2058 bool bpf_jit_supports_arena(void) 2059 { 2060 return true; 2061 } 2062 2063 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 2064 { 2065 if (in_arena) { 2066 switch (insn->code) { 2067 case BPF_STX | BPF_ATOMIC | BPF_W: 2068 case BPF_STX | BPF_ATOMIC | BPF_DW: 2069 if (insn->imm == BPF_CMPXCHG) 2070 return rv_ext_enabled(ZACAS); 2071 break; 2072 case BPF_LDX | BPF_MEMSX | BPF_B: 2073 case BPF_LDX | BPF_MEMSX | BPF_H: 2074 case BPF_LDX | BPF_MEMSX | BPF_W: 2075 return false; 2076 } 2077 } 2078 2079 return true; 2080 } 2081 2082 bool bpf_jit_supports_percpu_insn(void) 2083 { 2084 return true; 2085 } 2086 2087 bool bpf_jit_inlines_helper_call(s32 imm) 2088 { 2089 switch (imm) { 2090 case BPF_FUNC_get_smp_processor_id: 2091 return true; 2092 default: 2093 return false; 2094 } 2095 } 2096