1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2019 Marvell. 5 * 6 */ 7 8 #ifdef CONFIG_DEBUG_FS 9 10 #include <linux/fs.h> 11 #include <linux/debugfs.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 15 #include "rvu_struct.h" 16 #include "rvu_reg.h" 17 #include "rvu.h" 18 #include "cgx.h" 19 #include "lmac_common.h" 20 #include "npc.h" 21 #include "rvu_npc_hash.h" 22 #include "mcs.h" 23 24 #include "cn20k/reg.h" 25 #include "cn20k/debugfs.h" 26 #include "cn20k/npc.h" 27 28 #define DEBUGFS_DIR_NAME "octeontx2" 29 30 enum { 31 CGX_STAT0, 32 CGX_STAT1, 33 CGX_STAT2, 34 CGX_STAT3, 35 CGX_STAT4, 36 CGX_STAT5, 37 CGX_STAT6, 38 CGX_STAT7, 39 CGX_STAT8, 40 CGX_STAT9, 41 CGX_STAT10, 42 CGX_STAT11, 43 CGX_STAT12, 44 CGX_STAT13, 45 CGX_STAT14, 46 CGX_STAT15, 47 CGX_STAT16, 48 CGX_STAT17, 49 CGX_STAT18, 50 }; 51 52 static char *cgx_rx_stats_fields[] = { 53 [CGX_STAT0] = "Received packets", 54 [CGX_STAT1] = "Octets of received packets", 55 [CGX_STAT2] = "Received PAUSE packets", 56 [CGX_STAT3] = "Received PAUSE and control packets", 57 [CGX_STAT4] = "Filtered DMAC0 (NIX-bound) packets", 58 [CGX_STAT5] = "Filtered DMAC0 (NIX-bound) octets", 59 [CGX_STAT6] = "Packets dropped due to RX FIFO full", 60 [CGX_STAT7] = "Octets dropped due to RX FIFO full", 61 [CGX_STAT8] = "Error packets", 62 [CGX_STAT9] = "Filtered DMAC1 (NCSI-bound) packets", 63 [CGX_STAT10] = "Filtered DMAC1 (NCSI-bound) octets", 64 [CGX_STAT11] = "NCSI-bound packets dropped", 65 [CGX_STAT12] = "NCSI-bound octets dropped", 66 }; 67 68 static char *cgx_tx_stats_fields[] = { 69 [CGX_STAT0] = "Packets dropped due to excessive collisions", 70 [CGX_STAT1] = "Packets dropped due to excessive deferral", 71 [CGX_STAT2] = "Multiple collisions before successful transmission", 72 [CGX_STAT3] = "Single collisions before successful transmission", 73 [CGX_STAT4] = "Total octets sent on the interface", 74 [CGX_STAT5] = "Total frames sent on the interface", 75 [CGX_STAT6] = "Packets sent with an octet count < 64", 76 [CGX_STAT7] = "Packets sent with an octet count == 64", 77 [CGX_STAT8] = "Packets sent with an octet count of 65-127", 78 [CGX_STAT9] = "Packets sent with an octet count of 128-255", 79 [CGX_STAT10] = "Packets sent with an octet count of 256-511", 80 [CGX_STAT11] = "Packets sent with an octet count of 512-1023", 81 [CGX_STAT12] = "Packets sent with an octet count of 1024-1518", 82 [CGX_STAT13] = "Packets sent with an octet count of > 1518", 83 [CGX_STAT14] = "Packets sent to a broadcast DMAC", 84 [CGX_STAT15] = "Packets sent to the multicast DMAC", 85 [CGX_STAT16] = "Transmit underflow and were truncated", 86 [CGX_STAT17] = "Control/PAUSE packets sent", 87 }; 88 89 static char *rpm_rx_stats_fields[] = { 90 "Octets of received packets", 91 "Octets of received packets with out error", 92 "Received packets with alignment errors", 93 "Control/PAUSE packets received", 94 "Packets received with Frame too long Errors", 95 "Packets received with a1nrange length Errors", 96 "Received packets", 97 "Packets received with FrameCheckSequenceErrors", 98 "Packets received with VLAN header", 99 "Error packets", 100 "Packets received with unicast DMAC", 101 "Packets received with multicast DMAC", 102 "Packets received with broadcast DMAC", 103 "Dropped packets", 104 "Total frames received on interface", 105 "Packets received with an octet count < 64", 106 "Packets received with an octet count == 64", 107 "Packets received with an octet count of 65-127", 108 "Packets received with an octet count of 128-255", 109 "Packets received with an octet count of 256-511", 110 "Packets received with an octet count of 512-1023", 111 "Packets received with an octet count of 1024-1518", 112 "Packets received with an octet count of > 1518", 113 "Oversized Packets", 114 "Jabber Packets", 115 "Fragmented Packets", 116 "CBFC(class based flow control) pause frames received for class 0", 117 "CBFC pause frames received for class 1", 118 "CBFC pause frames received for class 2", 119 "CBFC pause frames received for class 3", 120 "CBFC pause frames received for class 4", 121 "CBFC pause frames received for class 5", 122 "CBFC pause frames received for class 6", 123 "CBFC pause frames received for class 7", 124 "CBFC pause frames received for class 8", 125 "CBFC pause frames received for class 9", 126 "CBFC pause frames received for class 10", 127 "CBFC pause frames received for class 11", 128 "CBFC pause frames received for class 12", 129 "CBFC pause frames received for class 13", 130 "CBFC pause frames received for class 14", 131 "CBFC pause frames received for class 15", 132 "MAC control packets received", 133 }; 134 135 static char *rpm_tx_stats_fields[] = { 136 "Total octets sent on the interface", 137 "Total octets transmitted OK", 138 "Control/Pause frames sent", 139 "Total frames transmitted OK", 140 "Total frames sent with VLAN header", 141 "Error Packets", 142 "Packets sent to unicast DMAC", 143 "Packets sent to the multicast DMAC", 144 "Packets sent to a broadcast DMAC", 145 "Packets sent with an octet count == 64", 146 "Packets sent with an octet count of 65-127", 147 "Packets sent with an octet count of 128-255", 148 "Packets sent with an octet count of 256-511", 149 "Packets sent with an octet count of 512-1023", 150 "Packets sent with an octet count of 1024-1518", 151 "Packets sent with an octet count of > 1518", 152 "CBFC(class based flow control) pause frames transmitted for class 0", 153 "CBFC pause frames transmitted for class 1", 154 "CBFC pause frames transmitted for class 2", 155 "CBFC pause frames transmitted for class 3", 156 "CBFC pause frames transmitted for class 4", 157 "CBFC pause frames transmitted for class 5", 158 "CBFC pause frames transmitted for class 6", 159 "CBFC pause frames transmitted for class 7", 160 "CBFC pause frames transmitted for class 8", 161 "CBFC pause frames transmitted for class 9", 162 "CBFC pause frames transmitted for class 10", 163 "CBFC pause frames transmitted for class 11", 164 "CBFC pause frames transmitted for class 12", 165 "CBFC pause frames transmitted for class 13", 166 "CBFC pause frames transmitted for class 14", 167 "CBFC pause frames transmitted for class 15", 168 "MAC control packets sent", 169 "Total frames sent on the interface" 170 }; 171 172 enum cpt_eng_type { 173 CPT_AE_TYPE = 1, 174 CPT_SE_TYPE = 2, 175 CPT_IE_TYPE = 3, 176 }; 177 178 #define rvu_dbg_NULL NULL 179 #define rvu_dbg_open_NULL NULL 180 181 #define RVU_DEBUG_SEQ_FOPS(name, read_op, write_op) \ 182 static int rvu_dbg_open_##name(struct inode *inode, struct file *file) \ 183 { \ 184 return single_open(file, rvu_dbg_##read_op, inode->i_private); \ 185 } \ 186 static const struct file_operations rvu_dbg_##name##_fops = { \ 187 .owner = THIS_MODULE, \ 188 .open = rvu_dbg_open_##name, \ 189 .read = seq_read, \ 190 .write = rvu_dbg_##write_op, \ 191 .llseek = seq_lseek, \ 192 .release = single_release, \ 193 } 194 195 #define RVU_DEBUG_FOPS(name, read_op, write_op) \ 196 static const struct file_operations rvu_dbg_##name##_fops = { \ 197 .owner = THIS_MODULE, \ 198 .open = simple_open, \ 199 .read = rvu_dbg_##read_op, \ 200 .write = rvu_dbg_##write_op \ 201 } 202 203 static void print_nix_qsize(struct seq_file *filp, struct rvu_pfvf *pfvf); 204 205 static int rvu_dbg_mcs_port_stats_display(struct seq_file *filp, void *unused, int dir) 206 { 207 struct mcs *mcs = filp->private; 208 struct mcs_port_stats stats; 209 int lmac; 210 211 seq_puts(filp, "\n port stats\n"); 212 mutex_lock(&mcs->stats_lock); 213 for_each_set_bit(lmac, &mcs->hw->lmac_bmap, mcs->hw->lmac_cnt) { 214 mcs_get_port_stats(mcs, &stats, lmac, dir); 215 seq_printf(filp, "port%d: Tcam Miss: %lld\n", lmac, stats.tcam_miss_cnt); 216 seq_printf(filp, "port%d: Parser errors: %lld\n", lmac, stats.parser_err_cnt); 217 218 if (dir == MCS_RX && mcs->hw->mcs_blks > 1) 219 seq_printf(filp, "port%d: Preempt error: %lld\n", lmac, 220 stats.preempt_err_cnt); 221 if (dir == MCS_TX) 222 seq_printf(filp, "port%d: Sectag insert error: %lld\n", lmac, 223 stats.sectag_insert_err_cnt); 224 } 225 mutex_unlock(&mcs->stats_lock); 226 return 0; 227 } 228 229 static int rvu_dbg_mcs_rx_port_stats_display(struct seq_file *filp, void *unused) 230 { 231 return rvu_dbg_mcs_port_stats_display(filp, unused, MCS_RX); 232 } 233 234 RVU_DEBUG_SEQ_FOPS(mcs_rx_port_stats, mcs_rx_port_stats_display, NULL); 235 236 static int rvu_dbg_mcs_tx_port_stats_display(struct seq_file *filp, void *unused) 237 { 238 return rvu_dbg_mcs_port_stats_display(filp, unused, MCS_TX); 239 } 240 241 RVU_DEBUG_SEQ_FOPS(mcs_tx_port_stats, mcs_tx_port_stats_display, NULL); 242 243 static int rvu_dbg_mcs_sa_stats_display(struct seq_file *filp, void *unused, int dir) 244 { 245 struct mcs *mcs = filp->private; 246 struct mcs_sa_stats stats; 247 struct rsrc_bmap *map; 248 int sa_id; 249 250 if (dir == MCS_TX) { 251 map = &mcs->tx.sa; 252 mutex_lock(&mcs->stats_lock); 253 for_each_set_bit(sa_id, map->bmap, mcs->hw->sa_entries) { 254 seq_puts(filp, "\n TX SA stats\n"); 255 mcs_get_sa_stats(mcs, &stats, sa_id, MCS_TX); 256 seq_printf(filp, "sa%d: Pkts encrypted: %lld\n", sa_id, 257 stats.pkt_encrypt_cnt); 258 259 seq_printf(filp, "sa%d: Pkts protected: %lld\n", sa_id, 260 stats.pkt_protected_cnt); 261 } 262 mutex_unlock(&mcs->stats_lock); 263 return 0; 264 } 265 266 /* RX stats */ 267 map = &mcs->rx.sa; 268 mutex_lock(&mcs->stats_lock); 269 for_each_set_bit(sa_id, map->bmap, mcs->hw->sa_entries) { 270 seq_puts(filp, "\n RX SA stats\n"); 271 mcs_get_sa_stats(mcs, &stats, sa_id, MCS_RX); 272 seq_printf(filp, "sa%d: Invalid pkts: %lld\n", sa_id, stats.pkt_invalid_cnt); 273 seq_printf(filp, "sa%d: Pkts no sa error: %lld\n", sa_id, stats.pkt_nosaerror_cnt); 274 seq_printf(filp, "sa%d: Pkts not valid: %lld\n", sa_id, stats.pkt_notvalid_cnt); 275 seq_printf(filp, "sa%d: Pkts ok: %lld\n", sa_id, stats.pkt_ok_cnt); 276 seq_printf(filp, "sa%d: Pkts no sa: %lld\n", sa_id, stats.pkt_nosa_cnt); 277 } 278 mutex_unlock(&mcs->stats_lock); 279 return 0; 280 } 281 282 static int rvu_dbg_mcs_rx_sa_stats_display(struct seq_file *filp, void *unused) 283 { 284 return rvu_dbg_mcs_sa_stats_display(filp, unused, MCS_RX); 285 } 286 287 RVU_DEBUG_SEQ_FOPS(mcs_rx_sa_stats, mcs_rx_sa_stats_display, NULL); 288 289 static int rvu_dbg_mcs_tx_sa_stats_display(struct seq_file *filp, void *unused) 290 { 291 return rvu_dbg_mcs_sa_stats_display(filp, unused, MCS_TX); 292 } 293 294 RVU_DEBUG_SEQ_FOPS(mcs_tx_sa_stats, mcs_tx_sa_stats_display, NULL); 295 296 static int rvu_dbg_mcs_tx_sc_stats_display(struct seq_file *filp, void *unused) 297 { 298 struct mcs *mcs = filp->private; 299 struct mcs_sc_stats stats; 300 struct rsrc_bmap *map; 301 int sc_id; 302 303 map = &mcs->tx.sc; 304 seq_puts(filp, "\n SC stats\n"); 305 306 mutex_lock(&mcs->stats_lock); 307 for_each_set_bit(sc_id, map->bmap, mcs->hw->sc_entries) { 308 mcs_get_sc_stats(mcs, &stats, sc_id, MCS_TX); 309 seq_printf(filp, "\n=======sc%d======\n\n", sc_id); 310 seq_printf(filp, "sc%d: Pkts encrypted: %lld\n", sc_id, stats.pkt_encrypt_cnt); 311 seq_printf(filp, "sc%d: Pkts protected: %lld\n", sc_id, stats.pkt_protected_cnt); 312 313 if (mcs->hw->mcs_blks == 1) { 314 seq_printf(filp, "sc%d: Octets encrypted: %lld\n", sc_id, 315 stats.octet_encrypt_cnt); 316 seq_printf(filp, "sc%d: Octets protected: %lld\n", sc_id, 317 stats.octet_protected_cnt); 318 } 319 } 320 mutex_unlock(&mcs->stats_lock); 321 return 0; 322 } 323 324 RVU_DEBUG_SEQ_FOPS(mcs_tx_sc_stats, mcs_tx_sc_stats_display, NULL); 325 326 static int rvu_dbg_mcs_rx_sc_stats_display(struct seq_file *filp, void *unused) 327 { 328 struct mcs *mcs = filp->private; 329 struct mcs_sc_stats stats; 330 struct rsrc_bmap *map; 331 int sc_id; 332 333 map = &mcs->rx.sc; 334 seq_puts(filp, "\n SC stats\n"); 335 336 mutex_lock(&mcs->stats_lock); 337 for_each_set_bit(sc_id, map->bmap, mcs->hw->sc_entries) { 338 mcs_get_sc_stats(mcs, &stats, sc_id, MCS_RX); 339 seq_printf(filp, "\n=======sc%d======\n\n", sc_id); 340 seq_printf(filp, "sc%d: Cam hits: %lld\n", sc_id, stats.hit_cnt); 341 seq_printf(filp, "sc%d: Invalid pkts: %lld\n", sc_id, stats.pkt_invalid_cnt); 342 seq_printf(filp, "sc%d: Late pkts: %lld\n", sc_id, stats.pkt_late_cnt); 343 seq_printf(filp, "sc%d: Notvalid pkts: %lld\n", sc_id, stats.pkt_notvalid_cnt); 344 seq_printf(filp, "sc%d: Unchecked pkts: %lld\n", sc_id, stats.pkt_unchecked_cnt); 345 346 if (mcs->hw->mcs_blks > 1) { 347 seq_printf(filp, "sc%d: Delay pkts: %lld\n", sc_id, stats.pkt_delay_cnt); 348 seq_printf(filp, "sc%d: Pkts ok: %lld\n", sc_id, stats.pkt_ok_cnt); 349 } 350 if (mcs->hw->mcs_blks == 1) { 351 seq_printf(filp, "sc%d: Octets decrypted: %lld\n", sc_id, 352 stats.octet_decrypt_cnt); 353 seq_printf(filp, "sc%d: Octets validated: %lld\n", sc_id, 354 stats.octet_validate_cnt); 355 } 356 } 357 mutex_unlock(&mcs->stats_lock); 358 return 0; 359 } 360 361 RVU_DEBUG_SEQ_FOPS(mcs_rx_sc_stats, mcs_rx_sc_stats_display, NULL); 362 363 static int rvu_dbg_mcs_flowid_stats_display(struct seq_file *filp, void *unused, int dir) 364 { 365 struct mcs *mcs = filp->private; 366 struct mcs_flowid_stats stats; 367 struct rsrc_bmap *map; 368 int flow_id; 369 370 seq_puts(filp, "\n Flowid stats\n"); 371 372 if (dir == MCS_RX) 373 map = &mcs->rx.flow_ids; 374 else 375 map = &mcs->tx.flow_ids; 376 377 mutex_lock(&mcs->stats_lock); 378 for_each_set_bit(flow_id, map->bmap, mcs->hw->tcam_entries) { 379 mcs_get_flowid_stats(mcs, &stats, flow_id, dir); 380 seq_printf(filp, "Flowid%d: Hit:%lld\n", flow_id, stats.tcam_hit_cnt); 381 } 382 mutex_unlock(&mcs->stats_lock); 383 return 0; 384 } 385 386 static int rvu_dbg_mcs_tx_flowid_stats_display(struct seq_file *filp, void *unused) 387 { 388 return rvu_dbg_mcs_flowid_stats_display(filp, unused, MCS_TX); 389 } 390 391 RVU_DEBUG_SEQ_FOPS(mcs_tx_flowid_stats, mcs_tx_flowid_stats_display, NULL); 392 393 static int rvu_dbg_mcs_rx_flowid_stats_display(struct seq_file *filp, void *unused) 394 { 395 return rvu_dbg_mcs_flowid_stats_display(filp, unused, MCS_RX); 396 } 397 398 RVU_DEBUG_SEQ_FOPS(mcs_rx_flowid_stats, mcs_rx_flowid_stats_display, NULL); 399 400 static int rvu_dbg_mcs_tx_secy_stats_display(struct seq_file *filp, void *unused) 401 { 402 struct mcs *mcs = filp->private; 403 struct mcs_secy_stats stats; 404 struct rsrc_bmap *map; 405 int secy_id; 406 407 map = &mcs->tx.secy; 408 seq_puts(filp, "\n MCS TX secy stats\n"); 409 410 mutex_lock(&mcs->stats_lock); 411 for_each_set_bit(secy_id, map->bmap, mcs->hw->secy_entries) { 412 mcs_get_tx_secy_stats(mcs, &stats, secy_id); 413 seq_printf(filp, "\n=======Secy%d======\n\n", secy_id); 414 seq_printf(filp, "secy%d: Ctrl bcast pkts: %lld\n", secy_id, 415 stats.ctl_pkt_bcast_cnt); 416 seq_printf(filp, "secy%d: Ctrl Mcast pkts: %lld\n", secy_id, 417 stats.ctl_pkt_mcast_cnt); 418 seq_printf(filp, "secy%d: Ctrl ucast pkts: %lld\n", secy_id, 419 stats.ctl_pkt_ucast_cnt); 420 seq_printf(filp, "secy%d: Ctrl octets: %lld\n", secy_id, stats.ctl_octet_cnt); 421 seq_printf(filp, "secy%d: Unctrl bcast cnt: %lld\n", secy_id, 422 stats.unctl_pkt_bcast_cnt); 423 seq_printf(filp, "secy%d: Unctrl mcast pkts: %lld\n", secy_id, 424 stats.unctl_pkt_mcast_cnt); 425 seq_printf(filp, "secy%d: Unctrl ucast pkts: %lld\n", secy_id, 426 stats.unctl_pkt_ucast_cnt); 427 seq_printf(filp, "secy%d: Unctrl octets: %lld\n", secy_id, stats.unctl_octet_cnt); 428 seq_printf(filp, "secy%d: Octet encrypted: %lld\n", secy_id, 429 stats.octet_encrypted_cnt); 430 seq_printf(filp, "secy%d: octet protected: %lld\n", secy_id, 431 stats.octet_protected_cnt); 432 seq_printf(filp, "secy%d: Pkts on active sa: %lld\n", secy_id, 433 stats.pkt_noactivesa_cnt); 434 seq_printf(filp, "secy%d: Pkts too long: %lld\n", secy_id, stats.pkt_toolong_cnt); 435 seq_printf(filp, "secy%d: Pkts untagged: %lld\n", secy_id, stats.pkt_untagged_cnt); 436 } 437 mutex_unlock(&mcs->stats_lock); 438 return 0; 439 } 440 441 RVU_DEBUG_SEQ_FOPS(mcs_tx_secy_stats, mcs_tx_secy_stats_display, NULL); 442 443 static int rvu_dbg_mcs_rx_secy_stats_display(struct seq_file *filp, void *unused) 444 { 445 struct mcs *mcs = filp->private; 446 struct mcs_secy_stats stats; 447 struct rsrc_bmap *map; 448 int secy_id; 449 450 map = &mcs->rx.secy; 451 seq_puts(filp, "\n MCS secy stats\n"); 452 453 mutex_lock(&mcs->stats_lock); 454 for_each_set_bit(secy_id, map->bmap, mcs->hw->secy_entries) { 455 mcs_get_rx_secy_stats(mcs, &stats, secy_id); 456 seq_printf(filp, "\n=======Secy%d======\n\n", secy_id); 457 seq_printf(filp, "secy%d: Ctrl bcast pkts: %lld\n", secy_id, 458 stats.ctl_pkt_bcast_cnt); 459 seq_printf(filp, "secy%d: Ctrl Mcast pkts: %lld\n", secy_id, 460 stats.ctl_pkt_mcast_cnt); 461 seq_printf(filp, "secy%d: Ctrl ucast pkts: %lld\n", secy_id, 462 stats.ctl_pkt_ucast_cnt); 463 seq_printf(filp, "secy%d: Ctrl octets: %lld\n", secy_id, stats.ctl_octet_cnt); 464 seq_printf(filp, "secy%d: Unctrl bcast cnt: %lld\n", secy_id, 465 stats.unctl_pkt_bcast_cnt); 466 seq_printf(filp, "secy%d: Unctrl mcast pkts: %lld\n", secy_id, 467 stats.unctl_pkt_mcast_cnt); 468 seq_printf(filp, "secy%d: Unctrl ucast pkts: %lld\n", secy_id, 469 stats.unctl_pkt_ucast_cnt); 470 seq_printf(filp, "secy%d: Unctrl octets: %lld\n", secy_id, stats.unctl_octet_cnt); 471 seq_printf(filp, "secy%d: Octet decrypted: %lld\n", secy_id, 472 stats.octet_decrypted_cnt); 473 seq_printf(filp, "secy%d: octet validated: %lld\n", secy_id, 474 stats.octet_validated_cnt); 475 seq_printf(filp, "secy%d: Pkts on disable port: %lld\n", secy_id, 476 stats.pkt_port_disabled_cnt); 477 seq_printf(filp, "secy%d: Pkts with badtag: %lld\n", secy_id, stats.pkt_badtag_cnt); 478 seq_printf(filp, "secy%d: Pkts with no SA(sectag.tci.c=0): %lld\n", secy_id, 479 stats.pkt_nosa_cnt); 480 seq_printf(filp, "secy%d: Pkts with nosaerror: %lld\n", secy_id, 481 stats.pkt_nosaerror_cnt); 482 seq_printf(filp, "secy%d: Tagged ctrl pkts: %lld\n", secy_id, 483 stats.pkt_tagged_ctl_cnt); 484 seq_printf(filp, "secy%d: Untaged pkts: %lld\n", secy_id, stats.pkt_untaged_cnt); 485 if (mcs->hw->mcs_blks > 1) 486 seq_printf(filp, "secy%d: pkts notag: %lld\n", secy_id, 487 stats.pkt_notag_cnt); 488 else 489 seq_printf(filp, "secy%d: Ctrl pkts: %lld\n", secy_id, stats.pkt_ctl_cnt); 490 } 491 mutex_unlock(&mcs->stats_lock); 492 return 0; 493 } 494 495 RVU_DEBUG_SEQ_FOPS(mcs_rx_secy_stats, mcs_rx_secy_stats_display, NULL); 496 497 static void rvu_dbg_mcs_init(struct rvu *rvu) 498 { 499 struct mcs *mcs; 500 char dname[10]; 501 int i; 502 503 if (!rvu->mcs_blk_cnt) 504 return; 505 506 rvu->rvu_dbg.mcs_root = debugfs_create_dir("mcs", rvu->rvu_dbg.root); 507 508 for (i = 0; i < rvu->mcs_blk_cnt; i++) { 509 mcs = mcs_get_pdata(i); 510 511 sprintf(dname, "mcs%d", i); 512 rvu->rvu_dbg.mcs = debugfs_create_dir(dname, 513 rvu->rvu_dbg.mcs_root); 514 515 rvu->rvu_dbg.mcs_rx = debugfs_create_dir("rx_stats", rvu->rvu_dbg.mcs); 516 517 debugfs_create_file("flowid", 0600, rvu->rvu_dbg.mcs_rx, mcs, 518 &rvu_dbg_mcs_rx_flowid_stats_fops); 519 520 debugfs_create_file("secy", 0600, rvu->rvu_dbg.mcs_rx, mcs, 521 &rvu_dbg_mcs_rx_secy_stats_fops); 522 523 debugfs_create_file("sc", 0600, rvu->rvu_dbg.mcs_rx, mcs, 524 &rvu_dbg_mcs_rx_sc_stats_fops); 525 526 debugfs_create_file("sa", 0600, rvu->rvu_dbg.mcs_rx, mcs, 527 &rvu_dbg_mcs_rx_sa_stats_fops); 528 529 debugfs_create_file("port", 0600, rvu->rvu_dbg.mcs_rx, mcs, 530 &rvu_dbg_mcs_rx_port_stats_fops); 531 532 rvu->rvu_dbg.mcs_tx = debugfs_create_dir("tx_stats", rvu->rvu_dbg.mcs); 533 534 debugfs_create_file("flowid", 0600, rvu->rvu_dbg.mcs_tx, mcs, 535 &rvu_dbg_mcs_tx_flowid_stats_fops); 536 537 debugfs_create_file("secy", 0600, rvu->rvu_dbg.mcs_tx, mcs, 538 &rvu_dbg_mcs_tx_secy_stats_fops); 539 540 debugfs_create_file("sc", 0600, rvu->rvu_dbg.mcs_tx, mcs, 541 &rvu_dbg_mcs_tx_sc_stats_fops); 542 543 debugfs_create_file("sa", 0600, rvu->rvu_dbg.mcs_tx, mcs, 544 &rvu_dbg_mcs_tx_sa_stats_fops); 545 546 debugfs_create_file("port", 0600, rvu->rvu_dbg.mcs_tx, mcs, 547 &rvu_dbg_mcs_tx_port_stats_fops); 548 } 549 } 550 551 #define LMT_MAPTBL_ENTRY_SIZE 16 552 /* Dump LMTST map table */ 553 static ssize_t rvu_dbg_lmtst_map_table_display(struct file *filp, 554 char __user *buffer, 555 size_t count, loff_t *ppos) 556 { 557 struct rvu *rvu = filp->private_data; 558 u64 lmt_addr, val, tbl_base; 559 int pf, vf, num_vfs, hw_vfs; 560 void __iomem *lmt_map_base; 561 int apr_pfs, apr_vfs; 562 int buf_size = 10240; 563 size_t off = 0; 564 int index = 0; 565 char *buf; 566 int ret; 567 568 /* don't allow partial reads */ 569 if (*ppos != 0) 570 return 0; 571 572 buf = kzalloc(buf_size, GFP_KERNEL); 573 if (!buf) 574 return -ENOMEM; 575 576 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); 577 val = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG); 578 apr_vfs = 1 << (val & 0xF); 579 apr_pfs = 1 << ((val >> 4) & 0x7); 580 581 lmt_map_base = ioremap_wc(tbl_base, apr_pfs * apr_vfs * 582 LMT_MAPTBL_ENTRY_SIZE); 583 if (!lmt_map_base) { 584 dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); 585 kfree(buf); 586 return false; 587 } 588 589 off += scnprintf(&buf[off], buf_size - 1 - off, 590 "\n\t\t\t\t\tLmtst Map Table Entries"); 591 off += scnprintf(&buf[off], buf_size - 1 - off, 592 "\n\t\t\t\t\t======================="); 593 off += scnprintf(&buf[off], buf_size - 1 - off, "\nPcifunc\t\t\t"); 594 off += scnprintf(&buf[off], buf_size - 1 - off, "Table Index\t\t"); 595 off += scnprintf(&buf[off], buf_size - 1 - off, 596 "Lmtline Base (word 0)\t\t"); 597 off += scnprintf(&buf[off], buf_size - 1 - off, 598 "Lmt Map Entry (word 1)"); 599 off += scnprintf(&buf[off], buf_size - 1 - off, "\n"); 600 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 601 off += scnprintf(&buf[off], buf_size - 1 - off, "PF%d \t\t\t", 602 pf); 603 604 index = pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE; 605 off += scnprintf(&buf[off], buf_size - 1 - off, " 0x%llx\t\t", 606 (tbl_base + index)); 607 lmt_addr = readq(lmt_map_base + index); 608 off += scnprintf(&buf[off], buf_size - 1 - off, 609 " 0x%016llx\t\t", lmt_addr); 610 index += 8; 611 val = readq(lmt_map_base + index); 612 off += scnprintf(&buf[off], buf_size - 1 - off, " 0x%016llx\n", 613 val); 614 /* Reading num of VFs per PF */ 615 rvu_get_pf_numvfs(rvu, pf, &num_vfs, &hw_vfs); 616 for (vf = 0; vf < num_vfs; vf++) { 617 index = (pf * apr_vfs * LMT_MAPTBL_ENTRY_SIZE) + 618 ((vf + 1) * LMT_MAPTBL_ENTRY_SIZE); 619 off += scnprintf(&buf[off], buf_size - 1 - off, 620 "PF%d:VF%d \t\t", pf, vf); 621 off += scnprintf(&buf[off], buf_size - 1 - off, 622 " 0x%llx\t\t", (tbl_base + index)); 623 lmt_addr = readq(lmt_map_base + index); 624 off += scnprintf(&buf[off], buf_size - 1 - off, 625 " 0x%016llx\t\t", lmt_addr); 626 index += 8; 627 val = readq(lmt_map_base + index); 628 off += scnprintf(&buf[off], buf_size - 1 - off, 629 " 0x%016llx\n", val); 630 } 631 } 632 off += scnprintf(&buf[off], buf_size - 1 - off, "\n"); 633 634 ret = min(off, count); 635 if (copy_to_user(buffer, buf, ret)) 636 ret = -EFAULT; 637 kfree(buf); 638 639 iounmap(lmt_map_base); 640 if (ret < 0) 641 return ret; 642 643 *ppos = ret; 644 return ret; 645 } 646 647 RVU_DEBUG_FOPS(lmtst_map_table, lmtst_map_table_display, NULL); 648 649 static void get_lf_str_list(const struct rvu_block *block, int pcifunc, 650 char *lfs) 651 { 652 int lf = 0, seq = 0, len = 0, prev_lf = block->lf.max; 653 654 for_each_set_bit(lf, block->lf.bmap, block->lf.max) { 655 if (lf >= block->lf.max) 656 break; 657 658 if (block->fn_map[lf] != pcifunc) 659 continue; 660 661 if (lf == prev_lf + 1) { 662 prev_lf = lf; 663 seq = 1; 664 continue; 665 } 666 667 if (seq) 668 len += sprintf(lfs + len, "-%d,%d", prev_lf, lf); 669 else 670 len += (len ? sprintf(lfs + len, ",%d", lf) : 671 sprintf(lfs + len, "%d", lf)); 672 673 prev_lf = lf; 674 seq = 0; 675 } 676 677 if (seq) 678 len += sprintf(lfs + len, "-%d", prev_lf); 679 680 lfs[len] = '\0'; 681 } 682 683 static int get_max_column_width(struct rvu *rvu) 684 { 685 int index, pf, vf, lf_str_size = 12, buf_size = 256; 686 struct rvu_block block; 687 u16 pcifunc; 688 char *buf; 689 690 buf = kzalloc(buf_size, GFP_KERNEL); 691 if (!buf) 692 return -ENOMEM; 693 694 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 695 for (vf = 0; vf <= rvu->hw->total_vfs; vf++) { 696 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, vf); 697 if (!pcifunc) 698 continue; 699 700 for (index = 0; index < BLK_COUNT; index++) { 701 block = rvu->hw->block[index]; 702 if (!strlen(block.name)) 703 continue; 704 705 get_lf_str_list(&block, pcifunc, buf); 706 if (lf_str_size <= strlen(buf)) 707 lf_str_size = strlen(buf) + 1; 708 } 709 } 710 } 711 712 kfree(buf); 713 return lf_str_size; 714 } 715 716 /* Dumps current provisioning status of all RVU block LFs */ 717 static int rvu_dbg_rsrc_attach_status(struct seq_file *filp, void *unused) 718 { 719 struct rvu *rvu = filp->private; 720 int index, pf, vf, pcifunc; 721 struct rvu_block block; 722 int lf_str_size; 723 char *lfs; 724 725 lf_str_size = get_max_column_width(rvu); 726 if (lf_str_size < 0) 727 return lf_str_size; 728 729 lfs = kzalloc(lf_str_size, GFP_KERNEL); 730 if (!lfs) 731 return -ENOMEM; 732 733 seq_printf(filp, "%-*s", lf_str_size, "pcifunc"); 734 for (index = 0; index < BLK_COUNT; index++) 735 if (strlen(rvu->hw->block[index].name)) 736 seq_printf(filp, "%-*s", lf_str_size, 737 rvu->hw->block[index].name); 738 739 seq_putc(filp, '\n'); 740 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 741 for (vf = 0; vf <= rvu->hw->total_vfs; vf++) { 742 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, vf); 743 if (!pcifunc) 744 continue; 745 746 for (index = 0; index < BLK_COUNT; index++) { 747 block = rvu->hw->block[index]; 748 if (!strlen(block.name)) 749 continue; 750 lfs[0] = '\0'; 751 get_lf_str_list(&block, pcifunc, lfs); 752 if (strlen(lfs)) 753 break; 754 } 755 if (index == BLK_COUNT) 756 continue; 757 758 if (vf) 759 sprintf(lfs, "PF%d:VF%d", pf, vf - 1); 760 else 761 sprintf(lfs, "PF%d", pf); 762 seq_printf(filp, "%-*s", lf_str_size, lfs); 763 764 for (index = 0; index < BLK_COUNT; index++) { 765 block = rvu->hw->block[index]; 766 if (!strlen(block.name)) 767 continue; 768 769 lfs[0] = '\0'; 770 get_lf_str_list(&block, pcifunc, lfs); 771 seq_printf(filp, "%-*s", lf_str_size, lfs); 772 } 773 seq_putc(filp, '\n'); 774 } 775 } 776 777 kfree(lfs); 778 779 return 0; 780 } 781 782 RVU_DEBUG_SEQ_FOPS(rsrc_status, rsrc_attach_status, NULL); 783 784 static int rvu_dbg_rvu_pf_cgx_map_display(struct seq_file *filp, void *unused) 785 { 786 char cgx[10], lmac[10], chan[10]; 787 struct rvu *rvu = filp->private; 788 struct pci_dev *pdev = NULL; 789 struct mac_ops *mac_ops; 790 struct rvu_pfvf *pfvf; 791 int pf, domain, blkid; 792 u8 cgx_id, lmac_id; 793 u16 pcifunc; 794 u8 start; 795 796 domain = pci_domain_nr(rvu->pdev->bus); 797 mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu)); 798 /* There can be no CGX devices at all */ 799 if (!mac_ops) 800 return 0; 801 seq_printf(filp, "PCI dev\t\tRVU PF Func\tNIX block\t%s\tLMAC\tCHAN\n", 802 mac_ops->name); 803 804 /* All the PF devices are on contiguous PCI bus numbers, but the PF0(AF) 805 * may not start from 1 always. Hence get domain and bus from PCI device. 806 */ 807 start = rvu->pdev->bus->number; 808 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 809 if (!is_pf_cgxmapped(rvu, pf)) 810 continue; 811 812 pdev = pci_get_domain_bus_and_slot(domain, pf + start, 0); 813 if (!pdev) 814 continue; 815 816 cgx[0] = 0; 817 lmac[0] = 0; 818 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0); 819 pfvf = rvu_get_pfvf(rvu, pcifunc); 820 821 if (pfvf->nix_blkaddr == BLKADDR_NIX0) 822 blkid = 0; 823 else 824 blkid = 1; 825 826 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, 827 &lmac_id); 828 sprintf(cgx, "%s%d", mac_ops->name, cgx_id); 829 sprintf(lmac, "LMAC%d", lmac_id); 830 sprintf(chan, "%d", 831 rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0)); 832 seq_printf(filp, "%s\t0x%x\t\tNIX%d\t\t%s\t%s\t%s\n", 833 dev_name(&pdev->dev), pcifunc, blkid, cgx, lmac, 834 chan); 835 836 pci_dev_put(pdev); 837 } 838 return 0; 839 } 840 841 RVU_DEBUG_SEQ_FOPS(rvu_pf_cgx_map, rvu_pf_cgx_map_display, NULL); 842 843 static int rvu_dbg_rvu_fwdata_display(struct seq_file *s, void *unused) 844 { 845 struct rvu *rvu = s->private; 846 struct rvu_fwdata *fwdata; 847 u8 mac[ETH_ALEN]; 848 int count = 0, i; 849 850 if (!rvu->fwdata) 851 return -EAGAIN; 852 853 fwdata = rvu->fwdata; 854 seq_puts(s, "\nRVU Firmware Data:\n"); 855 seq_puts(s, "\n\t\tPTP INFORMATION\n"); 856 seq_puts(s, "\t\t===============\n"); 857 seq_printf(s, "\t\texternal clockrate \t :%x\n", 858 fwdata->ptp_ext_clk_rate); 859 seq_printf(s, "\t\texternal timestamp \t :%x\n", 860 fwdata->ptp_ext_tstamp); 861 seq_puts(s, "\n"); 862 863 seq_puts(s, "\n\t\tSDP CHANNEL INFORMATION\n"); 864 seq_puts(s, "\t\t=======================\n"); 865 seq_printf(s, "\t\tValid \t\t\t :%x\n", fwdata->channel_data.valid); 866 seq_printf(s, "\t\tNode ID \t\t :%x\n", 867 fwdata->channel_data.info.node_id); 868 seq_printf(s, "\t\tNumber of VFs \t\t :%x\n", 869 fwdata->channel_data.info.max_vfs); 870 seq_printf(s, "\t\tNumber of PF-Rings \t :%x\n", 871 fwdata->channel_data.info.num_pf_rings); 872 seq_printf(s, "\t\tPF SRN \t\t\t :%x\n", 873 fwdata->channel_data.info.pf_srn); 874 seq_puts(s, "\n"); 875 876 seq_puts(s, "\n\t\tPF-INDEX MACADDRESS\n"); 877 seq_puts(s, "\t\t====================\n"); 878 for (i = 0; i < PF_MACNUM_MAX; i++) { 879 u64_to_ether_addr(fwdata->pf_macs[i], mac); 880 if (!is_zero_ether_addr(mac)) { 881 seq_printf(s, "\t\t %d %pM\n", i, mac); 882 count++; 883 } 884 } 885 886 if (!count) 887 seq_puts(s, "\t\tNo valid address found\n"); 888 889 seq_puts(s, "\n\t\tVF-INDEX MACADDRESS\n"); 890 seq_puts(s, "\t\t====================\n"); 891 count = 0; 892 for (i = 0; i < VF_MACNUM_MAX; i++) { 893 u64_to_ether_addr(fwdata->vf_macs[i], mac); 894 if (!is_zero_ether_addr(mac)) { 895 seq_printf(s, "\t\t %d %pM\n", i, mac); 896 count++; 897 } 898 } 899 900 if (!count) 901 seq_puts(s, "\t\tNo valid address found\n"); 902 903 return 0; 904 } 905 906 RVU_DEBUG_SEQ_FOPS(rvu_fwdata, rvu_fwdata_display, NULL); 907 908 static bool rvu_dbg_is_valid_lf(struct rvu *rvu, int blkaddr, int lf, 909 u16 *pcifunc) 910 { 911 struct rvu_block *block; 912 struct rvu_hwinfo *hw; 913 914 hw = rvu->hw; 915 block = &hw->block[blkaddr]; 916 917 if (lf < 0 || lf >= block->lf.max) { 918 dev_warn(rvu->dev, "Invalid LF: valid range: 0-%d\n", 919 block->lf.max - 1); 920 return false; 921 } 922 923 *pcifunc = block->fn_map[lf]; 924 if (!*pcifunc) { 925 dev_warn(rvu->dev, 926 "This LF is not attached to any RVU PFFUNC\n"); 927 return false; 928 } 929 return true; 930 } 931 932 static void print_npa_qsize(struct seq_file *m, struct rvu_pfvf *pfvf) 933 { 934 if (!pfvf->aura_ctx) { 935 seq_puts(m, "Aura context is not initialized\n"); 936 } else { 937 seq_printf(m, "Aura count : %d\n", pfvf->aura_ctx->qsize); 938 seq_printf(m, "Aura context ena/dis bitmap : %*pb\n", 939 pfvf->aura_ctx->qsize, pfvf->aura_bmap); 940 } 941 942 if (!pfvf->pool_ctx) { 943 seq_puts(m, "Pool context is not initialized\n"); 944 } else { 945 seq_printf(m, "Pool count : %d\n", pfvf->pool_ctx->qsize); 946 seq_printf(m, "Pool context ena/dis bitmap : %*pb\n", 947 pfvf->pool_ctx->qsize, pfvf->pool_bmap); 948 } 949 } 950 951 /* The 'qsize' entry dumps current Aura/Pool context Qsize 952 * and each context's current enable/disable status in a bitmap. 953 */ 954 static int rvu_dbg_qsize_display(struct seq_file *s, void *unsused, 955 int blktype) 956 { 957 void (*print_qsize)(struct seq_file *s, 958 struct rvu_pfvf *pfvf) = NULL; 959 struct rvu_pfvf *pfvf; 960 struct rvu *rvu; 961 int qsize_id; 962 u16 pcifunc; 963 int blkaddr; 964 965 rvu = s->private; 966 switch (blktype) { 967 case BLKTYPE_NPA: 968 qsize_id = rvu->rvu_dbg.npa_qsize_id; 969 print_qsize = print_npa_qsize; 970 break; 971 972 case BLKTYPE_NIX: 973 qsize_id = rvu->rvu_dbg.nix_qsize_id; 974 print_qsize = print_nix_qsize; 975 break; 976 977 default: 978 return -EINVAL; 979 } 980 981 if (blktype == BLKTYPE_NPA) 982 blkaddr = BLKADDR_NPA; 983 else 984 blkaddr = debugfs_get_aux_num(s->file); 985 986 if (!rvu_dbg_is_valid_lf(rvu, blkaddr, qsize_id, &pcifunc)) 987 return -EINVAL; 988 989 pfvf = rvu_get_pfvf(rvu, pcifunc); 990 print_qsize(s, pfvf); 991 992 return 0; 993 } 994 995 static ssize_t rvu_dbg_qsize_write(struct file *file, 996 const char __user *buffer, size_t count, 997 loff_t *ppos, int blktype) 998 { 999 char *blk_string = (blktype == BLKTYPE_NPA) ? "npa" : "nix"; 1000 struct seq_file *seqfile = file->private_data; 1001 char *cmd_buf, *cmd_buf_tmp, *subtoken; 1002 struct rvu *rvu = seqfile->private; 1003 int blkaddr; 1004 u16 pcifunc; 1005 int ret, lf; 1006 1007 cmd_buf = memdup_user_nul(buffer, count); 1008 if (IS_ERR(cmd_buf)) 1009 return -ENOMEM; 1010 1011 cmd_buf_tmp = strchr(cmd_buf, '\n'); 1012 if (cmd_buf_tmp) { 1013 *cmd_buf_tmp = '\0'; 1014 count = cmd_buf_tmp - cmd_buf + 1; 1015 } 1016 1017 cmd_buf_tmp = cmd_buf; 1018 subtoken = strsep(&cmd_buf, " "); 1019 ret = subtoken ? kstrtoint(subtoken, 10, &lf) : -EINVAL; 1020 if (cmd_buf) 1021 ret = -EINVAL; 1022 1023 if (ret < 0 || !strncmp(subtoken, "help", 4)) { 1024 dev_info(rvu->dev, "Use echo <%s-lf > qsize\n", blk_string); 1025 goto qsize_write_done; 1026 } 1027 1028 if (blktype == BLKTYPE_NPA) 1029 blkaddr = BLKADDR_NPA; 1030 else 1031 blkaddr = debugfs_get_aux_num(file); 1032 1033 if (!rvu_dbg_is_valid_lf(rvu, blkaddr, lf, &pcifunc)) { 1034 ret = -EINVAL; 1035 goto qsize_write_done; 1036 } 1037 if (blktype == BLKTYPE_NPA) 1038 rvu->rvu_dbg.npa_qsize_id = lf; 1039 else 1040 rvu->rvu_dbg.nix_qsize_id = lf; 1041 1042 qsize_write_done: 1043 kfree(cmd_buf_tmp); 1044 return ret ? ret : count; 1045 } 1046 1047 static ssize_t rvu_dbg_npa_qsize_write(struct file *filp, 1048 const char __user *buffer, 1049 size_t count, loff_t *ppos) 1050 { 1051 return rvu_dbg_qsize_write(filp, buffer, count, ppos, 1052 BLKTYPE_NPA); 1053 } 1054 1055 static int rvu_dbg_npa_qsize_display(struct seq_file *filp, void *unused) 1056 { 1057 return rvu_dbg_qsize_display(filp, unused, BLKTYPE_NPA); 1058 } 1059 1060 RVU_DEBUG_SEQ_FOPS(npa_qsize, npa_qsize_display, npa_qsize_write); 1061 1062 /* Dumps given NPA Aura's context */ 1063 static void print_npa_aura_ctx(struct seq_file *m, struct npa_aq_enq_rsp *rsp) 1064 { 1065 struct npa_aura_s *aura = &rsp->aura; 1066 struct rvu *rvu = m->private; 1067 1068 if (is_cn20k(rvu->pdev)) { 1069 print_npa_cn20k_aura_ctx(m, (struct npa_cn20k_aq_enq_rsp *)rsp); 1070 return; 1071 } 1072 1073 seq_printf(m, "W0: Pool addr\t\t%llx\n", aura->pool_addr); 1074 1075 seq_printf(m, "W1: ena\t\t\t%d\nW1: pool caching\t%d\n", 1076 aura->ena, aura->pool_caching); 1077 seq_printf(m, "W1: pool way mask\t%d\nW1: avg con\t\t%d\n", 1078 aura->pool_way_mask, aura->avg_con); 1079 seq_printf(m, "W1: pool drop ena\t%d\nW1: aura drop ena\t%d\n", 1080 aura->pool_drop_ena, aura->aura_drop_ena); 1081 seq_printf(m, "W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\n", 1082 aura->bp_ena, aura->aura_drop); 1083 seq_printf(m, "W1: aura shift\t\t%d\nW1: avg_level\t\t%d\n", 1084 aura->shift, aura->avg_level); 1085 1086 seq_printf(m, "W2: count\t\t%llu\nW2: nix0_bpid\t\t%d\nW2: nix1_bpid\t\t%d\n", 1087 (u64)aura->count, aura->nix0_bpid, aura->nix1_bpid); 1088 1089 seq_printf(m, "W3: limit\t\t%llu\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n", 1090 (u64)aura->limit, aura->bp, aura->fc_ena); 1091 1092 if (!is_rvu_otx2(rvu)) 1093 seq_printf(m, "W3: fc_be\t\t%d\n", aura->fc_be); 1094 seq_printf(m, "W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d\n", 1095 aura->fc_up_crossing, aura->fc_stype); 1096 seq_printf(m, "W3: fc_hyst_bits\t%d\n", aura->fc_hyst_bits); 1097 1098 seq_printf(m, "W4: fc_addr\t\t%llx\n", aura->fc_addr); 1099 1100 seq_printf(m, "W5: pool_drop\t\t%d\nW5: update_time\t\t%d\n", 1101 aura->pool_drop, aura->update_time); 1102 seq_printf(m, "W5: err_int \t\t%d\nW5: err_int_ena\t\t%d\n", 1103 aura->err_int, aura->err_int_ena); 1104 seq_printf(m, "W5: thresh_int\t\t%d\nW5: thresh_int_ena \t%d\n", 1105 aura->thresh_int, aura->thresh_int_ena); 1106 seq_printf(m, "W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d\n", 1107 aura->thresh_up, aura->thresh_qint_idx); 1108 seq_printf(m, "W5: err_qint_idx \t%d\n", aura->err_qint_idx); 1109 1110 seq_printf(m, "W6: thresh\t\t%llu\n", (u64)aura->thresh); 1111 if (!is_rvu_otx2(rvu)) 1112 seq_printf(m, "W6: fc_msh_dst\t\t%d\n", aura->fc_msh_dst); 1113 } 1114 1115 /* Dumps given NPA Pool's context */ 1116 static void print_npa_pool_ctx(struct seq_file *m, struct npa_aq_enq_rsp *rsp) 1117 { 1118 struct npa_pool_s *pool = &rsp->pool; 1119 struct rvu *rvu = m->private; 1120 1121 if (is_cn20k(rvu->pdev)) { 1122 print_npa_cn20k_pool_ctx(m, (struct npa_cn20k_aq_enq_rsp *)rsp); 1123 return; 1124 } 1125 1126 seq_printf(m, "W0: Stack base\t\t%llx\n", pool->stack_base); 1127 1128 seq_printf(m, "W1: ena \t\t%d\nW1: nat_align \t\t%d\n", 1129 pool->ena, pool->nat_align); 1130 seq_printf(m, "W1: stack_caching\t%d\nW1: stack_way_mask\t%d\n", 1131 pool->stack_caching, pool->stack_way_mask); 1132 seq_printf(m, "W1: buf_offset\t\t%d\nW1: buf_size\t\t%d\n", 1133 pool->buf_offset, pool->buf_size); 1134 1135 seq_printf(m, "W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d\n", 1136 pool->stack_max_pages, pool->stack_pages); 1137 1138 seq_printf(m, "W3: op_pc \t\t%llu\n", (u64)pool->op_pc); 1139 1140 seq_printf(m, "W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d\n", 1141 pool->stack_offset, pool->shift, pool->avg_level); 1142 seq_printf(m, "W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d\n", 1143 pool->avg_con, pool->fc_ena, pool->fc_stype); 1144 seq_printf(m, "W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d\n", 1145 pool->fc_hyst_bits, pool->fc_up_crossing); 1146 if (!is_rvu_otx2(rvu)) 1147 seq_printf(m, "W4: fc_be\t\t%d\n", pool->fc_be); 1148 seq_printf(m, "W4: update_time\t\t%d\n", pool->update_time); 1149 1150 seq_printf(m, "W5: fc_addr\t\t%llx\n", pool->fc_addr); 1151 1152 seq_printf(m, "W6: ptr_start\t\t%llx\n", pool->ptr_start); 1153 1154 seq_printf(m, "W7: ptr_end\t\t%llx\n", pool->ptr_end); 1155 1156 seq_printf(m, "W8: err_int\t\t%d\nW8: err_int_ena\t\t%d\n", 1157 pool->err_int, pool->err_int_ena); 1158 seq_printf(m, "W8: thresh_int\t\t%d\n", pool->thresh_int); 1159 seq_printf(m, "W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d\n", 1160 pool->thresh_int_ena, pool->thresh_up); 1161 seq_printf(m, "W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d\n", 1162 pool->thresh_qint_idx, pool->err_qint_idx); 1163 if (!is_rvu_otx2(rvu)) 1164 seq_printf(m, "W8: fc_msh_dst\t\t%d\n", pool->fc_msh_dst); 1165 } 1166 1167 /* Reads aura/pool's ctx from admin queue */ 1168 static int rvu_dbg_npa_ctx_display(struct seq_file *m, void *unused, int ctype) 1169 { 1170 void (*print_npa_ctx)(struct seq_file *m, struct npa_aq_enq_rsp *rsp); 1171 struct npa_aq_enq_req aq_req; 1172 struct npa_aq_enq_rsp rsp; 1173 struct rvu_pfvf *pfvf; 1174 int aura, rc, max_id; 1175 int npalf, id, all; 1176 struct rvu *rvu; 1177 u16 pcifunc; 1178 1179 rvu = m->private; 1180 1181 switch (ctype) { 1182 case NPA_AQ_CTYPE_AURA: 1183 npalf = rvu->rvu_dbg.npa_aura_ctx.lf; 1184 id = rvu->rvu_dbg.npa_aura_ctx.id; 1185 all = rvu->rvu_dbg.npa_aura_ctx.all; 1186 break; 1187 1188 case NPA_AQ_CTYPE_POOL: 1189 npalf = rvu->rvu_dbg.npa_pool_ctx.lf; 1190 id = rvu->rvu_dbg.npa_pool_ctx.id; 1191 all = rvu->rvu_dbg.npa_pool_ctx.all; 1192 break; 1193 default: 1194 return -EINVAL; 1195 } 1196 1197 if (!rvu_dbg_is_valid_lf(rvu, BLKADDR_NPA, npalf, &pcifunc)) 1198 return -EINVAL; 1199 1200 pfvf = rvu_get_pfvf(rvu, pcifunc); 1201 if (ctype == NPA_AQ_CTYPE_AURA && !pfvf->aura_ctx) { 1202 seq_puts(m, "Aura context is not initialized\n"); 1203 return -EINVAL; 1204 } else if (ctype == NPA_AQ_CTYPE_POOL && !pfvf->pool_ctx) { 1205 seq_puts(m, "Pool context is not initialized\n"); 1206 return -EINVAL; 1207 } 1208 1209 memset(&aq_req, 0, sizeof(struct npa_aq_enq_req)); 1210 aq_req.hdr.pcifunc = pcifunc; 1211 aq_req.ctype = ctype; 1212 aq_req.op = NPA_AQ_INSTOP_READ; 1213 if (ctype == NPA_AQ_CTYPE_AURA) { 1214 max_id = pfvf->aura_ctx->qsize; 1215 print_npa_ctx = print_npa_aura_ctx; 1216 } else { 1217 max_id = pfvf->pool_ctx->qsize; 1218 print_npa_ctx = print_npa_pool_ctx; 1219 } 1220 1221 if (id < 0 || id >= max_id) { 1222 seq_printf(m, "Invalid %s, valid range is 0-%d\n", 1223 (ctype == NPA_AQ_CTYPE_AURA) ? "aura" : "pool", 1224 max_id - 1); 1225 return -EINVAL; 1226 } 1227 1228 if (all) 1229 id = 0; 1230 else 1231 max_id = id + 1; 1232 1233 for (aura = id; aura < max_id; aura++) { 1234 aq_req.aura_id = aura; 1235 1236 /* Skip if queue is uninitialized */ 1237 if (ctype == NPA_AQ_CTYPE_POOL && !test_bit(aura, pfvf->pool_bmap)) 1238 continue; 1239 1240 seq_printf(m, "======%s : %d=======\n", 1241 (ctype == NPA_AQ_CTYPE_AURA) ? "AURA" : "POOL", 1242 aq_req.aura_id); 1243 rc = rvu_npa_aq_enq_inst(rvu, &aq_req, &rsp); 1244 if (rc) { 1245 seq_puts(m, "Failed to read context\n"); 1246 return -EINVAL; 1247 } 1248 print_npa_ctx(m, &rsp); 1249 } 1250 return 0; 1251 } 1252 1253 static int write_npa_ctx(struct rvu *rvu, bool all, 1254 int npalf, int id, int ctype) 1255 { 1256 struct rvu_pfvf *pfvf; 1257 int max_id = 0; 1258 u16 pcifunc; 1259 1260 if (!rvu_dbg_is_valid_lf(rvu, BLKADDR_NPA, npalf, &pcifunc)) 1261 return -EINVAL; 1262 1263 pfvf = rvu_get_pfvf(rvu, pcifunc); 1264 1265 if (ctype == NPA_AQ_CTYPE_AURA) { 1266 if (!pfvf->aura_ctx) { 1267 dev_warn(rvu->dev, "Aura context is not initialized\n"); 1268 return -EINVAL; 1269 } 1270 max_id = pfvf->aura_ctx->qsize; 1271 } else if (ctype == NPA_AQ_CTYPE_POOL) { 1272 if (!pfvf->pool_ctx) { 1273 dev_warn(rvu->dev, "Pool context is not initialized\n"); 1274 return -EINVAL; 1275 } 1276 max_id = pfvf->pool_ctx->qsize; 1277 } 1278 1279 if (id < 0 || id >= max_id) { 1280 dev_warn(rvu->dev, "Invalid %s, valid range is 0-%d\n", 1281 (ctype == NPA_AQ_CTYPE_AURA) ? "aura" : "pool", 1282 max_id - 1); 1283 return -EINVAL; 1284 } 1285 1286 switch (ctype) { 1287 case NPA_AQ_CTYPE_AURA: 1288 rvu->rvu_dbg.npa_aura_ctx.lf = npalf; 1289 rvu->rvu_dbg.npa_aura_ctx.id = id; 1290 rvu->rvu_dbg.npa_aura_ctx.all = all; 1291 break; 1292 1293 case NPA_AQ_CTYPE_POOL: 1294 rvu->rvu_dbg.npa_pool_ctx.lf = npalf; 1295 rvu->rvu_dbg.npa_pool_ctx.id = id; 1296 rvu->rvu_dbg.npa_pool_ctx.all = all; 1297 break; 1298 default: 1299 return -EINVAL; 1300 } 1301 return 0; 1302 } 1303 1304 static int parse_cmd_buffer_ctx(char *cmd_buf, size_t *count, 1305 const char __user *buffer, int *npalf, 1306 int *id, bool *all) 1307 { 1308 int bytes_not_copied; 1309 char *cmd_buf_tmp; 1310 char *subtoken; 1311 int ret; 1312 1313 bytes_not_copied = copy_from_user(cmd_buf, buffer, *count); 1314 if (bytes_not_copied) 1315 return -EFAULT; 1316 1317 cmd_buf[*count] = '\0'; 1318 cmd_buf_tmp = strchr(cmd_buf, '\n'); 1319 1320 if (cmd_buf_tmp) { 1321 *cmd_buf_tmp = '\0'; 1322 *count = cmd_buf_tmp - cmd_buf + 1; 1323 } 1324 1325 subtoken = strsep(&cmd_buf, " "); 1326 ret = subtoken ? kstrtoint(subtoken, 10, npalf) : -EINVAL; 1327 if (ret < 0) 1328 return ret; 1329 subtoken = strsep(&cmd_buf, " "); 1330 if (subtoken && strcmp(subtoken, "all") == 0) { 1331 *all = true; 1332 } else { 1333 ret = subtoken ? kstrtoint(subtoken, 10, id) : -EINVAL; 1334 if (ret < 0) 1335 return ret; 1336 } 1337 if (cmd_buf) 1338 return -EINVAL; 1339 return ret; 1340 } 1341 1342 static ssize_t rvu_dbg_npa_ctx_write(struct file *filp, 1343 const char __user *buffer, 1344 size_t count, loff_t *ppos, int ctype) 1345 { 1346 char *cmd_buf, *ctype_string = (ctype == NPA_AQ_CTYPE_AURA) ? 1347 "aura" : "pool"; 1348 struct seq_file *seqfp = filp->private_data; 1349 struct rvu *rvu = seqfp->private; 1350 int npalf, id = 0, ret; 1351 bool all = false; 1352 1353 if ((*ppos != 0) || !count) 1354 return -EINVAL; 1355 1356 cmd_buf = kzalloc(count + 1, GFP_KERNEL); 1357 if (!cmd_buf) 1358 return count; 1359 ret = parse_cmd_buffer_ctx(cmd_buf, &count, buffer, 1360 &npalf, &id, &all); 1361 if (ret < 0) { 1362 dev_info(rvu->dev, 1363 "Usage: echo <npalf> [%s number/all] > %s_ctx\n", 1364 ctype_string, ctype_string); 1365 goto done; 1366 } else { 1367 ret = write_npa_ctx(rvu, all, npalf, id, ctype); 1368 } 1369 done: 1370 kfree(cmd_buf); 1371 return ret ? ret : count; 1372 } 1373 1374 static ssize_t rvu_dbg_npa_aura_ctx_write(struct file *filp, 1375 const char __user *buffer, 1376 size_t count, loff_t *ppos) 1377 { 1378 return rvu_dbg_npa_ctx_write(filp, buffer, count, ppos, 1379 NPA_AQ_CTYPE_AURA); 1380 } 1381 1382 static int rvu_dbg_npa_aura_ctx_display(struct seq_file *filp, void *unused) 1383 { 1384 return rvu_dbg_npa_ctx_display(filp, unused, NPA_AQ_CTYPE_AURA); 1385 } 1386 1387 RVU_DEBUG_SEQ_FOPS(npa_aura_ctx, npa_aura_ctx_display, npa_aura_ctx_write); 1388 1389 static ssize_t rvu_dbg_npa_pool_ctx_write(struct file *filp, 1390 const char __user *buffer, 1391 size_t count, loff_t *ppos) 1392 { 1393 return rvu_dbg_npa_ctx_write(filp, buffer, count, ppos, 1394 NPA_AQ_CTYPE_POOL); 1395 } 1396 1397 static int rvu_dbg_npa_pool_ctx_display(struct seq_file *filp, void *unused) 1398 { 1399 return rvu_dbg_npa_ctx_display(filp, unused, NPA_AQ_CTYPE_POOL); 1400 } 1401 1402 RVU_DEBUG_SEQ_FOPS(npa_pool_ctx, npa_pool_ctx_display, npa_pool_ctx_write); 1403 1404 static void ndc_cache_stats(struct seq_file *s, int blk_addr, 1405 int ctype, int transaction) 1406 { 1407 u64 req, out_req, lat, cant_alloc; 1408 struct nix_hw *nix_hw; 1409 struct rvu *rvu; 1410 int port; 1411 1412 if (blk_addr == BLKADDR_NDC_NPA0) { 1413 rvu = s->private; 1414 } else { 1415 nix_hw = s->private; 1416 rvu = nix_hw->rvu; 1417 } 1418 1419 for (port = 0; port < NDC_MAX_PORT; port++) { 1420 req = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_REQ_PC 1421 (port, ctype, transaction)); 1422 lat = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_LAT_PC 1423 (port, ctype, transaction)); 1424 out_req = rvu_read64(rvu, blk_addr, 1425 NDC_AF_PORTX_RTX_RWX_OSTDN_PC 1426 (port, ctype, transaction)); 1427 cant_alloc = rvu_read64(rvu, blk_addr, 1428 NDC_AF_PORTX_RTX_CANT_ALLOC_PC 1429 (port, transaction)); 1430 seq_printf(s, "\nPort:%d\n", port); 1431 seq_printf(s, "\tTotal Requests:\t\t%lld\n", req); 1432 seq_printf(s, "\tTotal Time Taken:\t%lld cycles\n", lat); 1433 seq_printf(s, "\tAvg Latency:\t\t%lld cycles\n", lat / req); 1434 seq_printf(s, "\tOutstanding Requests:\t%lld\n", out_req); 1435 seq_printf(s, "\tCant Alloc Requests:\t%lld\n", cant_alloc); 1436 } 1437 } 1438 1439 static int ndc_blk_cache_stats(struct seq_file *s, int idx, int blk_addr) 1440 { 1441 seq_puts(s, "\n***** CACHE mode read stats *****\n"); 1442 ndc_cache_stats(s, blk_addr, CACHING, NDC_READ_TRANS); 1443 seq_puts(s, "\n***** CACHE mode write stats *****\n"); 1444 ndc_cache_stats(s, blk_addr, CACHING, NDC_WRITE_TRANS); 1445 seq_puts(s, "\n***** BY-PASS mode read stats *****\n"); 1446 ndc_cache_stats(s, blk_addr, BYPASS, NDC_READ_TRANS); 1447 seq_puts(s, "\n***** BY-PASS mode write stats *****\n"); 1448 ndc_cache_stats(s, blk_addr, BYPASS, NDC_WRITE_TRANS); 1449 return 0; 1450 } 1451 1452 static int rvu_dbg_npa_ndc_cache_display(struct seq_file *filp, void *unused) 1453 { 1454 return ndc_blk_cache_stats(filp, NPA0_U, BLKADDR_NDC_NPA0); 1455 } 1456 1457 RVU_DEBUG_SEQ_FOPS(npa_ndc_cache, npa_ndc_cache_display, NULL); 1458 1459 static int ndc_blk_hits_miss_stats(struct seq_file *s, int idx, int blk_addr) 1460 { 1461 struct nix_hw *nix_hw; 1462 struct rvu *rvu; 1463 int bank, max_bank; 1464 u64 ndc_af_const; 1465 1466 if (blk_addr == BLKADDR_NDC_NPA0) { 1467 rvu = s->private; 1468 } else { 1469 nix_hw = s->private; 1470 rvu = nix_hw->rvu; 1471 } 1472 1473 ndc_af_const = rvu_read64(rvu, blk_addr, NDC_AF_CONST); 1474 max_bank = FIELD_GET(NDC_AF_BANK_MASK, ndc_af_const); 1475 for (bank = 0; bank < max_bank; bank++) { 1476 seq_printf(s, "BANK:%d\n", bank); 1477 seq_printf(s, "\tHits:\t%lld\n", 1478 (u64)rvu_read64(rvu, blk_addr, 1479 NDC_AF_BANKX_HIT_PC(bank))); 1480 seq_printf(s, "\tMiss:\t%lld\n", 1481 (u64)rvu_read64(rvu, blk_addr, 1482 NDC_AF_BANKX_MISS_PC(bank))); 1483 } 1484 return 0; 1485 } 1486 1487 static int rvu_dbg_nix_ndc_rx_cache_display(struct seq_file *filp, void *unused) 1488 { 1489 struct nix_hw *nix_hw = filp->private; 1490 int blkaddr = 0; 1491 int ndc_idx = 0; 1492 1493 blkaddr = (nix_hw->blkaddr == BLKADDR_NIX1 ? 1494 BLKADDR_NDC_NIX1_RX : BLKADDR_NDC_NIX0_RX); 1495 ndc_idx = (nix_hw->blkaddr == BLKADDR_NIX1 ? NIX1_RX : NIX0_RX); 1496 1497 return ndc_blk_cache_stats(filp, ndc_idx, blkaddr); 1498 } 1499 1500 RVU_DEBUG_SEQ_FOPS(nix_ndc_rx_cache, nix_ndc_rx_cache_display, NULL); 1501 1502 static int rvu_dbg_nix_ndc_tx_cache_display(struct seq_file *filp, void *unused) 1503 { 1504 struct nix_hw *nix_hw = filp->private; 1505 int blkaddr = 0; 1506 int ndc_idx = 0; 1507 1508 blkaddr = (nix_hw->blkaddr == BLKADDR_NIX1 ? 1509 BLKADDR_NDC_NIX1_TX : BLKADDR_NDC_NIX0_TX); 1510 ndc_idx = (nix_hw->blkaddr == BLKADDR_NIX1 ? NIX1_TX : NIX0_TX); 1511 1512 return ndc_blk_cache_stats(filp, ndc_idx, blkaddr); 1513 } 1514 1515 RVU_DEBUG_SEQ_FOPS(nix_ndc_tx_cache, nix_ndc_tx_cache_display, NULL); 1516 1517 static int rvu_dbg_npa_ndc_hits_miss_display(struct seq_file *filp, 1518 void *unused) 1519 { 1520 return ndc_blk_hits_miss_stats(filp, NPA0_U, BLKADDR_NDC_NPA0); 1521 } 1522 1523 RVU_DEBUG_SEQ_FOPS(npa_ndc_hits_miss, npa_ndc_hits_miss_display, NULL); 1524 1525 static int rvu_dbg_nix_ndc_rx_hits_miss_display(struct seq_file *filp, 1526 void *unused) 1527 { 1528 struct nix_hw *nix_hw = filp->private; 1529 int ndc_idx = NPA0_U; 1530 int blkaddr = 0; 1531 1532 blkaddr = (nix_hw->blkaddr == BLKADDR_NIX1 ? 1533 BLKADDR_NDC_NIX1_RX : BLKADDR_NDC_NIX0_RX); 1534 1535 return ndc_blk_hits_miss_stats(filp, ndc_idx, blkaddr); 1536 } 1537 1538 RVU_DEBUG_SEQ_FOPS(nix_ndc_rx_hits_miss, nix_ndc_rx_hits_miss_display, NULL); 1539 1540 static int rvu_dbg_nix_ndc_tx_hits_miss_display(struct seq_file *filp, 1541 void *unused) 1542 { 1543 struct nix_hw *nix_hw = filp->private; 1544 int ndc_idx = NPA0_U; 1545 int blkaddr = 0; 1546 1547 blkaddr = (nix_hw->blkaddr == BLKADDR_NIX1 ? 1548 BLKADDR_NDC_NIX1_TX : BLKADDR_NDC_NIX0_TX); 1549 1550 return ndc_blk_hits_miss_stats(filp, ndc_idx, blkaddr); 1551 } 1552 1553 RVU_DEBUG_SEQ_FOPS(nix_ndc_tx_hits_miss, nix_ndc_tx_hits_miss_display, NULL); 1554 1555 static void print_nix_cn10k_sq_ctx(struct seq_file *m, 1556 struct nix_cn10k_sq_ctx_s *sq_ctx) 1557 { 1558 seq_printf(m, "W0: ena \t\t\t%d\nW0: qint_idx \t\t\t%d\n", 1559 sq_ctx->ena, sq_ctx->qint_idx); 1560 seq_printf(m, "W0: substream \t\t\t0x%03x\nW0: sdp_mcast \t\t\t%d\n", 1561 sq_ctx->substream, sq_ctx->sdp_mcast); 1562 seq_printf(m, "W0: cq \t\t\t\t%d\nW0: sqe_way_mask \t\t%d\n\n", 1563 sq_ctx->cq, sq_ctx->sqe_way_mask); 1564 1565 seq_printf(m, "W1: smq \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: xoff\t\t\t%d\n", 1566 sq_ctx->smq, sq_ctx->cq_ena, sq_ctx->xoff); 1567 seq_printf(m, "W1: sso_ena \t\t\t%d\nW1: smq_rr_weight\t\t%d\n", 1568 sq_ctx->sso_ena, sq_ctx->smq_rr_weight); 1569 seq_printf(m, "W1: default_chan\t\t%d\nW1: sqb_count\t\t\t%d\n\n", 1570 sq_ctx->default_chan, sq_ctx->sqb_count); 1571 1572 seq_printf(m, "W2: smq_rr_count_lb \t\t%d\n", sq_ctx->smq_rr_count_lb); 1573 seq_printf(m, "W2: smq_rr_count_ub \t\t%d\n", sq_ctx->smq_rr_count_ub); 1574 seq_printf(m, "W2: sqb_aura \t\t\t%d\nW2: sq_int \t\t\t%d\n", 1575 sq_ctx->sqb_aura, sq_ctx->sq_int); 1576 seq_printf(m, "W2: sq_int_ena \t\t\t%d\nW2: sqe_stype \t\t\t%d\n", 1577 sq_ctx->sq_int_ena, sq_ctx->sqe_stype); 1578 1579 seq_printf(m, "W3: max_sqe_size\t\t%d\nW3: cq_limit\t\t\t%d\n", 1580 sq_ctx->max_sqe_size, sq_ctx->cq_limit); 1581 seq_printf(m, "W3: lmt_dis \t\t\t%d\nW3: mnq_dis \t\t\t%d\n", 1582 sq_ctx->mnq_dis, sq_ctx->lmt_dis); 1583 seq_printf(m, "W3: smq_next_sq\t\t\t%d\nW3: smq_lso_segnum\t\t%d\n", 1584 sq_ctx->smq_next_sq, sq_ctx->smq_lso_segnum); 1585 seq_printf(m, "W3: tail_offset \t\t%d\nW3: smenq_offset\t\t%d\n", 1586 sq_ctx->tail_offset, sq_ctx->smenq_offset); 1587 seq_printf(m, "W3: head_offset\t\t\t%d\nW3: smenq_next_sqb_vld\t\t%d\n\n", 1588 sq_ctx->head_offset, sq_ctx->smenq_next_sqb_vld); 1589 1590 seq_printf(m, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d\n", 1591 sq_ctx->smq_next_sq_vld, sq_ctx->smq_pend); 1592 seq_printf(m, "W4: next_sqb \t\t\t%llx\n\n", sq_ctx->next_sqb); 1593 seq_printf(m, "W5: tail_sqb \t\t\t%llx\n\n", sq_ctx->tail_sqb); 1594 seq_printf(m, "W6: smenq_sqb \t\t\t%llx\n\n", sq_ctx->smenq_sqb); 1595 seq_printf(m, "W7: smenq_next_sqb \t\t%llx\n\n", 1596 sq_ctx->smenq_next_sqb); 1597 1598 seq_printf(m, "W8: head_sqb\t\t\t%llx\n\n", sq_ctx->head_sqb); 1599 1600 seq_printf(m, "W9: vfi_lso_total\t\t%d\n", sq_ctx->vfi_lso_total); 1601 seq_printf(m, "W9: vfi_lso_sizem1\t\t%d\nW9: vfi_lso_sb\t\t\t%d\n", 1602 sq_ctx->vfi_lso_sizem1, sq_ctx->vfi_lso_sb); 1603 seq_printf(m, "W9: vfi_lso_mps\t\t\t%d\nW9: vfi_lso_vlan0_ins_ena\t%d\n", 1604 sq_ctx->vfi_lso_mps, sq_ctx->vfi_lso_vlan0_ins_ena); 1605 seq_printf(m, "W9: vfi_lso_vlan1_ins_ena\t%d\nW9: vfi_lso_vld \t\t%d\n\n", 1606 sq_ctx->vfi_lso_vld, sq_ctx->vfi_lso_vlan1_ins_ena); 1607 1608 seq_printf(m, "W10: scm_lso_rem \t\t%llu\n\n", 1609 (u64)sq_ctx->scm_lso_rem); 1610 seq_printf(m, "W11: octs \t\t\t%llu\n\n", (u64)sq_ctx->octs); 1611 seq_printf(m, "W12: pkts \t\t\t%llu\n\n", (u64)sq_ctx->pkts); 1612 seq_printf(m, "W14: dropped_octs \t\t%llu\n\n", 1613 (u64)sq_ctx->dropped_octs); 1614 seq_printf(m, "W15: dropped_pkts \t\t%llu\n\n", 1615 (u64)sq_ctx->dropped_pkts); 1616 } 1617 1618 static void print_tm_tree(struct seq_file *m, 1619 struct nix_aq_enq_rsp *rsp, u64 sq) 1620 { 1621 struct nix_sq_ctx_s *sq_ctx = &rsp->sq; 1622 struct nix_hw *nix_hw = m->private; 1623 struct rvu *rvu = nix_hw->rvu; 1624 u16 p1, p2, p3, p4, schq; 1625 int blkaddr; 1626 u64 cfg; 1627 1628 if (!sq_ctx->ena) 1629 return; 1630 1631 blkaddr = nix_hw->blkaddr; 1632 schq = sq_ctx->smq; 1633 1634 cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_PARENT(schq)); 1635 p1 = FIELD_GET(NIX_AF_MDQ_PARENT_MASK, cfg); 1636 1637 cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL4X_PARENT(p1)); 1638 p2 = FIELD_GET(NIX_AF_TL4_PARENT_MASK, cfg); 1639 1640 cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL3X_PARENT(p2)); 1641 p3 = FIELD_GET(NIX_AF_TL3_PARENT_MASK, cfg); 1642 1643 cfg = rvu_read64(rvu, blkaddr, NIX_AF_TL2X_PARENT(p3)); 1644 p4 = FIELD_GET(NIX_AF_TL2_PARENT_MASK, cfg); 1645 seq_printf(m, 1646 "SQ(%llu) -> SMQ(%u) -> TL4(%u) -> TL3(%u) -> TL2(%u) -> TL1(%u)\n", 1647 sq, schq, p1, p2, p3, p4); 1648 } 1649 1650 /*dumps given tm_tree registers*/ 1651 static int rvu_dbg_nix_tm_tree_display(struct seq_file *m, void *unused) 1652 { 1653 int qidx, nixlf, rc, id, max_id = 0; 1654 struct nix_hw *nix_hw = m->private; 1655 struct rvu *rvu = nix_hw->rvu; 1656 struct nix_aq_enq_req aq_req; 1657 struct nix_aq_enq_rsp rsp; 1658 struct rvu_pfvf *pfvf; 1659 u16 pcifunc; 1660 1661 nixlf = rvu->rvu_dbg.nix_tm_ctx.lf; 1662 id = rvu->rvu_dbg.nix_tm_ctx.id; 1663 1664 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 1665 return -EINVAL; 1666 1667 pfvf = rvu_get_pfvf(rvu, pcifunc); 1668 1669 if (!pfvf->sq_ctx) { 1670 seq_printf(m, "SQ context is not initialized for pcifunc 0x%x\n", pcifunc); 1671 return -EINVAL; 1672 } 1673 1674 max_id = pfvf->sq_ctx->qsize; 1675 1676 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1677 aq_req.hdr.pcifunc = pcifunc; 1678 aq_req.ctype = NIX_AQ_CTYPE_SQ; 1679 aq_req.op = NIX_AQ_INSTOP_READ; 1680 seq_printf(m, "pcifunc is 0x%x\n", pcifunc); 1681 for (qidx = id; qidx < max_id; qidx++) { 1682 aq_req.qidx = qidx; 1683 1684 /* Skip SQ's if not initialized */ 1685 if (!test_bit(qidx, pfvf->sq_bmap)) 1686 continue; 1687 1688 rc = rvu_mbox_handler_nix_aq_enq(rvu, &aq_req, &rsp); 1689 1690 if (rc) { 1691 seq_printf(m, "Failed to read SQ(%d) context\n", 1692 aq_req.qidx); 1693 continue; 1694 } 1695 print_tm_tree(m, &rsp, aq_req.qidx); 1696 } 1697 return 0; 1698 } 1699 1700 static ssize_t rvu_dbg_nix_tm_tree_write(struct file *filp, 1701 const char __user *buffer, 1702 size_t count, loff_t *ppos) 1703 { 1704 struct seq_file *m = filp->private_data; 1705 struct nix_hw *nix_hw = m->private; 1706 struct rvu *rvu = nix_hw->rvu; 1707 struct rvu_pfvf *pfvf; 1708 u16 pcifunc; 1709 u64 nixlf; 1710 int ret; 1711 1712 ret = kstrtoull_from_user(buffer, count, 10, &nixlf); 1713 if (ret) 1714 return ret; 1715 1716 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 1717 return -EINVAL; 1718 1719 pfvf = rvu_get_pfvf(rvu, pcifunc); 1720 if (!pfvf->sq_ctx) { 1721 dev_warn(rvu->dev, "SQ context is not initialized\n"); 1722 return -EINVAL; 1723 } 1724 1725 rvu->rvu_dbg.nix_tm_ctx.lf = nixlf; 1726 return count; 1727 } 1728 1729 RVU_DEBUG_SEQ_FOPS(nix_tm_tree, nix_tm_tree_display, nix_tm_tree_write); 1730 1731 static void print_tm_topo(struct seq_file *m, u64 schq, u32 lvl) 1732 { 1733 struct nix_hw *nix_hw = m->private; 1734 struct rvu *rvu = nix_hw->rvu; 1735 int blkaddr, link, link_level; 1736 struct rvu_hwinfo *hw; 1737 1738 hw = rvu->hw; 1739 blkaddr = nix_hw->blkaddr; 1740 if (lvl == NIX_TXSCH_LVL_MDQ) { 1741 seq_printf(m, "NIX_AF_SMQ[%llu]_CFG =0x%llx\n", schq, 1742 rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq))); 1743 seq_printf(m, "NIX_AF_SMQ[%llu]_STATUS =0x%llx\n", schq, 1744 rvu_read64(rvu, blkaddr, NIX_AF_SMQX_STATUS(schq))); 1745 seq_printf(m, "NIX_AF_MDQ[%llu]_OUT_MD_COUNT =0x%llx\n", schq, 1746 rvu_read64(rvu, blkaddr, 1747 NIX_AF_MDQX_OUT_MD_COUNT(schq))); 1748 seq_printf(m, "NIX_AF_MDQ[%llu]_SCHEDULE =0x%llx\n", schq, 1749 rvu_read64(rvu, blkaddr, 1750 NIX_AF_MDQX_SCHEDULE(schq))); 1751 seq_printf(m, "NIX_AF_MDQ[%llu]_SHAPE =0x%llx\n", schq, 1752 rvu_read64(rvu, blkaddr, NIX_AF_MDQX_SHAPE(schq))); 1753 seq_printf(m, "NIX_AF_MDQ[%llu]_CIR =0x%llx\n", schq, 1754 rvu_read64(rvu, blkaddr, NIX_AF_MDQX_CIR(schq))); 1755 seq_printf(m, "NIX_AF_MDQ[%llu]_PIR =0x%llx\n", schq, 1756 rvu_read64(rvu, blkaddr, NIX_AF_MDQX_PIR(schq))); 1757 seq_printf(m, "NIX_AF_MDQ[%llu]_SW_XOFF =0x%llx\n", schq, 1758 rvu_read64(rvu, blkaddr, NIX_AF_MDQX_SW_XOFF(schq))); 1759 seq_printf(m, "NIX_AF_MDQ[%llu]_PARENT =0x%llx\n", schq, 1760 rvu_read64(rvu, blkaddr, NIX_AF_MDQX_PARENT(schq))); 1761 seq_puts(m, "\n"); 1762 } 1763 1764 if (lvl == NIX_TXSCH_LVL_TL4) { 1765 seq_printf(m, "NIX_AF_TL4[%llu]_SDP_LINK_CFG =0x%llx\n", schq, 1766 rvu_read64(rvu, blkaddr, 1767 NIX_AF_TL4X_SDP_LINK_CFG(schq))); 1768 seq_printf(m, "NIX_AF_TL4[%llu]_SCHEDULE =0x%llx\n", schq, 1769 rvu_read64(rvu, blkaddr, 1770 NIX_AF_TL4X_SCHEDULE(schq))); 1771 seq_printf(m, "NIX_AF_TL4[%llu]_SHAPE =0x%llx\n", schq, 1772 rvu_read64(rvu, blkaddr, NIX_AF_TL4X_SHAPE(schq))); 1773 seq_printf(m, "NIX_AF_TL4[%llu]_CIR =0x%llx\n", schq, 1774 rvu_read64(rvu, blkaddr, NIX_AF_TL4X_CIR(schq))); 1775 seq_printf(m, "NIX_AF_TL4[%llu]_PIR =0x%llx\n", schq, 1776 rvu_read64(rvu, blkaddr, NIX_AF_TL4X_PIR(schq))); 1777 seq_printf(m, "NIX_AF_TL4[%llu]_SW_XOFF =0x%llx\n", schq, 1778 rvu_read64(rvu, blkaddr, NIX_AF_TL4X_SW_XOFF(schq))); 1779 seq_printf(m, "NIX_AF_TL4[%llu]_TOPOLOGY =0x%llx\n", schq, 1780 rvu_read64(rvu, blkaddr, 1781 NIX_AF_TL4X_TOPOLOGY(schq))); 1782 seq_printf(m, "NIX_AF_TL4[%llu]_PARENT =0x%llx\n", schq, 1783 rvu_read64(rvu, blkaddr, NIX_AF_TL4X_PARENT(schq))); 1784 seq_printf(m, "NIX_AF_TL4[%llu]_MD_DEBUG0 =0x%llx\n", schq, 1785 rvu_read64(rvu, blkaddr, 1786 NIX_AF_TL4X_MD_DEBUG0(schq))); 1787 seq_printf(m, "NIX_AF_TL4[%llu]_MD_DEBUG1 =0x%llx\n", schq, 1788 rvu_read64(rvu, blkaddr, 1789 NIX_AF_TL4X_MD_DEBUG1(schq))); 1790 seq_puts(m, "\n"); 1791 } 1792 1793 if (lvl == NIX_TXSCH_LVL_TL3) { 1794 seq_printf(m, "NIX_AF_TL3[%llu]_SCHEDULE =0x%llx\n", schq, 1795 rvu_read64(rvu, blkaddr, 1796 NIX_AF_TL3X_SCHEDULE(schq))); 1797 seq_printf(m, "NIX_AF_TL3[%llu]_SHAPE =0x%llx\n", schq, 1798 rvu_read64(rvu, blkaddr, NIX_AF_TL3X_SHAPE(schq))); 1799 seq_printf(m, "NIX_AF_TL3[%llu]_CIR =0x%llx\n", schq, 1800 rvu_read64(rvu, blkaddr, NIX_AF_TL3X_CIR(schq))); 1801 seq_printf(m, "NIX_AF_TL3[%llu]_PIR =0x%llx\n", schq, 1802 rvu_read64(rvu, blkaddr, NIX_AF_TL3X_PIR(schq))); 1803 seq_printf(m, "NIX_AF_TL3[%llu]_SW_XOFF =0x%llx\n", schq, 1804 rvu_read64(rvu, blkaddr, NIX_AF_TL3X_SW_XOFF(schq))); 1805 seq_printf(m, "NIX_AF_TL3[%llu]_TOPOLOGY =0x%llx\n", schq, 1806 rvu_read64(rvu, blkaddr, 1807 NIX_AF_TL3X_TOPOLOGY(schq))); 1808 seq_printf(m, "NIX_AF_TL3[%llu]_PARENT =0x%llx\n", schq, 1809 rvu_read64(rvu, blkaddr, NIX_AF_TL3X_PARENT(schq))); 1810 seq_printf(m, "NIX_AF_TL3[%llu]_MD_DEBUG0 =0x%llx\n", schq, 1811 rvu_read64(rvu, blkaddr, 1812 NIX_AF_TL3X_MD_DEBUG0(schq))); 1813 seq_printf(m, "NIX_AF_TL3[%llu]_MD_DEBUG1 =0x%llx\n", schq, 1814 rvu_read64(rvu, blkaddr, 1815 NIX_AF_TL3X_MD_DEBUG1(schq))); 1816 1817 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) 1818 & 0x01 ? NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1819 if (lvl == link_level) { 1820 seq_printf(m, 1821 "NIX_AF_TL3_TL2[%llu]_BP_STATUS =0x%llx\n", 1822 schq, rvu_read64(rvu, blkaddr, 1823 NIX_AF_TL3_TL2X_BP_STATUS(schq))); 1824 for (link = 0; link < hw->cgx_links; link++) 1825 seq_printf(m, 1826 "NIX_AF_TL3_TL2[%llu]_LINK[%d]_CFG =0x%llx\n", 1827 schq, link, 1828 rvu_read64(rvu, blkaddr, 1829 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link))); 1830 } 1831 seq_puts(m, "\n"); 1832 } 1833 1834 if (lvl == NIX_TXSCH_LVL_TL2) { 1835 seq_printf(m, "NIX_AF_TL2[%llu]_SHAPE =0x%llx\n", schq, 1836 rvu_read64(rvu, blkaddr, NIX_AF_TL2X_SHAPE(schq))); 1837 seq_printf(m, "NIX_AF_TL2[%llu]_CIR =0x%llx\n", schq, 1838 rvu_read64(rvu, blkaddr, NIX_AF_TL2X_CIR(schq))); 1839 seq_printf(m, "NIX_AF_TL2[%llu]_PIR =0x%llx\n", schq, 1840 rvu_read64(rvu, blkaddr, NIX_AF_TL2X_PIR(schq))); 1841 seq_printf(m, "NIX_AF_TL2[%llu]_SW_XOFF =0x%llx\n", schq, 1842 rvu_read64(rvu, blkaddr, NIX_AF_TL2X_SW_XOFF(schq))); 1843 seq_printf(m, "NIX_AF_TL2[%llu]_TOPOLOGY =0x%llx\n", schq, 1844 rvu_read64(rvu, blkaddr, 1845 NIX_AF_TL2X_TOPOLOGY(schq))); 1846 seq_printf(m, "NIX_AF_TL2[%llu]_PARENT =0x%llx\n", schq, 1847 rvu_read64(rvu, blkaddr, NIX_AF_TL2X_PARENT(schq))); 1848 seq_printf(m, "NIX_AF_TL2[%llu]_MD_DEBUG0 =0x%llx\n", schq, 1849 rvu_read64(rvu, blkaddr, 1850 NIX_AF_TL2X_MD_DEBUG0(schq))); 1851 seq_printf(m, "NIX_AF_TL2[%llu]_MD_DEBUG1 =0x%llx\n", schq, 1852 rvu_read64(rvu, blkaddr, 1853 NIX_AF_TL2X_MD_DEBUG1(schq))); 1854 1855 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) 1856 & 0x01 ? NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1857 if (lvl == link_level) { 1858 seq_printf(m, 1859 "NIX_AF_TL3_TL2[%llu]_BP_STATUS =0x%llx\n", 1860 schq, rvu_read64(rvu, blkaddr, 1861 NIX_AF_TL3_TL2X_BP_STATUS(schq))); 1862 for (link = 0; link < hw->cgx_links; link++) 1863 seq_printf(m, 1864 "NIX_AF_TL3_TL2[%llu]_LINK[%d]_CFG =0x%llx\n", 1865 schq, link, rvu_read64(rvu, blkaddr, 1866 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link))); 1867 } 1868 seq_puts(m, "\n"); 1869 } 1870 1871 if (lvl == NIX_TXSCH_LVL_TL1) { 1872 seq_printf(m, "NIX_AF_TX_LINK[%llu]_NORM_CREDIT =0x%llx\n", 1873 schq, 1874 rvu_read64(rvu, blkaddr, 1875 NIX_AF_TX_LINKX_NORM_CREDIT(schq))); 1876 seq_printf(m, "NIX_AF_TX_LINK[%llu]_HW_XOFF =0x%llx\n", schq, 1877 rvu_read64(rvu, blkaddr, 1878 NIX_AF_TX_LINKX_HW_XOFF(schq))); 1879 seq_printf(m, "NIX_AF_TL1[%llu]_SCHEDULE =0x%llx\n", schq, 1880 rvu_read64(rvu, blkaddr, 1881 NIX_AF_TL1X_SCHEDULE(schq))); 1882 seq_printf(m, "NIX_AF_TL1[%llu]_SHAPE =0x%llx\n", schq, 1883 rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SHAPE(schq))); 1884 seq_printf(m, "NIX_AF_TL1[%llu]_CIR =0x%llx\n", schq, 1885 rvu_read64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq))); 1886 seq_printf(m, "NIX_AF_TL1[%llu]_SW_XOFF =0x%llx\n", schq, 1887 rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq))); 1888 seq_printf(m, "NIX_AF_TL1[%llu]_TOPOLOGY =0x%llx\n", schq, 1889 rvu_read64(rvu, blkaddr, 1890 NIX_AF_TL1X_TOPOLOGY(schq))); 1891 seq_printf(m, "NIX_AF_TL1[%llu]_MD_DEBUG0 =0x%llx\n", schq, 1892 rvu_read64(rvu, blkaddr, 1893 NIX_AF_TL1X_MD_DEBUG0(schq))); 1894 seq_printf(m, "NIX_AF_TL1[%llu]_MD_DEBUG1 =0x%llx\n", schq, 1895 rvu_read64(rvu, blkaddr, 1896 NIX_AF_TL1X_MD_DEBUG1(schq))); 1897 seq_printf(m, "NIX_AF_TL1[%llu]_DROPPED_PACKETS =0x%llx\n", 1898 schq, 1899 rvu_read64(rvu, blkaddr, 1900 NIX_AF_TL1X_DROPPED_PACKETS(schq))); 1901 seq_printf(m, "NIX_AF_TL1[%llu]_DROPPED_BYTES =0x%llx\n", schq, 1902 rvu_read64(rvu, blkaddr, 1903 NIX_AF_TL1X_DROPPED_BYTES(schq))); 1904 seq_printf(m, "NIX_AF_TL1[%llu]_RED_PACKETS =0x%llx\n", schq, 1905 rvu_read64(rvu, blkaddr, 1906 NIX_AF_TL1X_RED_PACKETS(schq))); 1907 seq_printf(m, "NIX_AF_TL1[%llu]_RED_BYTES =0x%llx\n", schq, 1908 rvu_read64(rvu, blkaddr, 1909 NIX_AF_TL1X_RED_BYTES(schq))); 1910 seq_printf(m, "NIX_AF_TL1[%llu]_YELLOW_PACKETS =0x%llx\n", schq, 1911 rvu_read64(rvu, blkaddr, 1912 NIX_AF_TL1X_YELLOW_PACKETS(schq))); 1913 seq_printf(m, "NIX_AF_TL1[%llu]_YELLOW_BYTES =0x%llx\n", schq, 1914 rvu_read64(rvu, blkaddr, 1915 NIX_AF_TL1X_YELLOW_BYTES(schq))); 1916 seq_printf(m, "NIX_AF_TL1[%llu]_GREEN_PACKETS =0x%llx\n", schq, 1917 rvu_read64(rvu, blkaddr, 1918 NIX_AF_TL1X_GREEN_PACKETS(schq))); 1919 seq_printf(m, "NIX_AF_TL1[%llu]_GREEN_BYTES =0x%llx\n", schq, 1920 rvu_read64(rvu, blkaddr, 1921 NIX_AF_TL1X_GREEN_BYTES(schq))); 1922 seq_puts(m, "\n"); 1923 } 1924 } 1925 1926 /*dumps given tm_topo registers*/ 1927 static int rvu_dbg_nix_tm_topo_display(struct seq_file *m, void *unused) 1928 { 1929 struct nix_hw *nix_hw = m->private; 1930 struct rvu *rvu = nix_hw->rvu; 1931 struct nix_aq_enq_req aq_req; 1932 struct nix_txsch *txsch; 1933 int nixlf, lvl, schq; 1934 u16 pcifunc; 1935 1936 nixlf = rvu->rvu_dbg.nix_tm_ctx.lf; 1937 1938 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 1939 return -EINVAL; 1940 1941 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1942 aq_req.hdr.pcifunc = pcifunc; 1943 aq_req.ctype = NIX_AQ_CTYPE_SQ; 1944 aq_req.op = NIX_AQ_INSTOP_READ; 1945 seq_printf(m, "pcifunc is 0x%x\n", pcifunc); 1946 1947 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1948 txsch = &nix_hw->txsch[lvl]; 1949 for (schq = 0; schq < txsch->schq.max; schq++) { 1950 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) == pcifunc) 1951 print_tm_topo(m, schq, lvl); 1952 } 1953 } 1954 return 0; 1955 } 1956 1957 static ssize_t rvu_dbg_nix_tm_topo_write(struct file *filp, 1958 const char __user *buffer, 1959 size_t count, loff_t *ppos) 1960 { 1961 struct seq_file *m = filp->private_data; 1962 struct nix_hw *nix_hw = m->private; 1963 struct rvu *rvu = nix_hw->rvu; 1964 struct rvu_pfvf *pfvf; 1965 u16 pcifunc; 1966 u64 nixlf; 1967 int ret; 1968 1969 ret = kstrtoull_from_user(buffer, count, 10, &nixlf); 1970 if (ret) 1971 return ret; 1972 1973 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 1974 return -EINVAL; 1975 1976 pfvf = rvu_get_pfvf(rvu, pcifunc); 1977 if (!pfvf->sq_ctx) { 1978 dev_warn(rvu->dev, "SQ context is not initialized\n"); 1979 return -EINVAL; 1980 } 1981 1982 rvu->rvu_dbg.nix_tm_ctx.lf = nixlf; 1983 return count; 1984 } 1985 1986 RVU_DEBUG_SEQ_FOPS(nix_tm_topo, nix_tm_topo_display, nix_tm_topo_write); 1987 1988 /* Dumps given nix_sq's context */ 1989 static void print_nix_sq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp) 1990 { 1991 struct nix_sq_ctx_s *sq_ctx = &rsp->sq; 1992 struct nix_hw *nix_hw = m->private; 1993 struct rvu *rvu = nix_hw->rvu; 1994 1995 if (is_cn20k(rvu->pdev)) { 1996 print_nix_cn20k_sq_ctx(m, (struct nix_cn20k_sq_ctx_s *)sq_ctx); 1997 return; 1998 } 1999 2000 if (!is_rvu_otx2(rvu)) { 2001 print_nix_cn10k_sq_ctx(m, (struct nix_cn10k_sq_ctx_s *)sq_ctx); 2002 return; 2003 } 2004 2005 seq_printf(m, "W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d\n", 2006 sq_ctx->sqe_way_mask, sq_ctx->cq); 2007 seq_printf(m, "W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x\n", 2008 sq_ctx->sdp_mcast, sq_ctx->substream); 2009 seq_printf(m, "W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n\n", 2010 sq_ctx->qint_idx, sq_ctx->ena); 2011 2012 seq_printf(m, "W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d\n", 2013 sq_ctx->sqb_count, sq_ctx->default_chan); 2014 seq_printf(m, "W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d\n", 2015 sq_ctx->smq_rr_quantum, sq_ctx->sso_ena); 2016 seq_printf(m, "W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n\n", 2017 sq_ctx->xoff, sq_ctx->cq_ena, sq_ctx->smq); 2018 2019 seq_printf(m, "W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d\n", 2020 sq_ctx->sqe_stype, sq_ctx->sq_int_ena); 2021 seq_printf(m, "W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d\n", 2022 sq_ctx->sq_int, sq_ctx->sqb_aura); 2023 seq_printf(m, "W2: smq_rr_count \t\t%d\n\n", sq_ctx->smq_rr_count); 2024 2025 seq_printf(m, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d\n", 2026 sq_ctx->smq_next_sq_vld, sq_ctx->smq_pend); 2027 seq_printf(m, "W3: smenq_next_sqb_vld \t\t%d\nW3: head_offset\t\t\t%d\n", 2028 sq_ctx->smenq_next_sqb_vld, sq_ctx->head_offset); 2029 seq_printf(m, "W3: smenq_offset\t\t%d\nW3: tail_offset\t\t\t%d\n", 2030 sq_ctx->smenq_offset, sq_ctx->tail_offset); 2031 seq_printf(m, "W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq\t\t\t%d\n", 2032 sq_ctx->smq_lso_segnum, sq_ctx->smq_next_sq); 2033 seq_printf(m, "W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d\n", 2034 sq_ctx->mnq_dis, sq_ctx->lmt_dis); 2035 seq_printf(m, "W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n\n", 2036 sq_ctx->cq_limit, sq_ctx->max_sqe_size); 2037 2038 seq_printf(m, "W4: next_sqb \t\t\t%llx\n\n", sq_ctx->next_sqb); 2039 seq_printf(m, "W5: tail_sqb \t\t\t%llx\n\n", sq_ctx->tail_sqb); 2040 seq_printf(m, "W6: smenq_sqb \t\t\t%llx\n\n", sq_ctx->smenq_sqb); 2041 seq_printf(m, "W7: smenq_next_sqb \t\t%llx\n\n", 2042 sq_ctx->smenq_next_sqb); 2043 2044 seq_printf(m, "W8: head_sqb\t\t\t%llx\n\n", sq_ctx->head_sqb); 2045 2046 seq_printf(m, "W9: vfi_lso_vld\t\t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d\n", 2047 sq_ctx->vfi_lso_vld, sq_ctx->vfi_lso_vlan1_ins_ena); 2048 seq_printf(m, "W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d\n", 2049 sq_ctx->vfi_lso_vlan0_ins_ena, sq_ctx->vfi_lso_mps); 2050 seq_printf(m, "W9: vfi_lso_sb\t\t\t%d\nW9: vfi_lso_sizem1\t\t%d\n", 2051 sq_ctx->vfi_lso_sb, sq_ctx->vfi_lso_sizem1); 2052 seq_printf(m, "W9: vfi_lso_total\t\t%d\n\n", sq_ctx->vfi_lso_total); 2053 2054 seq_printf(m, "W10: scm_lso_rem \t\t%llu\n\n", 2055 (u64)sq_ctx->scm_lso_rem); 2056 seq_printf(m, "W11: octs \t\t\t%llu\n\n", (u64)sq_ctx->octs); 2057 seq_printf(m, "W12: pkts \t\t\t%llu\n\n", (u64)sq_ctx->pkts); 2058 seq_printf(m, "W14: dropped_octs \t\t%llu\n\n", 2059 (u64)sq_ctx->dropped_octs); 2060 seq_printf(m, "W15: dropped_pkts \t\t%llu\n\n", 2061 (u64)sq_ctx->dropped_pkts); 2062 } 2063 2064 static void print_nix_cn10k_rq_ctx(struct seq_file *m, 2065 struct nix_cn10k_rq_ctx_s *rq_ctx) 2066 { 2067 seq_printf(m, "W0: ena \t\t\t%d\nW0: sso_ena \t\t\t%d\n", 2068 rq_ctx->ena, rq_ctx->sso_ena); 2069 seq_printf(m, "W0: ipsech_ena \t\t\t%d\nW0: ena_wqwd \t\t\t%d\n", 2070 rq_ctx->ipsech_ena, rq_ctx->ena_wqwd); 2071 seq_printf(m, "W0: cq \t\t\t\t%d\nW0: lenerr_dis \t\t\t%d\n", 2072 rq_ctx->cq, rq_ctx->lenerr_dis); 2073 seq_printf(m, "W0: csum_il4_dis \t\t%d\nW0: csum_ol4_dis \t\t%d\n", 2074 rq_ctx->csum_il4_dis, rq_ctx->csum_ol4_dis); 2075 seq_printf(m, "W0: len_il4_dis \t\t%d\nW0: len_il3_dis \t\t%d\n", 2076 rq_ctx->len_il4_dis, rq_ctx->len_il3_dis); 2077 seq_printf(m, "W0: len_ol4_dis \t\t%d\nW0: len_ol3_dis \t\t%d\n", 2078 rq_ctx->len_ol4_dis, rq_ctx->len_ol3_dis); 2079 seq_printf(m, "W0: wqe_aura \t\t\t%d\n\n", rq_ctx->wqe_aura); 2080 2081 seq_printf(m, "W1: spb_aura \t\t\t%d\nW1: lpb_aura \t\t\t%d\n", 2082 rq_ctx->spb_aura, rq_ctx->lpb_aura); 2083 seq_printf(m, "W1: spb_aura \t\t\t%d\n", rq_ctx->spb_aura); 2084 seq_printf(m, "W1: sso_grp \t\t\t%d\nW1: sso_tt \t\t\t%d\n", 2085 rq_ctx->sso_grp, rq_ctx->sso_tt); 2086 seq_printf(m, "W1: pb_caching \t\t\t%d\nW1: wqe_caching \t\t%d\n", 2087 rq_ctx->pb_caching, rq_ctx->wqe_caching); 2088 seq_printf(m, "W1: xqe_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d\n", 2089 rq_ctx->xqe_drop_ena, rq_ctx->spb_drop_ena); 2090 seq_printf(m, "W1: lpb_drop_ena \t\t%d\nW1: pb_stashing \t\t%d\n", 2091 rq_ctx->lpb_drop_ena, rq_ctx->pb_stashing); 2092 seq_printf(m, "W1: ipsecd_drop_ena \t\t%d\nW1: chi_ena \t\t\t%d\n\n", 2093 rq_ctx->ipsecd_drop_ena, rq_ctx->chi_ena); 2094 2095 seq_printf(m, "W2: band_prof_id \t\t%d\n", 2096 (u16)rq_ctx->band_prof_id_h << 10 | rq_ctx->band_prof_id); 2097 2098 seq_printf(m, "W2: policer_ena \t\t%d\n", rq_ctx->policer_ena); 2099 seq_printf(m, "W2: spb_sizem1 \t\t\t%d\n", rq_ctx->spb_sizem1); 2100 seq_printf(m, "W2: wqe_skip \t\t\t%d\nW2: sqb_ena \t\t\t%d\n", 2101 rq_ctx->wqe_skip, rq_ctx->spb_ena); 2102 seq_printf(m, "W2: lpb_size1 \t\t\t%d\nW2: first_skip \t\t\t%d\n", 2103 rq_ctx->lpb_sizem1, rq_ctx->first_skip); 2104 seq_printf(m, "W2: later_skip\t\t\t%d\nW2: xqe_imm_size\t\t%d\n", 2105 rq_ctx->later_skip, rq_ctx->xqe_imm_size); 2106 seq_printf(m, "W2: xqe_imm_copy \t\t%d\nW2: xqe_hdr_split \t\t%d\n\n", 2107 rq_ctx->xqe_imm_copy, rq_ctx->xqe_hdr_split); 2108 2109 seq_printf(m, "W3: xqe_drop \t\t\t%d\nW3: xqe_pass \t\t\t%d\n", 2110 rq_ctx->xqe_drop, rq_ctx->xqe_pass); 2111 seq_printf(m, "W3: wqe_pool_drop \t\t%d\nW3: wqe_pool_pass \t\t%d\n", 2112 rq_ctx->wqe_pool_drop, rq_ctx->wqe_pool_pass); 2113 seq_printf(m, "W3: spb_pool_drop \t\t%d\nW3: spb_pool_pass \t\t%d\n", 2114 rq_ctx->spb_pool_drop, rq_ctx->spb_pool_pass); 2115 seq_printf(m, "W3: spb_aura_drop \t\t%d\nW3: spb_aura_pass \t\t%d\n\n", 2116 rq_ctx->spb_aura_pass, rq_ctx->spb_aura_drop); 2117 2118 seq_printf(m, "W4: lpb_aura_drop \t\t%d\nW3: lpb_aura_pass \t\t%d\n", 2119 rq_ctx->lpb_aura_pass, rq_ctx->lpb_aura_drop); 2120 seq_printf(m, "W4: lpb_pool_drop \t\t%d\nW3: lpb_pool_pass \t\t%d\n", 2121 rq_ctx->lpb_pool_drop, rq_ctx->lpb_pool_pass); 2122 seq_printf(m, "W4: rq_int \t\t\t%d\nW4: rq_int_ena\t\t\t%d\n", 2123 rq_ctx->rq_int, rq_ctx->rq_int_ena); 2124 seq_printf(m, "W4: qint_idx \t\t\t%d\n\n", rq_ctx->qint_idx); 2125 2126 seq_printf(m, "W5: ltag \t\t\t%d\nW5: good_utag \t\t\t%d\n", 2127 rq_ctx->ltag, rq_ctx->good_utag); 2128 seq_printf(m, "W5: bad_utag \t\t\t%d\nW5: flow_tagw \t\t\t%d\n", 2129 rq_ctx->bad_utag, rq_ctx->flow_tagw); 2130 seq_printf(m, "W5: ipsec_vwqe \t\t\t%d\nW5: vwqe_ena \t\t\t%d\n", 2131 rq_ctx->ipsec_vwqe, rq_ctx->vwqe_ena); 2132 seq_printf(m, "W5: vwqe_wait \t\t\t%d\nW5: max_vsize_exp\t\t%d\n", 2133 rq_ctx->vwqe_wait, rq_ctx->max_vsize_exp); 2134 seq_printf(m, "W5: vwqe_skip \t\t\t%d\n\n", rq_ctx->vwqe_skip); 2135 2136 seq_printf(m, "W6: octs \t\t\t%llu\n\n", (u64)rq_ctx->octs); 2137 seq_printf(m, "W7: pkts \t\t\t%llu\n\n", (u64)rq_ctx->pkts); 2138 seq_printf(m, "W8: drop_octs \t\t\t%llu\n\n", (u64)rq_ctx->drop_octs); 2139 seq_printf(m, "W9: drop_pkts \t\t\t%llu\n\n", (u64)rq_ctx->drop_pkts); 2140 seq_printf(m, "W10: re_pkts \t\t\t%llu\n", (u64)rq_ctx->re_pkts); 2141 } 2142 2143 /* Dumps given nix_rq's context */ 2144 static void print_nix_rq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp) 2145 { 2146 struct nix_rq_ctx_s *rq_ctx = &rsp->rq; 2147 struct nix_hw *nix_hw = m->private; 2148 struct rvu *rvu = nix_hw->rvu; 2149 2150 if (!is_rvu_otx2(rvu)) { 2151 print_nix_cn10k_rq_ctx(m, (struct nix_cn10k_rq_ctx_s *)rq_ctx); 2152 return; 2153 } 2154 2155 seq_printf(m, "W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x\n", 2156 rq_ctx->wqe_aura, rq_ctx->substream); 2157 seq_printf(m, "W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d\n", 2158 rq_ctx->cq, rq_ctx->ena_wqwd); 2159 seq_printf(m, "W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d\n", 2160 rq_ctx->ipsech_ena, rq_ctx->sso_ena); 2161 seq_printf(m, "W0: ena \t\t\t%d\n\n", rq_ctx->ena); 2162 2163 seq_printf(m, "W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d\n", 2164 rq_ctx->lpb_drop_ena, rq_ctx->spb_drop_ena); 2165 seq_printf(m, "W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d\n", 2166 rq_ctx->xqe_drop_ena, rq_ctx->wqe_caching); 2167 seq_printf(m, "W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d\n", 2168 rq_ctx->pb_caching, rq_ctx->sso_tt); 2169 seq_printf(m, "W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d\n", 2170 rq_ctx->sso_grp, rq_ctx->lpb_aura); 2171 seq_printf(m, "W1: spb_aura \t\t\t%d\n\n", rq_ctx->spb_aura); 2172 2173 seq_printf(m, "W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d\n", 2174 rq_ctx->xqe_hdr_split, rq_ctx->xqe_imm_copy); 2175 seq_printf(m, "W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d\n", 2176 rq_ctx->xqe_imm_size, rq_ctx->later_skip); 2177 seq_printf(m, "W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d\n", 2178 rq_ctx->first_skip, rq_ctx->lpb_sizem1); 2179 seq_printf(m, "W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d\n", 2180 rq_ctx->spb_ena, rq_ctx->wqe_skip); 2181 seq_printf(m, "W2: spb_sizem1 \t\t\t%d\n\n", rq_ctx->spb_sizem1); 2182 2183 seq_printf(m, "W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d\n", 2184 rq_ctx->spb_pool_pass, rq_ctx->spb_pool_drop); 2185 seq_printf(m, "W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d\n", 2186 rq_ctx->spb_aura_pass, rq_ctx->spb_aura_drop); 2187 seq_printf(m, "W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d\n", 2188 rq_ctx->wqe_pool_pass, rq_ctx->wqe_pool_drop); 2189 seq_printf(m, "W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n\n", 2190 rq_ctx->xqe_pass, rq_ctx->xqe_drop); 2191 2192 seq_printf(m, "W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d\n", 2193 rq_ctx->qint_idx, rq_ctx->rq_int_ena); 2194 seq_printf(m, "W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d\n", 2195 rq_ctx->rq_int, rq_ctx->lpb_pool_pass); 2196 seq_printf(m, "W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d\n", 2197 rq_ctx->lpb_pool_drop, rq_ctx->lpb_aura_pass); 2198 seq_printf(m, "W4: lpb_aura_drop \t\t%d\n\n", rq_ctx->lpb_aura_drop); 2199 2200 seq_printf(m, "W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d\n", 2201 rq_ctx->flow_tagw, rq_ctx->bad_utag); 2202 seq_printf(m, "W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n\n", 2203 rq_ctx->good_utag, rq_ctx->ltag); 2204 2205 seq_printf(m, "W6: octs \t\t\t%llu\n\n", (u64)rq_ctx->octs); 2206 seq_printf(m, "W7: pkts \t\t\t%llu\n\n", (u64)rq_ctx->pkts); 2207 seq_printf(m, "W8: drop_octs \t\t\t%llu\n\n", (u64)rq_ctx->drop_octs); 2208 seq_printf(m, "W9: drop_pkts \t\t\t%llu\n\n", (u64)rq_ctx->drop_pkts); 2209 seq_printf(m, "W10: re_pkts \t\t\t%llu\n", (u64)rq_ctx->re_pkts); 2210 } 2211 2212 /* Dumps given nix_cq's context */ 2213 static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp) 2214 { 2215 struct nix_cq_ctx_s *cq_ctx = &rsp->cq; 2216 struct nix_hw *nix_hw = m->private; 2217 struct rvu *rvu = nix_hw->rvu; 2218 2219 if (is_cn20k(rvu->pdev)) { 2220 print_nix_cn20k_cq_ctx(m, (struct nix_cn20k_aq_enq_rsp *)rsp); 2221 return; 2222 } 2223 2224 seq_printf(m, "W0: base \t\t\t%llx\n\n", cq_ctx->base); 2225 2226 seq_printf(m, "W1: wrptr \t\t\t%llx\n", (u64)cq_ctx->wrptr); 2227 seq_printf(m, "W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d\n", 2228 cq_ctx->avg_con, cq_ctx->cint_idx); 2229 seq_printf(m, "W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d\n", 2230 cq_ctx->cq_err, cq_ctx->qint_idx); 2231 seq_printf(m, "W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n\n", 2232 cq_ctx->bpid, cq_ctx->bp_ena); 2233 2234 if (!is_rvu_otx2(rvu)) { 2235 seq_printf(m, "W1: lbpid_high \t\t\t0x%03x\n", cq_ctx->lbpid_high); 2236 seq_printf(m, "W1: lbpid_med \t\t\t0x%03x\n", cq_ctx->lbpid_med); 2237 seq_printf(m, "W1: lbpid_low \t\t\t0x%03x\n", cq_ctx->lbpid_low); 2238 seq_printf(m, "(W1: lbpid) \t\t\t0x%03x\n", 2239 cq_ctx->lbpid_high << 6 | cq_ctx->lbpid_med << 3 | 2240 cq_ctx->lbpid_low); 2241 seq_printf(m, "W1: lbp_ena \t\t\t\t%d\n\n", cq_ctx->lbp_ena); 2242 } 2243 2244 seq_printf(m, "W2: update_time \t\t%d\nW2:avg_level \t\t\t%d\n", 2245 cq_ctx->update_time, cq_ctx->avg_level); 2246 seq_printf(m, "W2: head \t\t\t%d\nW2:tail \t\t\t%d\n\n", 2247 cq_ctx->head, cq_ctx->tail); 2248 2249 seq_printf(m, "W3: cq_err_int_ena \t\t%d\nW3:cq_err_int \t\t\t%d\n", 2250 cq_ctx->cq_err_int_ena, cq_ctx->cq_err_int); 2251 seq_printf(m, "W3: qsize \t\t\t%d\nW3:caching \t\t\t%d\n", 2252 cq_ctx->qsize, cq_ctx->caching); 2253 2254 seq_printf(m, "W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d\n", 2255 cq_ctx->substream, cq_ctx->ena); 2256 if (!is_rvu_otx2(rvu)) { 2257 seq_printf(m, "W3: lbp_frac \t\t\t%d\n", cq_ctx->lbp_frac); 2258 seq_printf(m, "W3: cpt_drop_err_en \t\t\t%d\n", 2259 cq_ctx->cpt_drop_err_en); 2260 } 2261 seq_printf(m, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d\n", 2262 cq_ctx->drop_ena, cq_ctx->drop); 2263 seq_printf(m, "W3: bp \t\t\t\t%d\n\n", cq_ctx->bp); 2264 } 2265 2266 static int rvu_dbg_nix_queue_ctx_display(struct seq_file *filp, 2267 void *unused, int ctype) 2268 { 2269 void (*print_nix_ctx)(struct seq_file *filp, 2270 struct nix_aq_enq_rsp *rsp) = NULL; 2271 struct nix_hw *nix_hw = filp->private; 2272 struct rvu *rvu = nix_hw->rvu; 2273 struct nix_aq_enq_req aq_req; 2274 struct nix_aq_enq_rsp rsp; 2275 char *ctype_string = NULL; 2276 int qidx, rc, max_id = 0; 2277 struct rvu_pfvf *pfvf; 2278 int nixlf, id, all; 2279 u16 pcifunc; 2280 2281 switch (ctype) { 2282 case NIX_AQ_CTYPE_CQ: 2283 nixlf = rvu->rvu_dbg.nix_cq_ctx.lf; 2284 id = rvu->rvu_dbg.nix_cq_ctx.id; 2285 all = rvu->rvu_dbg.nix_cq_ctx.all; 2286 break; 2287 2288 case NIX_AQ_CTYPE_SQ: 2289 nixlf = rvu->rvu_dbg.nix_sq_ctx.lf; 2290 id = rvu->rvu_dbg.nix_sq_ctx.id; 2291 all = rvu->rvu_dbg.nix_sq_ctx.all; 2292 break; 2293 2294 case NIX_AQ_CTYPE_RQ: 2295 nixlf = rvu->rvu_dbg.nix_rq_ctx.lf; 2296 id = rvu->rvu_dbg.nix_rq_ctx.id; 2297 all = rvu->rvu_dbg.nix_rq_ctx.all; 2298 break; 2299 2300 default: 2301 return -EINVAL; 2302 } 2303 2304 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 2305 return -EINVAL; 2306 2307 pfvf = rvu_get_pfvf(rvu, pcifunc); 2308 if (ctype == NIX_AQ_CTYPE_SQ && !pfvf->sq_ctx) { 2309 seq_puts(filp, "SQ context is not initialized\n"); 2310 return -EINVAL; 2311 } else if (ctype == NIX_AQ_CTYPE_RQ && !pfvf->rq_ctx) { 2312 seq_puts(filp, "RQ context is not initialized\n"); 2313 return -EINVAL; 2314 } else if (ctype == NIX_AQ_CTYPE_CQ && !pfvf->cq_ctx) { 2315 seq_puts(filp, "CQ context is not initialized\n"); 2316 return -EINVAL; 2317 } 2318 2319 if (ctype == NIX_AQ_CTYPE_SQ) { 2320 max_id = pfvf->sq_ctx->qsize; 2321 ctype_string = "sq"; 2322 print_nix_ctx = print_nix_sq_ctx; 2323 } else if (ctype == NIX_AQ_CTYPE_RQ) { 2324 max_id = pfvf->rq_ctx->qsize; 2325 ctype_string = "rq"; 2326 print_nix_ctx = print_nix_rq_ctx; 2327 } else if (ctype == NIX_AQ_CTYPE_CQ) { 2328 max_id = pfvf->cq_ctx->qsize; 2329 ctype_string = "cq"; 2330 print_nix_ctx = print_nix_cq_ctx; 2331 } 2332 2333 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 2334 aq_req.hdr.pcifunc = pcifunc; 2335 aq_req.ctype = ctype; 2336 aq_req.op = NIX_AQ_INSTOP_READ; 2337 if (all) 2338 id = 0; 2339 else 2340 max_id = id + 1; 2341 for (qidx = id; qidx < max_id; qidx++) { 2342 aq_req.qidx = qidx; 2343 seq_printf(filp, "=====%s_ctx for nixlf:%d and qidx:%d is=====\n", 2344 ctype_string, nixlf, aq_req.qidx); 2345 rc = rvu_mbox_handler_nix_aq_enq(rvu, &aq_req, &rsp); 2346 if (rc) { 2347 seq_puts(filp, "Failed to read the context\n"); 2348 return -EINVAL; 2349 } 2350 print_nix_ctx(filp, &rsp); 2351 } 2352 return 0; 2353 } 2354 2355 static int write_nix_queue_ctx(struct rvu *rvu, bool all, int nixlf, 2356 int id, int ctype, char *ctype_string, 2357 struct seq_file *m) 2358 { 2359 struct nix_hw *nix_hw = m->private; 2360 struct rvu_pfvf *pfvf; 2361 int max_id = 0; 2362 u16 pcifunc; 2363 2364 if (!rvu_dbg_is_valid_lf(rvu, nix_hw->blkaddr, nixlf, &pcifunc)) 2365 return -EINVAL; 2366 2367 pfvf = rvu_get_pfvf(rvu, pcifunc); 2368 2369 if (ctype == NIX_AQ_CTYPE_SQ) { 2370 if (!pfvf->sq_ctx) { 2371 dev_warn(rvu->dev, "SQ context is not initialized\n"); 2372 return -EINVAL; 2373 } 2374 max_id = pfvf->sq_ctx->qsize; 2375 } else if (ctype == NIX_AQ_CTYPE_RQ) { 2376 if (!pfvf->rq_ctx) { 2377 dev_warn(rvu->dev, "RQ context is not initialized\n"); 2378 return -EINVAL; 2379 } 2380 max_id = pfvf->rq_ctx->qsize; 2381 } else if (ctype == NIX_AQ_CTYPE_CQ) { 2382 if (!pfvf->cq_ctx) { 2383 dev_warn(rvu->dev, "CQ context is not initialized\n"); 2384 return -EINVAL; 2385 } 2386 max_id = pfvf->cq_ctx->qsize; 2387 } 2388 2389 if (id < 0 || id >= max_id) { 2390 dev_warn(rvu->dev, "Invalid %s_ctx valid range 0-%d\n", 2391 ctype_string, max_id - 1); 2392 return -EINVAL; 2393 } 2394 switch (ctype) { 2395 case NIX_AQ_CTYPE_CQ: 2396 rvu->rvu_dbg.nix_cq_ctx.lf = nixlf; 2397 rvu->rvu_dbg.nix_cq_ctx.id = id; 2398 rvu->rvu_dbg.nix_cq_ctx.all = all; 2399 break; 2400 2401 case NIX_AQ_CTYPE_SQ: 2402 rvu->rvu_dbg.nix_sq_ctx.lf = nixlf; 2403 rvu->rvu_dbg.nix_sq_ctx.id = id; 2404 rvu->rvu_dbg.nix_sq_ctx.all = all; 2405 break; 2406 2407 case NIX_AQ_CTYPE_RQ: 2408 rvu->rvu_dbg.nix_rq_ctx.lf = nixlf; 2409 rvu->rvu_dbg.nix_rq_ctx.id = id; 2410 rvu->rvu_dbg.nix_rq_ctx.all = all; 2411 break; 2412 default: 2413 return -EINVAL; 2414 } 2415 return 0; 2416 } 2417 2418 static ssize_t rvu_dbg_nix_queue_ctx_write(struct file *filp, 2419 const char __user *buffer, 2420 size_t count, loff_t *ppos, 2421 int ctype) 2422 { 2423 struct seq_file *m = filp->private_data; 2424 struct nix_hw *nix_hw = m->private; 2425 struct rvu *rvu = nix_hw->rvu; 2426 char *cmd_buf, *ctype_string; 2427 int nixlf, id = 0, ret; 2428 bool all = false; 2429 2430 if ((*ppos != 0) || !count) 2431 return -EINVAL; 2432 2433 switch (ctype) { 2434 case NIX_AQ_CTYPE_SQ: 2435 ctype_string = "sq"; 2436 break; 2437 case NIX_AQ_CTYPE_RQ: 2438 ctype_string = "rq"; 2439 break; 2440 case NIX_AQ_CTYPE_CQ: 2441 ctype_string = "cq"; 2442 break; 2443 default: 2444 return -EINVAL; 2445 } 2446 2447 cmd_buf = kzalloc(count + 1, GFP_KERNEL); 2448 2449 if (!cmd_buf) 2450 return count; 2451 2452 ret = parse_cmd_buffer_ctx(cmd_buf, &count, buffer, 2453 &nixlf, &id, &all); 2454 if (ret < 0) { 2455 dev_info(rvu->dev, 2456 "Usage: echo <nixlf> [%s number/all] > %s_ctx\n", 2457 ctype_string, ctype_string); 2458 goto done; 2459 } else { 2460 ret = write_nix_queue_ctx(rvu, all, nixlf, id, ctype, 2461 ctype_string, m); 2462 } 2463 done: 2464 kfree(cmd_buf); 2465 return ret ? ret : count; 2466 } 2467 2468 static ssize_t rvu_dbg_nix_sq_ctx_write(struct file *filp, 2469 const char __user *buffer, 2470 size_t count, loff_t *ppos) 2471 { 2472 return rvu_dbg_nix_queue_ctx_write(filp, buffer, count, ppos, 2473 NIX_AQ_CTYPE_SQ); 2474 } 2475 2476 static int rvu_dbg_nix_sq_ctx_display(struct seq_file *filp, void *unused) 2477 { 2478 return rvu_dbg_nix_queue_ctx_display(filp, unused, NIX_AQ_CTYPE_SQ); 2479 } 2480 2481 RVU_DEBUG_SEQ_FOPS(nix_sq_ctx, nix_sq_ctx_display, nix_sq_ctx_write); 2482 2483 static ssize_t rvu_dbg_nix_rq_ctx_write(struct file *filp, 2484 const char __user *buffer, 2485 size_t count, loff_t *ppos) 2486 { 2487 return rvu_dbg_nix_queue_ctx_write(filp, buffer, count, ppos, 2488 NIX_AQ_CTYPE_RQ); 2489 } 2490 2491 static int rvu_dbg_nix_rq_ctx_display(struct seq_file *filp, void *unused) 2492 { 2493 return rvu_dbg_nix_queue_ctx_display(filp, unused, NIX_AQ_CTYPE_RQ); 2494 } 2495 2496 RVU_DEBUG_SEQ_FOPS(nix_rq_ctx, nix_rq_ctx_display, nix_rq_ctx_write); 2497 2498 static ssize_t rvu_dbg_nix_cq_ctx_write(struct file *filp, 2499 const char __user *buffer, 2500 size_t count, loff_t *ppos) 2501 { 2502 return rvu_dbg_nix_queue_ctx_write(filp, buffer, count, ppos, 2503 NIX_AQ_CTYPE_CQ); 2504 } 2505 2506 static int rvu_dbg_nix_cq_ctx_display(struct seq_file *filp, void *unused) 2507 { 2508 return rvu_dbg_nix_queue_ctx_display(filp, unused, NIX_AQ_CTYPE_CQ); 2509 } 2510 2511 RVU_DEBUG_SEQ_FOPS(nix_cq_ctx, nix_cq_ctx_display, nix_cq_ctx_write); 2512 2513 static void print_nix_qctx_qsize(struct seq_file *filp, int qsize, 2514 unsigned long *bmap, char *qtype) 2515 { 2516 seq_printf(filp, "%s context count : %d\n", qtype, qsize); 2517 seq_printf(filp, "%s context ena/dis bitmap : %*pb\n", qtype, qsize, bmap); 2518 } 2519 2520 static void print_nix_qsize(struct seq_file *filp, struct rvu_pfvf *pfvf) 2521 { 2522 if (!pfvf->cq_ctx) 2523 seq_puts(filp, "cq context is not initialized\n"); 2524 else 2525 print_nix_qctx_qsize(filp, pfvf->cq_ctx->qsize, pfvf->cq_bmap, 2526 "cq"); 2527 2528 if (!pfvf->rq_ctx) 2529 seq_puts(filp, "rq context is not initialized\n"); 2530 else 2531 print_nix_qctx_qsize(filp, pfvf->rq_ctx->qsize, pfvf->rq_bmap, 2532 "rq"); 2533 2534 if (!pfvf->sq_ctx) 2535 seq_puts(filp, "sq context is not initialized\n"); 2536 else 2537 print_nix_qctx_qsize(filp, pfvf->sq_ctx->qsize, pfvf->sq_bmap, 2538 "sq"); 2539 } 2540 2541 static ssize_t rvu_dbg_nix_qsize_write(struct file *filp, 2542 const char __user *buffer, 2543 size_t count, loff_t *ppos) 2544 { 2545 return rvu_dbg_qsize_write(filp, buffer, count, ppos, 2546 BLKTYPE_NIX); 2547 } 2548 2549 static int rvu_dbg_nix_qsize_display(struct seq_file *filp, void *unused) 2550 { 2551 return rvu_dbg_qsize_display(filp, unused, BLKTYPE_NIX); 2552 } 2553 2554 RVU_DEBUG_SEQ_FOPS(nix_qsize, nix_qsize_display, nix_qsize_write); 2555 2556 static void print_band_prof_ctx(struct seq_file *m, 2557 struct nix_bandprof_s *prof) 2558 { 2559 char *str; 2560 2561 switch (prof->pc_mode) { 2562 case NIX_RX_PC_MODE_VLAN: 2563 str = "VLAN"; 2564 break; 2565 case NIX_RX_PC_MODE_DSCP: 2566 str = "DSCP"; 2567 break; 2568 case NIX_RX_PC_MODE_GEN: 2569 str = "Generic"; 2570 break; 2571 case NIX_RX_PC_MODE_RSVD: 2572 str = "Reserved"; 2573 break; 2574 } 2575 seq_printf(m, "W0: pc_mode\t\t%s\n", str); 2576 str = (prof->icolor == 3) ? "Color blind" : 2577 (prof->icolor == 0) ? "Green" : 2578 (prof->icolor == 1) ? "Yellow" : "Red"; 2579 seq_printf(m, "W0: icolor\t\t%s\n", str); 2580 seq_printf(m, "W0: tnl_ena\t\t%d\n", prof->tnl_ena); 2581 seq_printf(m, "W0: peir_exponent\t%d\n", prof->peir_exponent); 2582 seq_printf(m, "W0: pebs_exponent\t%d\n", prof->pebs_exponent); 2583 seq_printf(m, "W0: cir_exponent\t%d\n", prof->cir_exponent); 2584 seq_printf(m, "W0: cbs_exponent\t%d\n", prof->cbs_exponent); 2585 seq_printf(m, "W0: peir_mantissa\t%d\n", prof->peir_mantissa); 2586 seq_printf(m, "W0: pebs_mantissa\t%d\n", prof->pebs_mantissa); 2587 seq_printf(m, "W0: cir_mantissa\t%d\n", prof->cir_mantissa); 2588 2589 seq_printf(m, "W1: cbs_mantissa\t%d\n", prof->cbs_mantissa); 2590 str = (prof->lmode == 0) ? "byte" : "packet"; 2591 seq_printf(m, "W1: lmode\t\t%s\n", str); 2592 seq_printf(m, "W1: l_select\t\t%d\n", prof->l_sellect); 2593 seq_printf(m, "W1: rdiv\t\t%d\n", prof->rdiv); 2594 seq_printf(m, "W1: adjust_exponent\t%d\n", prof->adjust_exponent); 2595 seq_printf(m, "W1: adjust_mantissa\t%d\n", prof->adjust_mantissa); 2596 str = (prof->gc_action == 0) ? "PASS" : 2597 (prof->gc_action == 1) ? "DROP" : "RED"; 2598 seq_printf(m, "W1: gc_action\t\t%s\n", str); 2599 str = (prof->yc_action == 0) ? "PASS" : 2600 (prof->yc_action == 1) ? "DROP" : "RED"; 2601 seq_printf(m, "W1: yc_action\t\t%s\n", str); 2602 str = (prof->rc_action == 0) ? "PASS" : 2603 (prof->rc_action == 1) ? "DROP" : "RED"; 2604 seq_printf(m, "W1: rc_action\t\t%s\n", str); 2605 seq_printf(m, "W1: meter_algo\t\t%d\n", prof->meter_algo); 2606 2607 seq_printf(m, "W1: band_prof_id\t%d\n", 2608 (u16)prof->band_prof_id_h << 7 | prof->band_prof_id); 2609 2610 seq_printf(m, "W1: hl_en\t\t%d\n", prof->hl_en); 2611 2612 seq_printf(m, "W2: ts\t\t\t%lld\n", (u64)prof->ts); 2613 seq_printf(m, "W3: pe_accum\t\t%d\n", prof->pe_accum); 2614 seq_printf(m, "W3: c_accum\t\t%d\n", prof->c_accum); 2615 seq_printf(m, "W4: green_pkt_pass\t%lld\n", 2616 (u64)prof->green_pkt_pass); 2617 seq_printf(m, "W5: yellow_pkt_pass\t%lld\n", 2618 (u64)prof->yellow_pkt_pass); 2619 seq_printf(m, "W6: red_pkt_pass\t%lld\n", (u64)prof->red_pkt_pass); 2620 seq_printf(m, "W7: green_octs_pass\t%lld\n", 2621 (u64)prof->green_octs_pass); 2622 seq_printf(m, "W8: yellow_octs_pass\t%lld\n", 2623 (u64)prof->yellow_octs_pass); 2624 seq_printf(m, "W9: red_octs_pass\t%lld\n", (u64)prof->red_octs_pass); 2625 seq_printf(m, "W10: green_pkt_drop\t%lld\n", 2626 (u64)prof->green_pkt_drop); 2627 seq_printf(m, "W11: yellow_pkt_drop\t%lld\n", 2628 (u64)prof->yellow_pkt_drop); 2629 seq_printf(m, "W12: red_pkt_drop\t%lld\n", (u64)prof->red_pkt_drop); 2630 seq_printf(m, "W13: green_octs_drop\t%lld\n", 2631 (u64)prof->green_octs_drop); 2632 seq_printf(m, "W14: yellow_octs_drop\t%lld\n", 2633 (u64)prof->yellow_octs_drop); 2634 seq_printf(m, "W15: red_octs_drop\t%lld\n", (u64)prof->red_octs_drop); 2635 seq_puts(m, "==============================\n"); 2636 } 2637 2638 static int rvu_dbg_nix_band_prof_ctx_display(struct seq_file *m, void *unused) 2639 { 2640 struct nix_hw *nix_hw = m->private; 2641 struct nix_cn10k_aq_enq_req aq_req; 2642 struct nix_cn10k_aq_enq_rsp aq_rsp; 2643 struct rvu *rvu = nix_hw->rvu; 2644 struct nix_ipolicer *ipolicer; 2645 int layer, prof_idx, idx, rc; 2646 u16 pcifunc; 2647 char *str; 2648 2649 /* Ingress policers do not exist on all platforms */ 2650 if (!nix_hw->ipolicer) 2651 return 0; 2652 2653 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 2654 if (layer == BAND_PROF_INVAL_LAYER) 2655 continue; 2656 str = (layer == BAND_PROF_LEAF_LAYER) ? "Leaf" : 2657 (layer == BAND_PROF_MID_LAYER) ? "Mid" : "Top"; 2658 2659 seq_printf(m, "\n%s bandwidth profiles\n", str); 2660 seq_puts(m, "=======================\n"); 2661 2662 ipolicer = &nix_hw->ipolicer[layer]; 2663 2664 for (idx = 0; idx < ipolicer->band_prof.max; idx++) { 2665 if (is_rsrc_free(&ipolicer->band_prof, idx)) 2666 continue; 2667 2668 prof_idx = (idx & 0x3FFF) | (layer << 14); 2669 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 2670 0x00, NIX_AQ_CTYPE_BANDPROF, 2671 prof_idx); 2672 if (rc) { 2673 dev_err(rvu->dev, 2674 "%s: Failed to fetch context of %s profile %d, err %d\n", 2675 __func__, str, idx, rc); 2676 return 0; 2677 } 2678 seq_printf(m, "\n%s bandwidth profile:: %d\n", str, idx); 2679 pcifunc = ipolicer->pfvf_map[idx]; 2680 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 2681 seq_printf(m, "Allocated to :: PF %d\n", 2682 rvu_get_pf(rvu->pdev, pcifunc)); 2683 else 2684 seq_printf(m, "Allocated to :: PF %d VF %d\n", 2685 rvu_get_pf(rvu->pdev, pcifunc), 2686 (pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2687 print_band_prof_ctx(m, &aq_rsp.prof); 2688 } 2689 } 2690 return 0; 2691 } 2692 2693 RVU_DEBUG_SEQ_FOPS(nix_band_prof_ctx, nix_band_prof_ctx_display, NULL); 2694 2695 static int rvu_dbg_nix_band_prof_rsrc_display(struct seq_file *m, void *unused) 2696 { 2697 struct nix_hw *nix_hw = m->private; 2698 struct nix_ipolicer *ipolicer; 2699 int layer; 2700 char *str; 2701 2702 /* Ingress policers do not exist on all platforms */ 2703 if (!nix_hw->ipolicer) 2704 return 0; 2705 2706 seq_puts(m, "\nBandwidth profile resource free count\n"); 2707 seq_puts(m, "=====================================\n"); 2708 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 2709 if (layer == BAND_PROF_INVAL_LAYER) 2710 continue; 2711 str = (layer == BAND_PROF_LEAF_LAYER) ? "Leaf" : 2712 (layer == BAND_PROF_MID_LAYER) ? "Mid " : "Top "; 2713 2714 ipolicer = &nix_hw->ipolicer[layer]; 2715 seq_printf(m, "%s :: Max: %4d Free: %4d\n", str, 2716 ipolicer->band_prof.max, 2717 rvu_rsrc_free_count(&ipolicer->band_prof)); 2718 } 2719 seq_puts(m, "=====================================\n"); 2720 2721 return 0; 2722 } 2723 2724 RVU_DEBUG_SEQ_FOPS(nix_band_prof_rsrc, nix_band_prof_rsrc_display, NULL); 2725 2726 static void rvu_dbg_nix_init(struct rvu *rvu, int blkaddr) 2727 { 2728 struct nix_hw *nix_hw; 2729 2730 if (!is_block_implemented(rvu->hw, blkaddr)) 2731 return; 2732 2733 if (blkaddr == BLKADDR_NIX0) { 2734 rvu->rvu_dbg.nix = debugfs_create_dir("nix", rvu->rvu_dbg.root); 2735 nix_hw = &rvu->hw->nix[0]; 2736 } else { 2737 rvu->rvu_dbg.nix = debugfs_create_dir("nix1", 2738 rvu->rvu_dbg.root); 2739 nix_hw = &rvu->hw->nix[1]; 2740 } 2741 2742 debugfs_create_file("tm_tree", 0600, rvu->rvu_dbg.nix, nix_hw, 2743 &rvu_dbg_nix_tm_tree_fops); 2744 debugfs_create_file("tm_topo", 0600, rvu->rvu_dbg.nix, nix_hw, 2745 &rvu_dbg_nix_tm_topo_fops); 2746 debugfs_create_file("sq_ctx", 0600, rvu->rvu_dbg.nix, nix_hw, 2747 &rvu_dbg_nix_sq_ctx_fops); 2748 debugfs_create_file("rq_ctx", 0600, rvu->rvu_dbg.nix, nix_hw, 2749 &rvu_dbg_nix_rq_ctx_fops); 2750 debugfs_create_file("cq_ctx", 0600, rvu->rvu_dbg.nix, nix_hw, 2751 &rvu_dbg_nix_cq_ctx_fops); 2752 debugfs_create_file("ndc_tx_cache", 0600, rvu->rvu_dbg.nix, nix_hw, 2753 &rvu_dbg_nix_ndc_tx_cache_fops); 2754 debugfs_create_file("ndc_rx_cache", 0600, rvu->rvu_dbg.nix, nix_hw, 2755 &rvu_dbg_nix_ndc_rx_cache_fops); 2756 debugfs_create_file("ndc_tx_hits_miss", 0600, rvu->rvu_dbg.nix, nix_hw, 2757 &rvu_dbg_nix_ndc_tx_hits_miss_fops); 2758 debugfs_create_file("ndc_rx_hits_miss", 0600, rvu->rvu_dbg.nix, nix_hw, 2759 &rvu_dbg_nix_ndc_rx_hits_miss_fops); 2760 debugfs_create_file_aux_num("qsize", 0600, rvu->rvu_dbg.nix, rvu, 2761 blkaddr, &rvu_dbg_nix_qsize_fops); 2762 debugfs_create_file("ingress_policer_ctx", 0600, rvu->rvu_dbg.nix, nix_hw, 2763 &rvu_dbg_nix_band_prof_ctx_fops); 2764 debugfs_create_file("ingress_policer_rsrc", 0600, rvu->rvu_dbg.nix, nix_hw, 2765 &rvu_dbg_nix_band_prof_rsrc_fops); 2766 } 2767 2768 static void rvu_dbg_npa_init(struct rvu *rvu) 2769 { 2770 rvu->rvu_dbg.npa = debugfs_create_dir("npa", rvu->rvu_dbg.root); 2771 2772 debugfs_create_file("qsize", 0600, rvu->rvu_dbg.npa, rvu, 2773 &rvu_dbg_npa_qsize_fops); 2774 debugfs_create_file("aura_ctx", 0600, rvu->rvu_dbg.npa, rvu, 2775 &rvu_dbg_npa_aura_ctx_fops); 2776 debugfs_create_file("pool_ctx", 0600, rvu->rvu_dbg.npa, rvu, 2777 &rvu_dbg_npa_pool_ctx_fops); 2778 2779 if (is_cn20k(rvu->pdev)) /* NDC not appliable for cn20k */ 2780 return; 2781 debugfs_create_file("ndc_cache", 0600, rvu->rvu_dbg.npa, rvu, 2782 &rvu_dbg_npa_ndc_cache_fops); 2783 debugfs_create_file("ndc_hits_miss", 0600, rvu->rvu_dbg.npa, rvu, 2784 &rvu_dbg_npa_ndc_hits_miss_fops); 2785 } 2786 2787 /* Per-lmac CGX debugfs files need both RVU and CGX handle; inode->i_private 2788 * points here so seq_file ops avoid pci_get_device(PCI_DEVID_OCTEONTX2_RVU_AF). 2789 */ 2790 struct rvu_cgx_lmac_dbgfs_ctx { 2791 struct rvu *rvu; 2792 void *cgxd; 2793 }; 2794 2795 #define PRINT_CGX_CUML_NIXRX_STATUS(idx, name) \ 2796 ({ \ 2797 u64 cnt; \ 2798 err = rvu_cgx_nix_cuml_stats(rvu, cgxd, lmac_id, (idx), \ 2799 NIX_STATS_RX, &(cnt)); \ 2800 if (!err) \ 2801 seq_printf(s, "%s: %llu\n", name, cnt); \ 2802 cnt; \ 2803 }) 2804 2805 #define PRINT_CGX_CUML_NIXTX_STATUS(idx, name) \ 2806 ({ \ 2807 u64 cnt; \ 2808 err = rvu_cgx_nix_cuml_stats(rvu, cgxd, lmac_id, (idx), \ 2809 NIX_STATS_TX, &(cnt)); \ 2810 if (!err) \ 2811 seq_printf(s, "%s: %llu\n", name, cnt); \ 2812 cnt; \ 2813 }) 2814 2815 static int cgx_print_stats(struct seq_file *s, int lmac_id) 2816 { 2817 struct rvu_cgx_lmac_dbgfs_ctx *dctx = s->private; 2818 struct cgx_link_user_info linfo; 2819 struct rvu *rvu = dctx->rvu; 2820 struct mac_ops *mac_ops; 2821 void *cgxd = dctx->cgxd; 2822 u64 ucast, mcast, bcast; 2823 int stat = 0, err = 0; 2824 u64 tx_stat, rx_stat; 2825 2826 mac_ops = get_mac_ops(cgxd); 2827 /* There can be no CGX devices at all */ 2828 if (!mac_ops) 2829 return 0; 2830 2831 /* Link status */ 2832 seq_puts(s, "\n=======Link Status======\n\n"); 2833 err = cgx_get_link_info(cgxd, lmac_id, &linfo); 2834 if (err) 2835 seq_puts(s, "Failed to read link status\n"); 2836 seq_printf(s, "\nLink is %s %d Mbps\n\n", 2837 linfo.link_up ? "UP" : "DOWN", linfo.speed); 2838 2839 /* Rx stats */ 2840 seq_printf(s, "\n=======NIX RX_STATS(%s port level)======\n\n", 2841 mac_ops->name); 2842 ucast = PRINT_CGX_CUML_NIXRX_STATUS(RX_UCAST, "rx_ucast_frames"); 2843 if (err) 2844 return err; 2845 mcast = PRINT_CGX_CUML_NIXRX_STATUS(RX_MCAST, "rx_mcast_frames"); 2846 if (err) 2847 return err; 2848 bcast = PRINT_CGX_CUML_NIXRX_STATUS(RX_BCAST, "rx_bcast_frames"); 2849 if (err) 2850 return err; 2851 seq_printf(s, "rx_frames: %llu\n", ucast + mcast + bcast); 2852 PRINT_CGX_CUML_NIXRX_STATUS(RX_OCTS, "rx_bytes"); 2853 if (err) 2854 return err; 2855 PRINT_CGX_CUML_NIXRX_STATUS(RX_DROP, "rx_drops"); 2856 if (err) 2857 return err; 2858 PRINT_CGX_CUML_NIXRX_STATUS(RX_ERR, "rx_errors"); 2859 if (err) 2860 return err; 2861 2862 /* Tx stats */ 2863 seq_printf(s, "\n=======NIX TX_STATS(%s port level)======\n\n", 2864 mac_ops->name); 2865 ucast = PRINT_CGX_CUML_NIXTX_STATUS(TX_UCAST, "tx_ucast_frames"); 2866 if (err) 2867 return err; 2868 mcast = PRINT_CGX_CUML_NIXTX_STATUS(TX_MCAST, "tx_mcast_frames"); 2869 if (err) 2870 return err; 2871 bcast = PRINT_CGX_CUML_NIXTX_STATUS(TX_BCAST, "tx_bcast_frames"); 2872 if (err) 2873 return err; 2874 seq_printf(s, "tx_frames: %llu\n", ucast + mcast + bcast); 2875 PRINT_CGX_CUML_NIXTX_STATUS(TX_OCTS, "tx_bytes"); 2876 if (err) 2877 return err; 2878 PRINT_CGX_CUML_NIXTX_STATUS(TX_DROP, "tx_drops"); 2879 if (err) 2880 return err; 2881 2882 /* Rx stats */ 2883 seq_printf(s, "\n=======%s RX_STATS======\n\n", mac_ops->name); 2884 while (stat < mac_ops->rx_stats_cnt) { 2885 err = mac_ops->mac_get_rx_stats(cgxd, lmac_id, stat, &rx_stat); 2886 if (err) 2887 return err; 2888 if (is_rvu_otx2(rvu)) 2889 seq_printf(s, "%s: %llu\n", cgx_rx_stats_fields[stat], 2890 rx_stat); 2891 else 2892 seq_printf(s, "%s: %llu\n", rpm_rx_stats_fields[stat], 2893 rx_stat); 2894 stat++; 2895 } 2896 2897 /* Tx stats */ 2898 stat = 0; 2899 seq_printf(s, "\n=======%s TX_STATS======\n\n", mac_ops->name); 2900 while (stat < mac_ops->tx_stats_cnt) { 2901 err = mac_ops->mac_get_tx_stats(cgxd, lmac_id, stat, &tx_stat); 2902 if (err) 2903 return err; 2904 2905 if (is_rvu_otx2(rvu)) 2906 seq_printf(s, "%s: %llu\n", cgx_tx_stats_fields[stat], 2907 tx_stat); 2908 else 2909 seq_printf(s, "%s: %llu\n", rpm_tx_stats_fields[stat], 2910 tx_stat); 2911 stat++; 2912 } 2913 2914 return err; 2915 } 2916 2917 static int rvu_dbg_derive_lmacid(struct seq_file *s) 2918 { 2919 return debugfs_get_aux_num(s->file); 2920 } 2921 2922 static int rvu_dbg_cgx_stat_display(struct seq_file *s, void *unused) 2923 { 2924 return cgx_print_stats(s, rvu_dbg_derive_lmacid(s)); 2925 } 2926 2927 RVU_DEBUG_SEQ_FOPS(cgx_stat, cgx_stat_display, NULL); 2928 2929 static int cgx_print_dmac_flt(struct seq_file *s, int lmac_id) 2930 { 2931 struct rvu_cgx_lmac_dbgfs_ctx *dctx = s->private; 2932 struct rvu *rvu = dctx->rvu; 2933 struct pci_dev *pdev = NULL; 2934 void *cgxd = dctx->cgxd; 2935 char *bcast, *mcast; 2936 u16 index, domain; 2937 u8 dmac[ETH_ALEN]; 2938 u64 cfg, mac; 2939 int pf; 2940 2941 pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id); 2942 domain = 2; 2943 2944 pdev = pci_get_domain_bus_and_slot(domain, pf + 1, 0); 2945 if (!pdev) 2946 return 0; 2947 2948 cfg = cgx_read_dmac_ctrl(cgxd, lmac_id); 2949 bcast = cfg & CGX_DMAC_BCAST_MODE ? "ACCEPT" : "REJECT"; 2950 mcast = cfg & CGX_DMAC_MCAST_MODE ? "ACCEPT" : "REJECT"; 2951 2952 seq_puts(s, 2953 "PCI dev RVUPF BROADCAST MULTICAST FILTER-MODE\n"); 2954 seq_printf(s, "%s PF%d %9s %9s", 2955 dev_name(&pdev->dev), pf, bcast, mcast); 2956 if (cfg & CGX_DMAC_CAM_ACCEPT) 2957 seq_printf(s, "%12s\n\n", "UNICAST"); 2958 else 2959 seq_printf(s, "%16s\n\n", "PROMISCUOUS"); 2960 2961 seq_puts(s, "\nDMAC-INDEX ADDRESS\n"); 2962 2963 for (index = 0 ; index < 32 ; index++) { 2964 cfg = cgx_read_dmac_entry(cgxd, index); 2965 /* Display enabled dmac entries associated with current lmac */ 2966 if (lmac_id == FIELD_GET(CGX_DMAC_CAM_ENTRY_LMACID, cfg) && 2967 FIELD_GET(CGX_DMAC_CAM_ADDR_ENABLE, cfg)) { 2968 mac = FIELD_GET(CGX_RX_DMAC_ADR_MASK, cfg); 2969 u64_to_ether_addr(mac, dmac); 2970 seq_printf(s, "%7d %pM\n", index, dmac); 2971 } 2972 } 2973 2974 pci_dev_put(pdev); 2975 return 0; 2976 } 2977 2978 static int rvu_dbg_cgx_dmac_flt_display(struct seq_file *s, void *unused) 2979 { 2980 return cgx_print_dmac_flt(s, rvu_dbg_derive_lmacid(s)); 2981 } 2982 2983 RVU_DEBUG_SEQ_FOPS(cgx_dmac_flt, cgx_dmac_flt_display, NULL); 2984 2985 static int cgx_print_fwdata(struct seq_file *s, int lmac_id) 2986 { 2987 struct rvu_cgx_lmac_dbgfs_ctx *dctx = s->private; 2988 struct cgx_lmac_fwdata_s *fwdata; 2989 struct rvu *rvu = dctx->rvu; 2990 void *cgxd = dctx->cgxd; 2991 struct phy_s *phy; 2992 int cgx_id, i; 2993 2994 if (!rvu->fwdata) 2995 return -EAGAIN; 2996 2997 cgx_id = cgx_get_cgxid(cgxd); 2998 2999 if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX) 3000 fwdata = &rvu->fwdata->cgx_fw_data_usx[cgx_id][lmac_id]; 3001 else 3002 fwdata = &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id]; 3003 3004 seq_puts(s, "\nFIRMWARE SHARED:\n"); 3005 seq_puts(s, "\t\tSUPPORTED LINK INFORMATION\t\t\n"); 3006 seq_puts(s, "\t\t==========================\n"); 3007 seq_printf(s, "\t\t Link modes \t\t :%llx\n", 3008 fwdata->supported_link_modes); 3009 seq_printf(s, "\t\t Autoneg \t\t :%llx\n", fwdata->supported_an); 3010 seq_printf(s, "\t\t FEC \t\t\t :%llx\n", fwdata->supported_fec); 3011 seq_puts(s, "\n"); 3012 3013 seq_puts(s, "\t\tADVERTISED LINK INFORMATION\t\t\n"); 3014 seq_puts(s, "\t\t==========================\n"); 3015 seq_printf(s, "\t\t Link modes \t\t :%llx\n", 3016 (u64)fwdata->advertised_link_modes); 3017 seq_printf(s, "\t\t Autoneg \t\t :%x\n", fwdata->advertised_an); 3018 seq_printf(s, "\t\t FEC \t\t\t :%llx\n", fwdata->advertised_fec); 3019 seq_puts(s, "\n"); 3020 3021 seq_puts(s, "\t\tLMAC CONFIG\t\t\n"); 3022 seq_puts(s, "\t\t============\n"); 3023 seq_printf(s, "\t\t rw_valid \t\t :%x\n", fwdata->rw_valid); 3024 seq_printf(s, "\t\t lmac_type \t\t :%x\n", fwdata->lmac_type); 3025 seq_printf(s, "\t\t portm_idx \t\t :%x\n", fwdata->portm_idx); 3026 seq_printf(s, "\t\t mgmt_port \t\t :%x\n", fwdata->mgmt_port); 3027 seq_printf(s, "\t\t Link modes own \t :%llx\n", 3028 (u64)fwdata->advertised_link_modes_own); 3029 seq_puts(s, "\n"); 3030 3031 seq_puts(s, "\n\t\tEEPROM DATA\n"); 3032 seq_puts(s, "\t\t===========\n"); 3033 seq_printf(s, "\t\t sff_id \t\t :%x\n", fwdata->sfp_eeprom.sff_id); 3034 seq_puts(s, "\t\t data \t\t\t :\n"); 3035 seq_puts(s, "\t\t"); 3036 for (i = 0; i < SFP_EEPROM_SIZE; i++) { 3037 seq_printf(s, "%x", fwdata->sfp_eeprom.buf[i]); 3038 if ((i + 1) % 16 == 0) { 3039 seq_puts(s, "\n"); 3040 seq_puts(s, "\t\t"); 3041 } 3042 } 3043 seq_puts(s, "\n"); 3044 3045 phy = &fwdata->phy; 3046 seq_puts(s, "\n\t\tPHY INFORMATION\n"); 3047 seq_puts(s, "\t\t===============\n"); 3048 seq_printf(s, "\t\t Mod type configurable \t\t :%x\n", 3049 phy->misc.can_change_mod_type); 3050 seq_printf(s, "\t\t Mod type \t\t\t :%x\n", phy->misc.mod_type); 3051 seq_printf(s, "\t\t Support FEC \t\t\t :%x\n", phy->misc.has_fec_stats); 3052 seq_printf(s, "\t\t RSFEC corrected words \t\t :%x\n", 3053 phy->fec_stats.rsfec_corr_cws); 3054 seq_printf(s, "\t\t RSFEC uncorrected words \t :%x\n", 3055 phy->fec_stats.rsfec_uncorr_cws); 3056 seq_printf(s, "\t\t BRFEC corrected words \t\t :%x\n", 3057 phy->fec_stats.brfec_corr_blks); 3058 seq_printf(s, "\t\t BRFEC uncorrected words \t :%x\n", 3059 phy->fec_stats.brfec_uncorr_blks); 3060 seq_puts(s, "\n"); 3061 3062 return 0; 3063 } 3064 3065 static int rvu_dbg_cgx_fwdata_display(struct seq_file *s, void *unused) 3066 { 3067 return cgx_print_fwdata(s, rvu_dbg_derive_lmacid(s)); 3068 } 3069 3070 RVU_DEBUG_SEQ_FOPS(cgx_fwdata, cgx_fwdata_display, NULL); 3071 3072 static void rvu_dbg_cgx_init(struct rvu *rvu) 3073 { 3074 struct rvu_cgx_lmac_dbgfs_ctx *ctx; 3075 struct mac_ops *mac_ops; 3076 unsigned long lmac_bmap; 3077 int i, lmac_id; 3078 char dname[20]; 3079 void *cgx; 3080 3081 if (!cgx_get_cgxcnt_max()) 3082 return; 3083 3084 mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu)); 3085 if (!mac_ops) 3086 return; 3087 3088 rvu->rvu_dbg.cgx_root = debugfs_create_dir(mac_ops->name, 3089 rvu->rvu_dbg.root); 3090 3091 for (i = 0; i < cgx_get_cgxcnt_max(); i++) { 3092 cgx = rvu_cgx_pdata(i, rvu); 3093 if (!cgx) 3094 continue; 3095 lmac_bmap = cgx_get_lmac_bmap(cgx); 3096 /* cgx debugfs dir */ 3097 sprintf(dname, "%s%d", mac_ops->name, i); 3098 rvu->rvu_dbg.cgx = debugfs_create_dir(dname, 3099 rvu->rvu_dbg.cgx_root); 3100 3101 ctx = devm_kzalloc(rvu->dev, sizeof(*ctx), GFP_KERNEL); 3102 if (!ctx) 3103 continue; 3104 3105 ctx->rvu = rvu; 3106 ctx->cgxd = cgx; 3107 3108 for_each_set_bit(lmac_id, &lmac_bmap, rvu->hw->lmac_per_cgx) { 3109 /* lmac debugfs dir */ 3110 sprintf(dname, "lmac%d", lmac_id); 3111 rvu->rvu_dbg.lmac = 3112 debugfs_create_dir(dname, rvu->rvu_dbg.cgx); 3113 3114 debugfs_create_file_aux_num("stats", 0600, rvu->rvu_dbg.lmac, 3115 ctx, lmac_id, &rvu_dbg_cgx_stat_fops); 3116 debugfs_create_file_aux_num("mac_filter", 0600, 3117 rvu->rvu_dbg.lmac, ctx, lmac_id, 3118 &rvu_dbg_cgx_dmac_flt_fops); 3119 debugfs_create_file_aux_num("fwdata", 0600, 3120 rvu->rvu_dbg.lmac, ctx, 3121 lmac_id, &rvu_dbg_cgx_fwdata_fops); 3122 } 3123 } 3124 } 3125 3126 /* NPC debugfs APIs */ 3127 static void rvu_print_npc_mcam_info(struct seq_file *s, 3128 u16 pcifunc, int blkaddr) 3129 { 3130 struct rvu *rvu = s->private; 3131 int entry_acnt, entry_ecnt; 3132 int cntr_acnt, cntr_ecnt; 3133 3134 rvu_npc_get_mcam_entry_alloc_info(rvu, pcifunc, blkaddr, 3135 &entry_acnt, &entry_ecnt); 3136 rvu_npc_get_mcam_counter_alloc_info(rvu, pcifunc, blkaddr, 3137 &cntr_acnt, &cntr_ecnt); 3138 if (!entry_acnt && !cntr_acnt) 3139 return; 3140 3141 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 3142 seq_printf(s, "\n\t\t Device \t\t: PF%d\n", 3143 rvu_get_pf(rvu->pdev, pcifunc)); 3144 else 3145 seq_printf(s, "\n\t\t Device \t\t: PF%d VF%d\n", 3146 rvu_get_pf(rvu->pdev, pcifunc), 3147 (pcifunc & RVU_PFVF_FUNC_MASK) - 1); 3148 3149 if (entry_acnt) { 3150 seq_printf(s, "\t\t Entries allocated \t: %d\n", entry_acnt); 3151 seq_printf(s, "\t\t Entries enabled \t: %d\n", entry_ecnt); 3152 } 3153 if (cntr_acnt) { 3154 seq_printf(s, "\t\t Counters allocated \t: %d\n", cntr_acnt); 3155 seq_printf(s, "\t\t Counters enabled \t: %d\n", cntr_ecnt); 3156 } 3157 } 3158 3159 static int rvu_dbg_npc_mcam_info_display(struct seq_file *filp, void *unsued) 3160 { 3161 struct rvu *rvu = filp->private; 3162 int x4_free, x2_free, sb_free; 3163 int pf, vf, numvfs, blkaddr; 3164 struct npc_priv_t *npc_priv; 3165 struct npc_mcam *mcam; 3166 u16 pcifunc, counters; 3167 u64 cfg; 3168 3169 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3170 if (blkaddr < 0) 3171 return -ENODEV; 3172 3173 mcam = &rvu->hw->mcam; 3174 counters = rvu->hw->npc_counters; 3175 3176 seq_puts(filp, "\nNPC MCAM info:\n"); 3177 /* MCAM keywidth on receive and transmit sides */ 3178 if (is_cn20k(rvu->pdev)) { 3179 npc_priv = npc_priv_get(); 3180 seq_printf(filp, "\t\t RX keywidth \t: %s\n", 3181 (npc_priv->kw == NPC_MCAM_KEY_X1) ? 3182 "256bits" : "512bits"); 3183 3184 npc_cn20k_subbank_calc_free(rvu, &x2_free, &x4_free, &sb_free); 3185 seq_printf(filp, "\t\t free x4 slots\t: %d\n", x4_free); 3186 3187 seq_printf(filp, "\t\t free x2 slots\t: %d\n", x2_free); 3188 3189 seq_printf(filp, "\t\t free subbanks\t: %d\n", sb_free); 3190 } else { 3191 cfg = rvu_read64(rvu, blkaddr, 3192 NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX)); 3193 cfg = (cfg >> 32) & 0x07; 3194 seq_printf(filp, "\t\t RX keywidth \t: %s\n", 3195 (cfg == NPC_MCAM_KEY_X1) ? 3196 "112bits" : ((cfg == NPC_MCAM_KEY_X2) ? 3197 "224bits" : "448bits")); 3198 cfg = rvu_read64(rvu, blkaddr, 3199 NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX)); 3200 cfg = (cfg >> 32) & 0x07; 3201 seq_printf(filp, "\t\t TX keywidth \t: %s\n", 3202 (cfg == NPC_MCAM_KEY_X1) ? 3203 "112bits" : ((cfg == NPC_MCAM_KEY_X2) ? 3204 "224bits" : "448bits")); 3205 } 3206 3207 mutex_lock(&mcam->lock); 3208 /* MCAM entries */ 3209 seq_printf(filp, "\n\t\t MCAM entries \t: %d\n", mcam->total_entries); 3210 seq_printf(filp, "\t\t Reserved \t: %d\n", 3211 mcam->total_entries - mcam->bmap_entries); 3212 seq_printf(filp, "\t\t Available \t: %d\n", mcam->bmap_fcnt); 3213 3214 /* MCAM counters */ 3215 seq_printf(filp, "\n\t\t MCAM counters \t: %d\n", counters); 3216 seq_printf(filp, "\t\t Reserved \t: %d\n", 3217 counters - mcam->counters.max); 3218 seq_printf(filp, "\t\t Available \t: %d\n", 3219 rvu_rsrc_free_count(&mcam->counters)); 3220 3221 if (mcam->bmap_entries == mcam->bmap_fcnt) { 3222 mutex_unlock(&mcam->lock); 3223 return 0; 3224 } 3225 3226 seq_puts(filp, "\n\t\t Current allocation\n"); 3227 seq_puts(filp, "\t\t====================\n"); 3228 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 3229 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, 0); 3230 rvu_print_npc_mcam_info(filp, pcifunc, blkaddr); 3231 3232 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 3233 numvfs = (cfg >> 12) & 0xFF; 3234 for (vf = 0; vf < numvfs; vf++) { 3235 pcifunc = rvu_make_pcifunc(rvu->pdev, pf, (vf + 1)); 3236 rvu_print_npc_mcam_info(filp, pcifunc, blkaddr); 3237 } 3238 } 3239 3240 mutex_unlock(&mcam->lock); 3241 return 0; 3242 } 3243 3244 RVU_DEBUG_SEQ_FOPS(npc_mcam_info, npc_mcam_info_display, NULL); 3245 3246 static int rvu_dbg_npc_rx_miss_stats_display(struct seq_file *filp, 3247 void *unused) 3248 { 3249 struct rvu *rvu = filp->private; 3250 struct npc_mcam *mcam; 3251 int blkaddr; 3252 3253 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3254 if (blkaddr < 0) 3255 return -ENODEV; 3256 3257 mcam = &rvu->hw->mcam; 3258 3259 seq_puts(filp, "\nNPC MCAM RX miss action stats\n"); 3260 seq_printf(filp, "\t\tStat %d: \t%lld\n", mcam->rx_miss_act_cntr, 3261 rvu_read64(rvu, blkaddr, 3262 NPC_AF_MATCH_STATX(mcam->rx_miss_act_cntr))); 3263 3264 return 0; 3265 } 3266 3267 RVU_DEBUG_SEQ_FOPS(npc_rx_miss_act, npc_rx_miss_stats_display, NULL); 3268 3269 #define RVU_DBG_PRINT_MPLS_TTL(pkt, mask) \ 3270 do { \ 3271 seq_printf(s, "%ld ", FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, pkt)); \ 3272 seq_printf(s, "mask 0x%lx\n", \ 3273 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TTL, mask)); \ 3274 } while (0) \ 3275 3276 #define RVU_DBG_PRINT_MPLS_LBTCBOS(_pkt, _mask) \ 3277 do { \ 3278 typeof(_pkt) (pkt) = (_pkt); \ 3279 typeof(_mask) (mask) = (_mask); \ 3280 seq_printf(s, "%ld %ld %ld\n", \ 3281 FIELD_GET(OTX2_FLOWER_MASK_MPLS_LB, pkt), \ 3282 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TC, pkt), \ 3283 FIELD_GET(OTX2_FLOWER_MASK_MPLS_BOS, pkt)); \ 3284 seq_printf(s, "\tmask 0x%lx 0x%lx 0x%lx\n", \ 3285 FIELD_GET(OTX2_FLOWER_MASK_MPLS_LB, mask), \ 3286 FIELD_GET(OTX2_FLOWER_MASK_MPLS_TC, mask), \ 3287 FIELD_GET(OTX2_FLOWER_MASK_MPLS_BOS, mask)); \ 3288 } while (0) \ 3289 3290 static void rvu_dbg_npc_mcam_show_flows(struct seq_file *s, 3291 struct rvu_npc_mcam_rule *rule) 3292 { 3293 u8 bit; 3294 3295 for_each_set_bit(bit, (unsigned long *)&rule->features, 64) { 3296 seq_printf(s, "\t%s ", npc_get_field_name(bit)); 3297 switch (bit) { 3298 case NPC_LXMB: 3299 if (rule->lxmb == 1) 3300 seq_puts(s, "\tL2M nibble is set\n"); 3301 else 3302 seq_puts(s, "\tL2B nibble is set\n"); 3303 break; 3304 case NPC_DMAC: 3305 seq_printf(s, "%pM ", rule->packet.dmac); 3306 seq_printf(s, "mask %pM\n", rule->mask.dmac); 3307 break; 3308 case NPC_SMAC: 3309 seq_printf(s, "%pM ", rule->packet.smac); 3310 seq_printf(s, "mask %pM\n", rule->mask.smac); 3311 break; 3312 case NPC_ETYPE: 3313 seq_printf(s, "0x%x ", ntohs(rule->packet.etype)); 3314 seq_printf(s, "mask 0x%x\n", ntohs(rule->mask.etype)); 3315 break; 3316 case NPC_OUTER_VID: 3317 seq_printf(s, "0x%x ", ntohs(rule->packet.vlan_tci)); 3318 seq_printf(s, "mask 0x%x\n", 3319 ntohs(rule->mask.vlan_tci)); 3320 break; 3321 case NPC_INNER_VID: 3322 seq_printf(s, "0x%x ", ntohs(rule->packet.vlan_itci)); 3323 seq_printf(s, "mask 0x%x\n", 3324 ntohs(rule->mask.vlan_itci)); 3325 break; 3326 case NPC_TOS: 3327 seq_printf(s, "%d ", rule->packet.tos); 3328 seq_printf(s, "mask 0x%x\n", rule->mask.tos); 3329 break; 3330 case NPC_SIP_IPV4: 3331 seq_printf(s, "%pI4 ", &rule->packet.ip4src); 3332 seq_printf(s, "mask %pI4\n", &rule->mask.ip4src); 3333 break; 3334 case NPC_DIP_IPV4: 3335 seq_printf(s, "%pI4 ", &rule->packet.ip4dst); 3336 seq_printf(s, "mask %pI4\n", &rule->mask.ip4dst); 3337 break; 3338 case NPC_SIP_IPV6: 3339 seq_printf(s, "%pI6 ", rule->packet.ip6src); 3340 seq_printf(s, "mask %pI6\n", rule->mask.ip6src); 3341 break; 3342 case NPC_DIP_IPV6: 3343 seq_printf(s, "%pI6 ", rule->packet.ip6dst); 3344 seq_printf(s, "mask %pI6\n", rule->mask.ip6dst); 3345 break; 3346 case NPC_IPFRAG_IPV6: 3347 seq_printf(s, "0x%x ", rule->packet.next_header); 3348 seq_printf(s, "mask 0x%x\n", rule->mask.next_header); 3349 break; 3350 case NPC_IPFRAG_IPV4: 3351 seq_printf(s, "0x%x ", rule->packet.ip_flag); 3352 seq_printf(s, "mask 0x%x\n", rule->mask.ip_flag); 3353 break; 3354 case NPC_SPORT_TCP: 3355 case NPC_SPORT_UDP: 3356 case NPC_SPORT_SCTP: 3357 seq_printf(s, "%d ", ntohs(rule->packet.sport)); 3358 seq_printf(s, "mask 0x%x\n", ntohs(rule->mask.sport)); 3359 break; 3360 case NPC_DPORT_TCP: 3361 case NPC_DPORT_UDP: 3362 case NPC_DPORT_SCTP: 3363 seq_printf(s, "%d ", ntohs(rule->packet.dport)); 3364 seq_printf(s, "mask 0x%x\n", ntohs(rule->mask.dport)); 3365 break; 3366 case NPC_TCP_FLAGS: 3367 seq_printf(s, "%d ", rule->packet.tcp_flags); 3368 seq_printf(s, "mask 0x%x\n", rule->mask.tcp_flags); 3369 break; 3370 case NPC_IPSEC_SPI: 3371 seq_printf(s, "0x%x ", ntohl(rule->packet.spi)); 3372 seq_printf(s, "mask 0x%x\n", ntohl(rule->mask.spi)); 3373 break; 3374 case NPC_MPLS1_LBTCBOS: 3375 RVU_DBG_PRINT_MPLS_LBTCBOS(rule->packet.mpls_lse[0], 3376 rule->mask.mpls_lse[0]); 3377 break; 3378 case NPC_MPLS1_TTL: 3379 RVU_DBG_PRINT_MPLS_TTL(rule->packet.mpls_lse[0], 3380 rule->mask.mpls_lse[0]); 3381 break; 3382 case NPC_MPLS2_LBTCBOS: 3383 RVU_DBG_PRINT_MPLS_LBTCBOS(rule->packet.mpls_lse[1], 3384 rule->mask.mpls_lse[1]); 3385 break; 3386 case NPC_MPLS2_TTL: 3387 RVU_DBG_PRINT_MPLS_TTL(rule->packet.mpls_lse[1], 3388 rule->mask.mpls_lse[1]); 3389 break; 3390 case NPC_MPLS3_LBTCBOS: 3391 RVU_DBG_PRINT_MPLS_LBTCBOS(rule->packet.mpls_lse[2], 3392 rule->mask.mpls_lse[2]); 3393 break; 3394 case NPC_MPLS3_TTL: 3395 RVU_DBG_PRINT_MPLS_TTL(rule->packet.mpls_lse[2], 3396 rule->mask.mpls_lse[2]); 3397 break; 3398 case NPC_MPLS4_LBTCBOS: 3399 RVU_DBG_PRINT_MPLS_LBTCBOS(rule->packet.mpls_lse[3], 3400 rule->mask.mpls_lse[3]); 3401 break; 3402 case NPC_MPLS4_TTL: 3403 RVU_DBG_PRINT_MPLS_TTL(rule->packet.mpls_lse[3], 3404 rule->mask.mpls_lse[3]); 3405 break; 3406 case NPC_TYPE_ICMP: 3407 seq_printf(s, "%d ", rule->packet.icmp_type); 3408 seq_printf(s, "mask 0x%x\n", rule->mask.icmp_type); 3409 break; 3410 case NPC_CODE_ICMP: 3411 seq_printf(s, "%d ", rule->packet.icmp_code); 3412 seq_printf(s, "mask 0x%x\n", rule->mask.icmp_code); 3413 break; 3414 default: 3415 seq_puts(s, "\n"); 3416 break; 3417 } 3418 } 3419 } 3420 3421 static void rvu_dbg_npc_mcam_show_action(struct seq_file *s, 3422 struct rvu_npc_mcam_rule *rule) 3423 { 3424 if (is_npc_intf_tx(rule->intf)) { 3425 switch (rule->tx_action.op) { 3426 case NIX_TX_ACTIONOP_DROP: 3427 seq_puts(s, "\taction: Drop\n"); 3428 break; 3429 case NIX_TX_ACTIONOP_UCAST_DEFAULT: 3430 seq_puts(s, "\taction: Unicast to default channel\n"); 3431 break; 3432 case NIX_TX_ACTIONOP_UCAST_CHAN: 3433 seq_printf(s, "\taction: Unicast to channel %d\n", 3434 rule->tx_action.index); 3435 break; 3436 case NIX_TX_ACTIONOP_MCAST: 3437 seq_puts(s, "\taction: Multicast\n"); 3438 break; 3439 case NIX_TX_ACTIONOP_DROP_VIOL: 3440 seq_puts(s, "\taction: Lockdown Violation Drop\n"); 3441 break; 3442 default: 3443 break; 3444 } 3445 } else { 3446 switch (rule->rx_action.op) { 3447 case NIX_RX_ACTIONOP_DROP: 3448 seq_puts(s, "\taction: Drop\n"); 3449 break; 3450 case NIX_RX_ACTIONOP_UCAST: 3451 seq_printf(s, "\taction: Direct to queue %d\n", 3452 rule->rx_action.index); 3453 break; 3454 case NIX_RX_ACTIONOP_RSS: 3455 seq_puts(s, "\taction: RSS\n"); 3456 break; 3457 case NIX_RX_ACTIONOP_UCAST_IPSEC: 3458 seq_puts(s, "\taction: Unicast ipsec\n"); 3459 break; 3460 case NIX_RX_ACTIONOP_MCAST: 3461 seq_puts(s, "\taction: Multicast\n"); 3462 break; 3463 default: 3464 break; 3465 } 3466 } 3467 } 3468 3469 static const char *rvu_dbg_get_intf_name(int intf) 3470 { 3471 switch (intf) { 3472 case NIX_INTFX_RX(0): 3473 return "NIX0_RX"; 3474 case NIX_INTFX_RX(1): 3475 return "NIX1_RX"; 3476 case NIX_INTFX_TX(0): 3477 return "NIX0_TX"; 3478 case NIX_INTFX_TX(1): 3479 return "NIX1_TX"; 3480 default: 3481 break; 3482 } 3483 3484 return "unknown"; 3485 } 3486 3487 static int rvu_dbg_npc_mcam_show_rules(struct seq_file *s, void *unused) 3488 { 3489 struct rvu_npc_mcam_rule *iter; 3490 struct rvu *rvu = s->private; 3491 struct npc_mcam *mcam; 3492 int pf, vf = -1, bank; 3493 u16 target, index; 3494 bool enabled; 3495 u64 hits, off; 3496 int blkaddr; 3497 3498 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3499 if (blkaddr < 0) 3500 return 0; 3501 3502 mcam = &rvu->hw->mcam; 3503 3504 mutex_lock(&mcam->lock); 3505 list_for_each_entry(iter, &mcam->mcam_rules, list) { 3506 pf = rvu_get_pf(rvu->pdev, iter->owner); 3507 seq_printf(s, "\n\tInstalled by: PF%d ", pf); 3508 3509 if (iter->owner & RVU_PFVF_FUNC_MASK) { 3510 vf = (iter->owner & RVU_PFVF_FUNC_MASK) - 1; 3511 seq_printf(s, "VF%d", vf); 3512 } 3513 seq_puts(s, "\n"); 3514 3515 seq_printf(s, "\tdirection: %s\n", is_npc_intf_rx(iter->intf) ? 3516 "RX" : "TX"); 3517 seq_printf(s, "\tinterface: %s\n", 3518 rvu_dbg_get_intf_name(iter->intf)); 3519 seq_printf(s, "\tmcam entry: %d\n", iter->entry); 3520 3521 rvu_dbg_npc_mcam_show_flows(s, iter); 3522 if (is_npc_intf_rx(iter->intf)) { 3523 target = iter->rx_action.pf_func; 3524 pf = rvu_get_pf(rvu->pdev, target); 3525 seq_printf(s, "\tForward to: PF%d ", pf); 3526 3527 if (target & RVU_PFVF_FUNC_MASK) { 3528 vf = (target & RVU_PFVF_FUNC_MASK) - 1; 3529 seq_printf(s, "VF%d", vf); 3530 } 3531 seq_puts(s, "\n"); 3532 seq_printf(s, "\tchannel: 0x%x\n", iter->chan); 3533 seq_printf(s, "\tchannel_mask: 0x%x\n", iter->chan_mask); 3534 } 3535 3536 rvu_dbg_npc_mcam_show_action(s, iter); 3537 3538 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, iter->entry); 3539 seq_printf(s, "\tenabled: %s\n", enabled ? "yes" : "no"); 3540 if (is_cn20k(rvu->pdev)) { 3541 seq_printf(s, "\tpriority: %u\n", iter->hw_prio); 3542 index = iter->entry & (mcam->banksize - 1); 3543 bank = npc_get_bank(mcam, iter->entry); 3544 off = NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(index, bank); 3545 hits = rvu_read64(rvu, blkaddr, off); 3546 seq_printf(s, "\thits: %lld\n", hits); 3547 continue; 3548 } 3549 3550 if (!iter->has_cntr) 3551 continue; 3552 seq_printf(s, "\tcounter: %d\n", iter->cntr); 3553 3554 hits = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(iter->cntr)); 3555 seq_printf(s, "\thits: %lld\n", hits); 3556 } 3557 mutex_unlock(&mcam->lock); 3558 3559 return 0; 3560 } 3561 3562 RVU_DEBUG_SEQ_FOPS(npc_mcam_rules, npc_mcam_show_rules, NULL); 3563 3564 static int rvu_dbg_npc_exact_show_entries(struct seq_file *s, void *unused) 3565 { 3566 struct npc_exact_table_entry *mem_entry[NPC_EXACT_TBL_MAX_WAYS] = { 0 }; 3567 struct npc_exact_table_entry *cam_entry; 3568 struct npc_exact_table *table; 3569 struct rvu *rvu = s->private; 3570 int i, j; 3571 3572 u8 bitmap = 0; 3573 3574 table = rvu->hw->table; 3575 3576 mutex_lock(&table->lock); 3577 3578 /* Check if there is at least one entry in mem table */ 3579 if (!table->mem_tbl_entry_cnt) 3580 goto dump_cam_table; 3581 3582 /* Print table headers */ 3583 seq_puts(s, "\n\tExact Match MEM Table\n"); 3584 seq_puts(s, "Index\t"); 3585 3586 for (i = 0; i < table->mem_table.ways; i++) { 3587 mem_entry[i] = list_first_entry_or_null(&table->lhead_mem_tbl_entry[i], 3588 struct npc_exact_table_entry, list); 3589 3590 seq_printf(s, "Way-%d\t\t\t\t\t", i); 3591 } 3592 3593 seq_puts(s, "\n"); 3594 for (i = 0; i < table->mem_table.ways; i++) 3595 seq_puts(s, "\tChan MAC \t"); 3596 3597 seq_puts(s, "\n\n"); 3598 3599 /* Print mem table entries */ 3600 for (i = 0; i < table->mem_table.depth; i++) { 3601 bitmap = 0; 3602 for (j = 0; j < table->mem_table.ways; j++) { 3603 if (!mem_entry[j]) 3604 continue; 3605 3606 if (mem_entry[j]->index != i) 3607 continue; 3608 3609 bitmap |= BIT(j); 3610 } 3611 3612 /* No valid entries */ 3613 if (!bitmap) 3614 continue; 3615 3616 seq_printf(s, "%d\t", i); 3617 for (j = 0; j < table->mem_table.ways; j++) { 3618 if (!(bitmap & BIT(j))) { 3619 seq_puts(s, "nil\t\t\t\t\t"); 3620 continue; 3621 } 3622 3623 seq_printf(s, "0x%x %pM\t\t\t", mem_entry[j]->chan, 3624 mem_entry[j]->mac); 3625 mem_entry[j] = list_next_entry(mem_entry[j], list); 3626 } 3627 seq_puts(s, "\n"); 3628 } 3629 3630 dump_cam_table: 3631 3632 if (!table->cam_tbl_entry_cnt) 3633 goto done; 3634 3635 seq_puts(s, "\n\tExact Match CAM Table\n"); 3636 seq_puts(s, "index\tchan\tMAC\n"); 3637 3638 /* Traverse cam table entries */ 3639 list_for_each_entry(cam_entry, &table->lhead_cam_tbl_entry, list) { 3640 seq_printf(s, "%d\t0x%x\t%pM\n", cam_entry->index, cam_entry->chan, 3641 cam_entry->mac); 3642 } 3643 3644 done: 3645 mutex_unlock(&table->lock); 3646 return 0; 3647 } 3648 3649 RVU_DEBUG_SEQ_FOPS(npc_exact_entries, npc_exact_show_entries, NULL); 3650 3651 static int rvu_dbg_npc_exact_show_info(struct seq_file *s, void *unused) 3652 { 3653 struct npc_exact_table *table; 3654 struct rvu *rvu = s->private; 3655 int i; 3656 3657 table = rvu->hw->table; 3658 3659 seq_puts(s, "\n\tExact Table Info\n"); 3660 seq_printf(s, "Exact Match Feature : %s\n", 3661 rvu->hw->cap.npc_exact_match_enabled ? "enabled" : "disable"); 3662 if (!rvu->hw->cap.npc_exact_match_enabled) 3663 return 0; 3664 3665 seq_puts(s, "\nMCAM Index\tMAC Filter Rules Count\n"); 3666 for (i = 0; i < table->num_drop_rules; i++) 3667 seq_printf(s, "%d\t\t%d\n", i, table->cnt_cmd_rules[i]); 3668 3669 seq_puts(s, "\nMcam Index\tPromisc Mode Status\n"); 3670 for (i = 0; i < table->num_drop_rules; i++) 3671 seq_printf(s, "%d\t\t%s\n", i, table->promisc_mode[i] ? "on" : "off"); 3672 3673 seq_puts(s, "\n\tMEM Table Info\n"); 3674 seq_printf(s, "Ways : %d\n", table->mem_table.ways); 3675 seq_printf(s, "Depth : %d\n", table->mem_table.depth); 3676 seq_printf(s, "Mask : 0x%llx\n", table->mem_table.mask); 3677 seq_printf(s, "Hash Mask : 0x%x\n", table->mem_table.hash_mask); 3678 seq_printf(s, "Hash Offset : 0x%x\n", table->mem_table.hash_offset); 3679 3680 seq_puts(s, "\n\tCAM Table Info\n"); 3681 seq_printf(s, "Depth : %d\n", table->cam_table.depth); 3682 3683 return 0; 3684 } 3685 3686 RVU_DEBUG_SEQ_FOPS(npc_exact_info, npc_exact_show_info, NULL); 3687 3688 static int rvu_dbg_npc_exact_drop_cnt(struct seq_file *s, void *unused) 3689 { 3690 struct npc_exact_table *table; 3691 struct rvu *rvu = s->private; 3692 struct npc_key_field *field; 3693 u64 cfg, cam1, off; 3694 u16 chan, pcifunc; 3695 int blkaddr, i; 3696 char *str; 3697 3698 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3699 table = rvu->hw->table; 3700 3701 field = &rvu->hw->mcam.rx_key_fields[NPC_CHAN]; 3702 3703 seq_puts(s, "\n\t Exact Hit on drop status\n"); 3704 seq_puts(s, "\npcifunc\tmcam_idx\tHits\tchan\tstatus\n"); 3705 3706 for (i = 0; i < table->num_drop_rules; i++) { 3707 pcifunc = rvu_npc_exact_drop_rule_to_pcifunc(rvu, i); 3708 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(i, 0)); 3709 3710 /* channel will be always in keyword 0 */ 3711 cam1 = rvu_read64(rvu, blkaddr, 3712 NPC_AF_MCAMEX_BANKX_CAMX_W0(i, 0, 1)); 3713 chan = field->kw_mask[0] & cam1; 3714 3715 str = (cfg & 1) ? "enabled" : "disabled"; 3716 if (is_cn20k(rvu->pdev)) { 3717 off = NPC_AF_CN20K_MCAMEX_BANKX_STAT_EXT(i, 0); 3718 seq_printf(s, "0x%x\t%d\t\t%llu\t0x%x\t%s\n", pcifunc, 3719 i, rvu_read64(rvu, blkaddr, off), chan, str); 3720 } else { 3721 off = NPC_AF_MATCH_STATX(table->counter_idx[i]); 3722 seq_printf(s, "0x%x\t%d\t\t%llu\t0x%x\t%s\n", pcifunc, 3723 i, rvu_read64(rvu, blkaddr, off), 3724 chan, str); 3725 } 3726 3727 } 3728 3729 return 0; 3730 } 3731 3732 RVU_DEBUG_SEQ_FOPS(npc_exact_drop_cnt, npc_exact_drop_cnt, NULL); 3733 3734 static void rvu_dbg_npc_init(struct rvu *rvu) 3735 { 3736 rvu->rvu_dbg.npc = debugfs_create_dir("npc", rvu->rvu_dbg.root); 3737 3738 debugfs_create_file("mcam_info", 0444, rvu->rvu_dbg.npc, rvu, 3739 &rvu_dbg_npc_mcam_info_fops); 3740 debugfs_create_file("mcam_rules", 0444, rvu->rvu_dbg.npc, rvu, 3741 &rvu_dbg_npc_mcam_rules_fops); 3742 3743 debugfs_create_file("rx_miss_act_stats", 0444, rvu->rvu_dbg.npc, rvu, 3744 &rvu_dbg_npc_rx_miss_act_fops); 3745 3746 if (is_cn20k(rvu->pdev)) 3747 npc_cn20k_debugfs_init(rvu); 3748 3749 if (!rvu->hw->cap.npc_exact_match_enabled) 3750 return; 3751 3752 debugfs_create_file("exact_entries", 0444, rvu->rvu_dbg.npc, rvu, 3753 &rvu_dbg_npc_exact_entries_fops); 3754 3755 debugfs_create_file("exact_info", 0444, rvu->rvu_dbg.npc, rvu, 3756 &rvu_dbg_npc_exact_info_fops); 3757 3758 debugfs_create_file("exact_drop_cnt", 0444, rvu->rvu_dbg.npc, rvu, 3759 &rvu_dbg_npc_exact_drop_cnt_fops); 3760 3761 } 3762 3763 static int cpt_eng_sts_display(struct seq_file *filp, u8 eng_type) 3764 { 3765 struct cpt_ctx *ctx = filp->private; 3766 u64 busy_sts = 0, free_sts = 0; 3767 u32 e_min = 0, e_max = 0, e, i; 3768 u16 max_ses, max_ies, max_aes; 3769 struct rvu *rvu = ctx->rvu; 3770 int blkaddr = ctx->blkaddr; 3771 u64 reg; 3772 3773 reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1); 3774 max_ses = reg & 0xffff; 3775 max_ies = (reg >> 16) & 0xffff; 3776 max_aes = (reg >> 32) & 0xffff; 3777 3778 switch (eng_type) { 3779 case CPT_AE_TYPE: 3780 e_min = max_ses + max_ies; 3781 e_max = max_ses + max_ies + max_aes; 3782 break; 3783 case CPT_SE_TYPE: 3784 e_min = 0; 3785 e_max = max_ses; 3786 break; 3787 case CPT_IE_TYPE: 3788 e_min = max_ses; 3789 e_max = max_ses + max_ies; 3790 break; 3791 default: 3792 return -EINVAL; 3793 } 3794 3795 for (e = e_min, i = 0; e < e_max; e++, i++) { 3796 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); 3797 if (reg & 0x1) 3798 busy_sts |= 1ULL << i; 3799 3800 if (reg & 0x2) 3801 free_sts |= 1ULL << i; 3802 } 3803 seq_printf(filp, "FREE STS : 0x%016llx\n", free_sts); 3804 seq_printf(filp, "BUSY STS : 0x%016llx\n", busy_sts); 3805 3806 return 0; 3807 } 3808 3809 static int rvu_dbg_cpt_ae_sts_display(struct seq_file *filp, void *unused) 3810 { 3811 return cpt_eng_sts_display(filp, CPT_AE_TYPE); 3812 } 3813 3814 RVU_DEBUG_SEQ_FOPS(cpt_ae_sts, cpt_ae_sts_display, NULL); 3815 3816 static int rvu_dbg_cpt_se_sts_display(struct seq_file *filp, void *unused) 3817 { 3818 return cpt_eng_sts_display(filp, CPT_SE_TYPE); 3819 } 3820 3821 RVU_DEBUG_SEQ_FOPS(cpt_se_sts, cpt_se_sts_display, NULL); 3822 3823 static int rvu_dbg_cpt_ie_sts_display(struct seq_file *filp, void *unused) 3824 { 3825 return cpt_eng_sts_display(filp, CPT_IE_TYPE); 3826 } 3827 3828 RVU_DEBUG_SEQ_FOPS(cpt_ie_sts, cpt_ie_sts_display, NULL); 3829 3830 static int rvu_dbg_cpt_engines_info_display(struct seq_file *filp, void *unused) 3831 { 3832 struct cpt_ctx *ctx = filp->private; 3833 u16 max_ses, max_ies, max_aes; 3834 struct rvu *rvu = ctx->rvu; 3835 int blkaddr = ctx->blkaddr; 3836 u32 e_max, e; 3837 u64 reg; 3838 3839 reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1); 3840 max_ses = reg & 0xffff; 3841 max_ies = (reg >> 16) & 0xffff; 3842 max_aes = (reg >> 32) & 0xffff; 3843 3844 e_max = max_ses + max_ies + max_aes; 3845 3846 seq_puts(filp, "===========================================\n"); 3847 for (e = 0; e < e_max; e++) { 3848 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(e)); 3849 seq_printf(filp, "CPT Engine[%u] Group Enable 0x%02llx\n", e, 3850 reg & 0xff); 3851 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_ACTIVE(e)); 3852 seq_printf(filp, "CPT Engine[%u] Active Info 0x%llx\n", e, 3853 reg); 3854 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL(e)); 3855 seq_printf(filp, "CPT Engine[%u] Control 0x%llx\n", e, 3856 reg); 3857 seq_puts(filp, "===========================================\n"); 3858 } 3859 return 0; 3860 } 3861 3862 RVU_DEBUG_SEQ_FOPS(cpt_engines_info, cpt_engines_info_display, NULL); 3863 3864 static int rvu_dbg_cpt_lfs_info_display(struct seq_file *filp, void *unused) 3865 { 3866 struct cpt_ctx *ctx = filp->private; 3867 int blkaddr = ctx->blkaddr; 3868 struct rvu *rvu = ctx->rvu; 3869 struct rvu_block *block; 3870 struct rvu_hwinfo *hw; 3871 u64 reg; 3872 u32 lf; 3873 3874 hw = rvu->hw; 3875 block = &hw->block[blkaddr]; 3876 if (!block->lf.bmap) 3877 return -ENODEV; 3878 3879 seq_puts(filp, "===========================================\n"); 3880 for (lf = 0; lf < block->lf.max; lf++) { 3881 reg = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(lf)); 3882 seq_printf(filp, "CPT Lf[%u] CTL 0x%llx\n", lf, reg); 3883 reg = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(lf)); 3884 seq_printf(filp, "CPT Lf[%u] CTL2 0x%llx\n", lf, reg); 3885 reg = rvu_read64(rvu, blkaddr, CPT_AF_LFX_PTR_CTL(lf)); 3886 seq_printf(filp, "CPT Lf[%u] PTR_CTL 0x%llx\n", lf, reg); 3887 reg = rvu_read64(rvu, blkaddr, block->lfcfg_reg | 3888 (lf << block->lfshift)); 3889 seq_printf(filp, "CPT Lf[%u] CFG 0x%llx\n", lf, reg); 3890 seq_puts(filp, "===========================================\n"); 3891 } 3892 return 0; 3893 } 3894 3895 RVU_DEBUG_SEQ_FOPS(cpt_lfs_info, cpt_lfs_info_display, NULL); 3896 3897 static int rvu_dbg_cpt_err_info_display(struct seq_file *filp, void *unused) 3898 { 3899 struct cpt_ctx *ctx = filp->private; 3900 struct rvu *rvu = ctx->rvu; 3901 int blkaddr = ctx->blkaddr; 3902 u64 reg0, reg1; 3903 3904 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(0)); 3905 reg1 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(1)); 3906 seq_printf(filp, "CPT_AF_FLTX_INT: 0x%llx 0x%llx\n", reg0, reg1); 3907 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_PSNX_EXE(0)); 3908 reg1 = rvu_read64(rvu, blkaddr, CPT_AF_PSNX_EXE(1)); 3909 seq_printf(filp, "CPT_AF_PSNX_EXE: 0x%llx 0x%llx\n", reg0, reg1); 3910 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_PSNX_LF(0)); 3911 seq_printf(filp, "CPT_AF_PSNX_LF: 0x%llx\n", reg0); 3912 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_RVU_INT); 3913 seq_printf(filp, "CPT_AF_RVU_INT: 0x%llx\n", reg0); 3914 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_RAS_INT); 3915 seq_printf(filp, "CPT_AF_RAS_INT: 0x%llx\n", reg0); 3916 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_EXE_ERR_INFO); 3917 seq_printf(filp, "CPT_AF_EXE_ERR_INFO: 0x%llx\n", reg0); 3918 3919 return 0; 3920 } 3921 3922 RVU_DEBUG_SEQ_FOPS(cpt_err_info, cpt_err_info_display, NULL); 3923 3924 static int rvu_dbg_cpt_pc_display(struct seq_file *filp, void *unused) 3925 { 3926 struct cpt_ctx *ctx = filp->private; 3927 struct rvu *rvu = ctx->rvu; 3928 int blkaddr = ctx->blkaddr; 3929 u64 reg; 3930 3931 reg = rvu_read64(rvu, blkaddr, CPT_AF_INST_REQ_PC); 3932 seq_printf(filp, "CPT instruction requests %llu\n", reg); 3933 reg = rvu_read64(rvu, blkaddr, CPT_AF_INST_LATENCY_PC); 3934 seq_printf(filp, "CPT instruction latency %llu\n", reg); 3935 reg = rvu_read64(rvu, blkaddr, CPT_AF_RD_REQ_PC); 3936 seq_printf(filp, "CPT NCB read requests %llu\n", reg); 3937 reg = rvu_read64(rvu, blkaddr, CPT_AF_RD_LATENCY_PC); 3938 seq_printf(filp, "CPT NCB read latency %llu\n", reg); 3939 reg = rvu_read64(rvu, blkaddr, CPT_AF_RD_UC_PC); 3940 seq_printf(filp, "CPT read requests caused by UC fills %llu\n", reg); 3941 reg = rvu_read64(rvu, blkaddr, CPT_AF_ACTIVE_CYCLES_PC); 3942 seq_printf(filp, "CPT active cycles pc %llu\n", reg); 3943 reg = rvu_read64(rvu, blkaddr, CPT_AF_CPTCLK_CNT); 3944 seq_printf(filp, "CPT clock count pc %llu\n", reg); 3945 3946 return 0; 3947 } 3948 3949 RVU_DEBUG_SEQ_FOPS(cpt_pc, cpt_pc_display, NULL); 3950 3951 static void rvu_dbg_cpt_init(struct rvu *rvu, int blkaddr) 3952 { 3953 struct cpt_ctx *ctx; 3954 3955 if (!is_block_implemented(rvu->hw, blkaddr)) 3956 return; 3957 3958 if (blkaddr == BLKADDR_CPT0) { 3959 rvu->rvu_dbg.cpt = debugfs_create_dir("cpt", rvu->rvu_dbg.root); 3960 ctx = &rvu->rvu_dbg.cpt_ctx[0]; 3961 ctx->blkaddr = BLKADDR_CPT0; 3962 ctx->rvu = rvu; 3963 } else { 3964 rvu->rvu_dbg.cpt = debugfs_create_dir("cpt1", 3965 rvu->rvu_dbg.root); 3966 ctx = &rvu->rvu_dbg.cpt_ctx[1]; 3967 ctx->blkaddr = BLKADDR_CPT1; 3968 ctx->rvu = rvu; 3969 } 3970 3971 debugfs_create_file("cpt_pc", 0600, rvu->rvu_dbg.cpt, ctx, 3972 &rvu_dbg_cpt_pc_fops); 3973 debugfs_create_file("cpt_ae_sts", 0600, rvu->rvu_dbg.cpt, ctx, 3974 &rvu_dbg_cpt_ae_sts_fops); 3975 debugfs_create_file("cpt_se_sts", 0600, rvu->rvu_dbg.cpt, ctx, 3976 &rvu_dbg_cpt_se_sts_fops); 3977 debugfs_create_file("cpt_ie_sts", 0600, rvu->rvu_dbg.cpt, ctx, 3978 &rvu_dbg_cpt_ie_sts_fops); 3979 debugfs_create_file("cpt_engines_info", 0600, rvu->rvu_dbg.cpt, ctx, 3980 &rvu_dbg_cpt_engines_info_fops); 3981 debugfs_create_file("cpt_lfs_info", 0600, rvu->rvu_dbg.cpt, ctx, 3982 &rvu_dbg_cpt_lfs_info_fops); 3983 debugfs_create_file("cpt_err_info", 0600, rvu->rvu_dbg.cpt, ctx, 3984 &rvu_dbg_cpt_err_info_fops); 3985 } 3986 3987 static const char *rvu_get_dbg_dir_name(struct rvu *rvu) 3988 { 3989 if (is_cn20k(rvu->pdev)) 3990 return "cn20k"; 3991 3992 if (!is_rvu_otx2(rvu)) 3993 return "cn10k"; 3994 else 3995 return "octeontx2"; 3996 } 3997 3998 void rvu_dbg_init(struct rvu *rvu) 3999 { 4000 rvu->rvu_dbg.root = debugfs_create_dir(rvu_get_dbg_dir_name(rvu), NULL); 4001 4002 debugfs_create_file("rsrc_alloc", 0444, rvu->rvu_dbg.root, rvu, 4003 &rvu_dbg_rsrc_status_fops); 4004 4005 if (!is_rvu_otx2(rvu)) 4006 debugfs_create_file("lmtst_map_table", 0444, rvu->rvu_dbg.root, 4007 rvu, &rvu_dbg_lmtst_map_table_fops); 4008 4009 debugfs_create_file("rvu_fwdata", 0444, rvu->rvu_dbg.root, rvu, 4010 &rvu_dbg_rvu_fwdata_fops); 4011 4012 if (!cgx_get_cgxcnt_max()) 4013 goto create; 4014 4015 if (is_rvu_otx2(rvu)) 4016 debugfs_create_file("rvu_pf_cgx_map", 0444, rvu->rvu_dbg.root, 4017 rvu, &rvu_dbg_rvu_pf_cgx_map_fops); 4018 else 4019 debugfs_create_file("rvu_pf_rpm_map", 0444, rvu->rvu_dbg.root, 4020 rvu, &rvu_dbg_rvu_pf_cgx_map_fops); 4021 4022 create: 4023 rvu_dbg_npa_init(rvu); 4024 rvu_dbg_nix_init(rvu, BLKADDR_NIX0); 4025 4026 rvu_dbg_nix_init(rvu, BLKADDR_NIX1); 4027 rvu_dbg_cgx_init(rvu); 4028 rvu_dbg_npc_init(rvu); 4029 rvu_dbg_cpt_init(rvu, BLKADDR_CPT0); 4030 rvu_dbg_cpt_init(rvu, BLKADDR_CPT1); 4031 rvu_dbg_mcs_init(rvu); 4032 } 4033 4034 void rvu_dbg_exit(struct rvu *rvu) 4035 { 4036 debugfs_remove_recursive(rvu->rvu_dbg.root); 4037 } 4038 4039 #endif /* CONFIG_DEBUG_FS */ 4040