xref: /linux/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3  * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4  *
5  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6  *
7  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
8  */
9 
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/of_net.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/delay.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22 #include <linux/pm_runtime.h>
23 
24 #include "stmmac_platform.h"
25 
26 struct rk_priv_data;
27 struct rk_gmac_ops {
28 	void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
29 			     int tx_delay, int rx_delay);
30 	void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
31 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
32 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
33 	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
34 				    bool enable);
35 	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36 	bool regs_valid;
37 	u32 regs[];
38 };
39 
40 static const char * const rk_clocks[] = {
41 	"aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
42 };
43 
44 static const char * const rk_rmii_clocks[] = {
45 	"mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
46 };
47 
48 enum rk_clocks_index {
49 	RK_ACLK_MAC = 0,
50 	RK_PCLK_MAC,
51 	RK_MAC_CLK_TX,
52 	RK_CLK_MAC_SPEED,
53 	RK_MAC_CLK_RX,
54 	RK_CLK_MAC_REF,
55 	RK_CLK_MAC_REFOUT,
56 };
57 
58 struct rk_priv_data {
59 	struct platform_device *pdev;
60 	phy_interface_t phy_iface;
61 	int id;
62 	struct regulator *regulator;
63 	bool suspended;
64 	const struct rk_gmac_ops *ops;
65 
66 	bool clk_enabled;
67 	bool clock_input;
68 	bool integrated_phy;
69 
70 	struct clk_bulk_data *clks;
71 	int num_clks;
72 	struct clk *clk_mac;
73 	struct clk *clk_phy;
74 
75 	struct reset_control *phy_reset;
76 
77 	int tx_delay;
78 	int rx_delay;
79 
80 	struct regmap *grf;
81 	struct regmap *php_grf;
82 };
83 
84 #define HIWORD_UPDATE(val, mask, shift) \
85 		((val) << (shift) | (mask) << ((shift) + 16))
86 
87 #define GRF_BIT(nr)	(BIT(nr) | BIT(nr+16))
88 #define GRF_CLR_BIT(nr)	(BIT(nr+16))
89 
90 #define DELAY_ENABLE(soc, tx, rx) \
91 	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
92 	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
93 
94 #define PX30_GRF_GMAC_CON1		0x0904
95 
96 /* PX30_GRF_GMAC_CON1 */
97 #define PX30_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
98 					 GRF_BIT(6))
99 #define PX30_GMAC_SPEED_10M		GRF_CLR_BIT(2)
100 #define PX30_GMAC_SPEED_100M		GRF_BIT(2)
101 
px30_set_to_rmii(struct rk_priv_data * bsp_priv)102 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
103 {
104 	struct device *dev = &bsp_priv->pdev->dev;
105 
106 	if (IS_ERR(bsp_priv->grf)) {
107 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
108 		return;
109 	}
110 
111 	regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
112 		     PX30_GMAC_PHY_INTF_SEL_RMII);
113 }
114 
px30_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)115 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
116 {
117 	struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
118 	struct device *dev = &bsp_priv->pdev->dev;
119 	int ret;
120 
121 	if (!clk_mac_speed) {
122 		dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
123 		return;
124 	}
125 
126 	if (speed == 10) {
127 		regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
128 			     PX30_GMAC_SPEED_10M);
129 
130 		ret = clk_set_rate(clk_mac_speed, 2500000);
131 		if (ret)
132 			dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
133 				__func__, ret);
134 	} else if (speed == 100) {
135 		regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
136 			     PX30_GMAC_SPEED_100M);
137 
138 		ret = clk_set_rate(clk_mac_speed, 25000000);
139 		if (ret)
140 			dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
141 				__func__, ret);
142 
143 	} else {
144 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
145 	}
146 }
147 
148 static const struct rk_gmac_ops px30_ops = {
149 	.set_to_rmii = px30_set_to_rmii,
150 	.set_rmii_speed = px30_set_rmii_speed,
151 };
152 
153 #define RK3128_GRF_MAC_CON0	0x0168
154 #define RK3128_GRF_MAC_CON1	0x016c
155 
156 /* RK3128_GRF_MAC_CON0 */
157 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
158 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
159 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
160 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
161 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
162 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
163 
164 /* RK3128_GRF_MAC_CON1 */
165 #define RK3128_GMAC_PHY_INTF_SEL_RGMII	\
166 		(GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
167 #define RK3128_GMAC_PHY_INTF_SEL_RMII	\
168 		(GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
169 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
170 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
171 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
172 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
173 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
174 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
175 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
176 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
177 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
178 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
179 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
180 
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)181 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
182 				int tx_delay, int rx_delay)
183 {
184 	struct device *dev = &bsp_priv->pdev->dev;
185 
186 	if (IS_ERR(bsp_priv->grf)) {
187 		dev_err(dev, "Missing rockchip,grf property\n");
188 		return;
189 	}
190 
191 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
192 		     RK3128_GMAC_PHY_INTF_SEL_RGMII |
193 		     RK3128_GMAC_RMII_MODE_CLR);
194 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
195 		     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
196 		     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
197 		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
198 }
199 
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)200 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
201 {
202 	struct device *dev = &bsp_priv->pdev->dev;
203 
204 	if (IS_ERR(bsp_priv->grf)) {
205 		dev_err(dev, "Missing rockchip,grf property\n");
206 		return;
207 	}
208 
209 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
210 		     RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
211 }
212 
rk3128_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)213 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
214 {
215 	struct device *dev = &bsp_priv->pdev->dev;
216 
217 	if (IS_ERR(bsp_priv->grf)) {
218 		dev_err(dev, "Missing rockchip,grf property\n");
219 		return;
220 	}
221 
222 	if (speed == 10)
223 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
224 			     RK3128_GMAC_CLK_2_5M);
225 	else if (speed == 100)
226 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
227 			     RK3128_GMAC_CLK_25M);
228 	else if (speed == 1000)
229 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
230 			     RK3128_GMAC_CLK_125M);
231 	else
232 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
233 }
234 
rk3128_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)235 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
236 {
237 	struct device *dev = &bsp_priv->pdev->dev;
238 
239 	if (IS_ERR(bsp_priv->grf)) {
240 		dev_err(dev, "Missing rockchip,grf property\n");
241 		return;
242 	}
243 
244 	if (speed == 10) {
245 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
246 			     RK3128_GMAC_RMII_CLK_2_5M |
247 			     RK3128_GMAC_SPEED_10M);
248 	} else if (speed == 100) {
249 		regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
250 			     RK3128_GMAC_RMII_CLK_25M |
251 			     RK3128_GMAC_SPEED_100M);
252 	} else {
253 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
254 	}
255 }
256 
257 static const struct rk_gmac_ops rk3128_ops = {
258 	.set_to_rgmii = rk3128_set_to_rgmii,
259 	.set_to_rmii = rk3128_set_to_rmii,
260 	.set_rgmii_speed = rk3128_set_rgmii_speed,
261 	.set_rmii_speed = rk3128_set_rmii_speed,
262 };
263 
264 #define RK3228_GRF_MAC_CON0	0x0900
265 #define RK3228_GRF_MAC_CON1	0x0904
266 
267 #define RK3228_GRF_CON_MUX	0x50
268 
269 /* RK3228_GRF_MAC_CON0 */
270 #define RK3228_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
271 #define RK3228_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
272 
273 /* RK3228_GRF_MAC_CON1 */
274 #define RK3228_GMAC_PHY_INTF_SEL_RGMII	\
275 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
276 #define RK3228_GMAC_PHY_INTF_SEL_RMII	\
277 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
278 #define RK3228_GMAC_FLOW_CTRL		GRF_BIT(3)
279 #define RK3228_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
280 #define RK3228_GMAC_SPEED_10M		GRF_CLR_BIT(2)
281 #define RK3228_GMAC_SPEED_100M		GRF_BIT(2)
282 #define RK3228_GMAC_RMII_CLK_25M	GRF_BIT(7)
283 #define RK3228_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
284 #define RK3228_GMAC_CLK_125M		(GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
285 #define RK3228_GMAC_CLK_25M		(GRF_BIT(8) | GRF_BIT(9))
286 #define RK3228_GMAC_CLK_2_5M		(GRF_CLR_BIT(8) | GRF_BIT(9))
287 #define RK3228_GMAC_RMII_MODE		GRF_BIT(10)
288 #define RK3228_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(10)
289 #define RK3228_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(0)
290 #define RK3228_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
291 #define RK3228_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
292 #define RK3228_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
293 
294 /* RK3228_GRF_COM_MUX */
295 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY	GRF_BIT(15)
296 
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)297 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
298 				int tx_delay, int rx_delay)
299 {
300 	struct device *dev = &bsp_priv->pdev->dev;
301 
302 	if (IS_ERR(bsp_priv->grf)) {
303 		dev_err(dev, "Missing rockchip,grf property\n");
304 		return;
305 	}
306 
307 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
308 		     RK3228_GMAC_PHY_INTF_SEL_RGMII |
309 		     RK3228_GMAC_RMII_MODE_CLR |
310 		     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
311 
312 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
313 		     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
314 		     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
315 }
316 
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)317 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
318 {
319 	struct device *dev = &bsp_priv->pdev->dev;
320 
321 	if (IS_ERR(bsp_priv->grf)) {
322 		dev_err(dev, "Missing rockchip,grf property\n");
323 		return;
324 	}
325 
326 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
327 		     RK3228_GMAC_PHY_INTF_SEL_RMII |
328 		     RK3228_GMAC_RMII_MODE);
329 
330 	/* set MAC to RMII mode */
331 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
332 }
333 
rk3228_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)334 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
335 {
336 	struct device *dev = &bsp_priv->pdev->dev;
337 
338 	if (IS_ERR(bsp_priv->grf)) {
339 		dev_err(dev, "Missing rockchip,grf property\n");
340 		return;
341 	}
342 
343 	if (speed == 10)
344 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
345 			     RK3228_GMAC_CLK_2_5M);
346 	else if (speed == 100)
347 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
348 			     RK3228_GMAC_CLK_25M);
349 	else if (speed == 1000)
350 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
351 			     RK3228_GMAC_CLK_125M);
352 	else
353 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
354 }
355 
rk3228_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)356 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
357 {
358 	struct device *dev = &bsp_priv->pdev->dev;
359 
360 	if (IS_ERR(bsp_priv->grf)) {
361 		dev_err(dev, "Missing rockchip,grf property\n");
362 		return;
363 	}
364 
365 	if (speed == 10)
366 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
367 			     RK3228_GMAC_RMII_CLK_2_5M |
368 			     RK3228_GMAC_SPEED_10M);
369 	else if (speed == 100)
370 		regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
371 			     RK3228_GMAC_RMII_CLK_25M |
372 			     RK3228_GMAC_SPEED_100M);
373 	else
374 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
375 }
376 
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)377 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
378 {
379 	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
380 		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
381 }
382 
383 static const struct rk_gmac_ops rk3228_ops = {
384 	.set_to_rgmii = rk3228_set_to_rgmii,
385 	.set_to_rmii = rk3228_set_to_rmii,
386 	.set_rgmii_speed = rk3228_set_rgmii_speed,
387 	.set_rmii_speed = rk3228_set_rmii_speed,
388 	.integrated_phy_powerup =  rk3228_integrated_phy_powerup,
389 };
390 
391 #define RK3288_GRF_SOC_CON1	0x0248
392 #define RK3288_GRF_SOC_CON3	0x0250
393 
394 /*RK3288_GRF_SOC_CON1*/
395 #define RK3288_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(6) | GRF_CLR_BIT(7) | \
396 					 GRF_CLR_BIT(8))
397 #define RK3288_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
398 					 GRF_BIT(8))
399 #define RK3288_GMAC_FLOW_CTRL		GRF_BIT(9)
400 #define RK3288_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(9)
401 #define RK3288_GMAC_SPEED_10M		GRF_CLR_BIT(10)
402 #define RK3288_GMAC_SPEED_100M		GRF_BIT(10)
403 #define RK3288_GMAC_RMII_CLK_25M	GRF_BIT(11)
404 #define RK3288_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(11)
405 #define RK3288_GMAC_CLK_125M		(GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
406 #define RK3288_GMAC_CLK_25M		(GRF_BIT(12) | GRF_BIT(13))
407 #define RK3288_GMAC_CLK_2_5M		(GRF_CLR_BIT(12) | GRF_BIT(13))
408 #define RK3288_GMAC_RMII_MODE		GRF_BIT(14)
409 #define RK3288_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(14)
410 
411 /*RK3288_GRF_SOC_CON3*/
412 #define RK3288_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
413 #define RK3288_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
414 #define RK3288_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
415 #define RK3288_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
416 #define RK3288_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
417 #define RK3288_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
418 
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)419 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
420 				int tx_delay, int rx_delay)
421 {
422 	struct device *dev = &bsp_priv->pdev->dev;
423 
424 	if (IS_ERR(bsp_priv->grf)) {
425 		dev_err(dev, "Missing rockchip,grf property\n");
426 		return;
427 	}
428 
429 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
430 		     RK3288_GMAC_PHY_INTF_SEL_RGMII |
431 		     RK3288_GMAC_RMII_MODE_CLR);
432 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
433 		     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
434 		     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
435 		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
436 }
437 
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)438 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
439 {
440 	struct device *dev = &bsp_priv->pdev->dev;
441 
442 	if (IS_ERR(bsp_priv->grf)) {
443 		dev_err(dev, "Missing rockchip,grf property\n");
444 		return;
445 	}
446 
447 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
448 		     RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
449 }
450 
rk3288_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)451 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
452 {
453 	struct device *dev = &bsp_priv->pdev->dev;
454 
455 	if (IS_ERR(bsp_priv->grf)) {
456 		dev_err(dev, "Missing rockchip,grf property\n");
457 		return;
458 	}
459 
460 	if (speed == 10)
461 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
462 			     RK3288_GMAC_CLK_2_5M);
463 	else if (speed == 100)
464 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
465 			     RK3288_GMAC_CLK_25M);
466 	else if (speed == 1000)
467 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
468 			     RK3288_GMAC_CLK_125M);
469 	else
470 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
471 }
472 
rk3288_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)473 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
474 {
475 	struct device *dev = &bsp_priv->pdev->dev;
476 
477 	if (IS_ERR(bsp_priv->grf)) {
478 		dev_err(dev, "Missing rockchip,grf property\n");
479 		return;
480 	}
481 
482 	if (speed == 10) {
483 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
484 			     RK3288_GMAC_RMII_CLK_2_5M |
485 			     RK3288_GMAC_SPEED_10M);
486 	} else if (speed == 100) {
487 		regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
488 			     RK3288_GMAC_RMII_CLK_25M |
489 			     RK3288_GMAC_SPEED_100M);
490 	} else {
491 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
492 	}
493 }
494 
495 static const struct rk_gmac_ops rk3288_ops = {
496 	.set_to_rgmii = rk3288_set_to_rgmii,
497 	.set_to_rmii = rk3288_set_to_rmii,
498 	.set_rgmii_speed = rk3288_set_rgmii_speed,
499 	.set_rmii_speed = rk3288_set_rmii_speed,
500 };
501 
502 #define RK3308_GRF_MAC_CON0		0x04a0
503 
504 /* RK3308_GRF_MAC_CON0 */
505 #define RK3308_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
506 					GRF_BIT(4))
507 #define RK3308_GMAC_FLOW_CTRL		GRF_BIT(3)
508 #define RK3308_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
509 #define RK3308_GMAC_SPEED_10M		GRF_CLR_BIT(0)
510 #define RK3308_GMAC_SPEED_100M		GRF_BIT(0)
511 
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)512 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
513 {
514 	struct device *dev = &bsp_priv->pdev->dev;
515 
516 	if (IS_ERR(bsp_priv->grf)) {
517 		dev_err(dev, "Missing rockchip,grf property\n");
518 		return;
519 	}
520 
521 	regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
522 		     RK3308_GMAC_PHY_INTF_SEL_RMII);
523 }
524 
rk3308_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)525 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
526 {
527 	struct device *dev = &bsp_priv->pdev->dev;
528 
529 	if (IS_ERR(bsp_priv->grf)) {
530 		dev_err(dev, "Missing rockchip,grf property\n");
531 		return;
532 	}
533 
534 	if (speed == 10) {
535 		regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
536 			     RK3308_GMAC_SPEED_10M);
537 	} else if (speed == 100) {
538 		regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
539 			     RK3308_GMAC_SPEED_100M);
540 	} else {
541 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
542 	}
543 }
544 
545 static const struct rk_gmac_ops rk3308_ops = {
546 	.set_to_rmii = rk3308_set_to_rmii,
547 	.set_rmii_speed = rk3308_set_rmii_speed,
548 };
549 
550 #define RK3328_GRF_MAC_CON0	0x0900
551 #define RK3328_GRF_MAC_CON1	0x0904
552 #define RK3328_GRF_MAC_CON2	0x0908
553 #define RK3328_GRF_MACPHY_CON1	0xb04
554 
555 /* RK3328_GRF_MAC_CON0 */
556 #define RK3328_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 7)
557 #define RK3328_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
558 
559 /* RK3328_GRF_MAC_CON1 */
560 #define RK3328_GMAC_PHY_INTF_SEL_RGMII	\
561 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
562 #define RK3328_GMAC_PHY_INTF_SEL_RMII	\
563 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
564 #define RK3328_GMAC_FLOW_CTRL		GRF_BIT(3)
565 #define RK3328_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
566 #define RK3328_GMAC_SPEED_10M		GRF_CLR_BIT(2)
567 #define RK3328_GMAC_SPEED_100M		GRF_BIT(2)
568 #define RK3328_GMAC_RMII_CLK_25M	GRF_BIT(7)
569 #define RK3328_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
570 #define RK3328_GMAC_CLK_125M		(GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
571 #define RK3328_GMAC_CLK_25M		(GRF_BIT(11) | GRF_BIT(12))
572 #define RK3328_GMAC_CLK_2_5M		(GRF_CLR_BIT(11) | GRF_BIT(12))
573 #define RK3328_GMAC_RMII_MODE		GRF_BIT(9)
574 #define RK3328_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(9)
575 #define RK3328_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(0)
576 #define RK3328_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
577 #define RK3328_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(1)
578 #define RK3328_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
579 
580 /* RK3328_GRF_MACPHY_CON1 */
581 #define RK3328_MACPHY_RMII_MODE		GRF_BIT(9)
582 
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)583 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
584 				int tx_delay, int rx_delay)
585 {
586 	struct device *dev = &bsp_priv->pdev->dev;
587 
588 	if (IS_ERR(bsp_priv->grf)) {
589 		dev_err(dev, "Missing rockchip,grf property\n");
590 		return;
591 	}
592 
593 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
594 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
595 		     RK3328_GMAC_RMII_MODE_CLR |
596 		     RK3328_GMAC_RXCLK_DLY_ENABLE |
597 		     RK3328_GMAC_TXCLK_DLY_ENABLE);
598 
599 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
600 		     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
601 		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
602 }
603 
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)604 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
605 {
606 	struct device *dev = &bsp_priv->pdev->dev;
607 	unsigned int reg;
608 
609 	if (IS_ERR(bsp_priv->grf)) {
610 		dev_err(dev, "Missing rockchip,grf property\n");
611 		return;
612 	}
613 
614 	reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
615 		  RK3328_GRF_MAC_CON1;
616 
617 	regmap_write(bsp_priv->grf, reg,
618 		     RK3328_GMAC_PHY_INTF_SEL_RMII |
619 		     RK3328_GMAC_RMII_MODE);
620 }
621 
rk3328_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)622 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
623 {
624 	struct device *dev = &bsp_priv->pdev->dev;
625 
626 	if (IS_ERR(bsp_priv->grf)) {
627 		dev_err(dev, "Missing rockchip,grf property\n");
628 		return;
629 	}
630 
631 	if (speed == 10)
632 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
633 			     RK3328_GMAC_CLK_2_5M);
634 	else if (speed == 100)
635 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
636 			     RK3328_GMAC_CLK_25M);
637 	else if (speed == 1000)
638 		regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
639 			     RK3328_GMAC_CLK_125M);
640 	else
641 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
642 }
643 
rk3328_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)644 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
645 {
646 	struct device *dev = &bsp_priv->pdev->dev;
647 	unsigned int reg;
648 
649 	if (IS_ERR(bsp_priv->grf)) {
650 		dev_err(dev, "Missing rockchip,grf property\n");
651 		return;
652 	}
653 
654 	reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
655 		  RK3328_GRF_MAC_CON1;
656 
657 	if (speed == 10)
658 		regmap_write(bsp_priv->grf, reg,
659 			     RK3328_GMAC_RMII_CLK_2_5M |
660 			     RK3328_GMAC_SPEED_10M);
661 	else if (speed == 100)
662 		regmap_write(bsp_priv->grf, reg,
663 			     RK3328_GMAC_RMII_CLK_25M |
664 			     RK3328_GMAC_SPEED_100M);
665 	else
666 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
667 }
668 
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)669 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
670 {
671 	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
672 		     RK3328_MACPHY_RMII_MODE);
673 }
674 
675 static const struct rk_gmac_ops rk3328_ops = {
676 	.set_to_rgmii = rk3328_set_to_rgmii,
677 	.set_to_rmii = rk3328_set_to_rmii,
678 	.set_rgmii_speed = rk3328_set_rgmii_speed,
679 	.set_rmii_speed = rk3328_set_rmii_speed,
680 	.integrated_phy_powerup =  rk3328_integrated_phy_powerup,
681 };
682 
683 #define RK3366_GRF_SOC_CON6	0x0418
684 #define RK3366_GRF_SOC_CON7	0x041c
685 
686 /* RK3366_GRF_SOC_CON6 */
687 #define RK3366_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
688 					 GRF_CLR_BIT(11))
689 #define RK3366_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
690 					 GRF_BIT(11))
691 #define RK3366_GMAC_FLOW_CTRL		GRF_BIT(8)
692 #define RK3366_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
693 #define RK3366_GMAC_SPEED_10M		GRF_CLR_BIT(7)
694 #define RK3366_GMAC_SPEED_100M		GRF_BIT(7)
695 #define RK3366_GMAC_RMII_CLK_25M	GRF_BIT(3)
696 #define RK3366_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
697 #define RK3366_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
698 #define RK3366_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
699 #define RK3366_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
700 #define RK3366_GMAC_RMII_MODE		GRF_BIT(6)
701 #define RK3366_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
702 
703 /* RK3366_GRF_SOC_CON7 */
704 #define RK3366_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
705 #define RK3366_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
706 #define RK3366_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
707 #define RK3366_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
708 #define RK3366_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
709 #define RK3366_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
710 
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)711 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
712 				int tx_delay, int rx_delay)
713 {
714 	struct device *dev = &bsp_priv->pdev->dev;
715 
716 	if (IS_ERR(bsp_priv->grf)) {
717 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
718 		return;
719 	}
720 
721 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
722 		     RK3366_GMAC_PHY_INTF_SEL_RGMII |
723 		     RK3366_GMAC_RMII_MODE_CLR);
724 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
725 		     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
726 		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
727 		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
728 }
729 
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)730 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
731 {
732 	struct device *dev = &bsp_priv->pdev->dev;
733 
734 	if (IS_ERR(bsp_priv->grf)) {
735 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
736 		return;
737 	}
738 
739 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
740 		     RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
741 }
742 
rk3366_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)743 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
744 {
745 	struct device *dev = &bsp_priv->pdev->dev;
746 
747 	if (IS_ERR(bsp_priv->grf)) {
748 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
749 		return;
750 	}
751 
752 	if (speed == 10)
753 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
754 			     RK3366_GMAC_CLK_2_5M);
755 	else if (speed == 100)
756 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
757 			     RK3366_GMAC_CLK_25M);
758 	else if (speed == 1000)
759 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
760 			     RK3366_GMAC_CLK_125M);
761 	else
762 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
763 }
764 
rk3366_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)765 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
766 {
767 	struct device *dev = &bsp_priv->pdev->dev;
768 
769 	if (IS_ERR(bsp_priv->grf)) {
770 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
771 		return;
772 	}
773 
774 	if (speed == 10) {
775 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
776 			     RK3366_GMAC_RMII_CLK_2_5M |
777 			     RK3366_GMAC_SPEED_10M);
778 	} else if (speed == 100) {
779 		regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
780 			     RK3366_GMAC_RMII_CLK_25M |
781 			     RK3366_GMAC_SPEED_100M);
782 	} else {
783 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
784 	}
785 }
786 
787 static const struct rk_gmac_ops rk3366_ops = {
788 	.set_to_rgmii = rk3366_set_to_rgmii,
789 	.set_to_rmii = rk3366_set_to_rmii,
790 	.set_rgmii_speed = rk3366_set_rgmii_speed,
791 	.set_rmii_speed = rk3366_set_rmii_speed,
792 };
793 
794 #define RK3368_GRF_SOC_CON15	0x043c
795 #define RK3368_GRF_SOC_CON16	0x0440
796 
797 /* RK3368_GRF_SOC_CON15 */
798 #define RK3368_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
799 					 GRF_CLR_BIT(11))
800 #define RK3368_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
801 					 GRF_BIT(11))
802 #define RK3368_GMAC_FLOW_CTRL		GRF_BIT(8)
803 #define RK3368_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
804 #define RK3368_GMAC_SPEED_10M		GRF_CLR_BIT(7)
805 #define RK3368_GMAC_SPEED_100M		GRF_BIT(7)
806 #define RK3368_GMAC_RMII_CLK_25M	GRF_BIT(3)
807 #define RK3368_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
808 #define RK3368_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
809 #define RK3368_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
810 #define RK3368_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
811 #define RK3368_GMAC_RMII_MODE		GRF_BIT(6)
812 #define RK3368_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
813 
814 /* RK3368_GRF_SOC_CON16 */
815 #define RK3368_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
816 #define RK3368_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
817 #define RK3368_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
818 #define RK3368_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
819 #define RK3368_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
820 #define RK3368_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
821 
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)822 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
823 				int tx_delay, int rx_delay)
824 {
825 	struct device *dev = &bsp_priv->pdev->dev;
826 
827 	if (IS_ERR(bsp_priv->grf)) {
828 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
829 		return;
830 	}
831 
832 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
833 		     RK3368_GMAC_PHY_INTF_SEL_RGMII |
834 		     RK3368_GMAC_RMII_MODE_CLR);
835 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
836 		     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
837 		     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
838 		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
839 }
840 
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)841 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
842 {
843 	struct device *dev = &bsp_priv->pdev->dev;
844 
845 	if (IS_ERR(bsp_priv->grf)) {
846 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
847 		return;
848 	}
849 
850 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
851 		     RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
852 }
853 
rk3368_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)854 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
855 {
856 	struct device *dev = &bsp_priv->pdev->dev;
857 
858 	if (IS_ERR(bsp_priv->grf)) {
859 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
860 		return;
861 	}
862 
863 	if (speed == 10)
864 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
865 			     RK3368_GMAC_CLK_2_5M);
866 	else if (speed == 100)
867 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
868 			     RK3368_GMAC_CLK_25M);
869 	else if (speed == 1000)
870 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
871 			     RK3368_GMAC_CLK_125M);
872 	else
873 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
874 }
875 
rk3368_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)876 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
877 {
878 	struct device *dev = &bsp_priv->pdev->dev;
879 
880 	if (IS_ERR(bsp_priv->grf)) {
881 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
882 		return;
883 	}
884 
885 	if (speed == 10) {
886 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
887 			     RK3368_GMAC_RMII_CLK_2_5M |
888 			     RK3368_GMAC_SPEED_10M);
889 	} else if (speed == 100) {
890 		regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
891 			     RK3368_GMAC_RMII_CLK_25M |
892 			     RK3368_GMAC_SPEED_100M);
893 	} else {
894 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
895 	}
896 }
897 
898 static const struct rk_gmac_ops rk3368_ops = {
899 	.set_to_rgmii = rk3368_set_to_rgmii,
900 	.set_to_rmii = rk3368_set_to_rmii,
901 	.set_rgmii_speed = rk3368_set_rgmii_speed,
902 	.set_rmii_speed = rk3368_set_rmii_speed,
903 };
904 
905 #define RK3399_GRF_SOC_CON5	0xc214
906 #define RK3399_GRF_SOC_CON6	0xc218
907 
908 /* RK3399_GRF_SOC_CON5 */
909 #define RK3399_GMAC_PHY_INTF_SEL_RGMII	(GRF_BIT(9) | GRF_CLR_BIT(10) | \
910 					 GRF_CLR_BIT(11))
911 #define RK3399_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
912 					 GRF_BIT(11))
913 #define RK3399_GMAC_FLOW_CTRL		GRF_BIT(8)
914 #define RK3399_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(8)
915 #define RK3399_GMAC_SPEED_10M		GRF_CLR_BIT(7)
916 #define RK3399_GMAC_SPEED_100M		GRF_BIT(7)
917 #define RK3399_GMAC_RMII_CLK_25M	GRF_BIT(3)
918 #define RK3399_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(3)
919 #define RK3399_GMAC_CLK_125M		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
920 #define RK3399_GMAC_CLK_25M		(GRF_BIT(4) | GRF_BIT(5))
921 #define RK3399_GMAC_CLK_2_5M		(GRF_CLR_BIT(4) | GRF_BIT(5))
922 #define RK3399_GMAC_RMII_MODE		GRF_BIT(6)
923 #define RK3399_GMAC_RMII_MODE_CLR	GRF_CLR_BIT(6)
924 
925 /* RK3399_GRF_SOC_CON6 */
926 #define RK3399_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(7)
927 #define RK3399_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(7)
928 #define RK3399_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
929 #define RK3399_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
930 #define RK3399_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
931 #define RK3399_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
932 
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)933 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
934 				int tx_delay, int rx_delay)
935 {
936 	struct device *dev = &bsp_priv->pdev->dev;
937 
938 	if (IS_ERR(bsp_priv->grf)) {
939 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
940 		return;
941 	}
942 
943 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
944 		     RK3399_GMAC_PHY_INTF_SEL_RGMII |
945 		     RK3399_GMAC_RMII_MODE_CLR);
946 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
947 		     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
948 		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
949 		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
950 }
951 
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)952 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
953 {
954 	struct device *dev = &bsp_priv->pdev->dev;
955 
956 	if (IS_ERR(bsp_priv->grf)) {
957 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
958 		return;
959 	}
960 
961 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
962 		     RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
963 }
964 
rk3399_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)965 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
966 {
967 	struct device *dev = &bsp_priv->pdev->dev;
968 
969 	if (IS_ERR(bsp_priv->grf)) {
970 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
971 		return;
972 	}
973 
974 	if (speed == 10)
975 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
976 			     RK3399_GMAC_CLK_2_5M);
977 	else if (speed == 100)
978 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
979 			     RK3399_GMAC_CLK_25M);
980 	else if (speed == 1000)
981 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
982 			     RK3399_GMAC_CLK_125M);
983 	else
984 		dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
985 }
986 
rk3399_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)987 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
988 {
989 	struct device *dev = &bsp_priv->pdev->dev;
990 
991 	if (IS_ERR(bsp_priv->grf)) {
992 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
993 		return;
994 	}
995 
996 	if (speed == 10) {
997 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
998 			     RK3399_GMAC_RMII_CLK_2_5M |
999 			     RK3399_GMAC_SPEED_10M);
1000 	} else if (speed == 100) {
1001 		regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
1002 			     RK3399_GMAC_RMII_CLK_25M |
1003 			     RK3399_GMAC_SPEED_100M);
1004 	} else {
1005 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1006 	}
1007 }
1008 
1009 static const struct rk_gmac_ops rk3399_ops = {
1010 	.set_to_rgmii = rk3399_set_to_rgmii,
1011 	.set_to_rmii = rk3399_set_to_rmii,
1012 	.set_rgmii_speed = rk3399_set_rgmii_speed,
1013 	.set_rmii_speed = rk3399_set_rmii_speed,
1014 };
1015 
1016 #define RK3568_GRF_GMAC0_CON0		0x0380
1017 #define RK3568_GRF_GMAC0_CON1		0x0384
1018 #define RK3568_GRF_GMAC1_CON0		0x0388
1019 #define RK3568_GRF_GMAC1_CON1		0x038c
1020 
1021 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1022 #define RK3568_GMAC_PHY_INTF_SEL_RGMII	\
1023 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1024 #define RK3568_GMAC_PHY_INTF_SEL_RMII	\
1025 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1026 #define RK3568_GMAC_FLOW_CTRL			GRF_BIT(3)
1027 #define RK3568_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(3)
1028 #define RK3568_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1029 #define RK3568_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(1)
1030 #define RK3568_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1031 #define RK3568_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
1032 
1033 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1034 #define RK3568_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1035 #define RK3568_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1036 
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1037 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1038 				int tx_delay, int rx_delay)
1039 {
1040 	struct device *dev = &bsp_priv->pdev->dev;
1041 	u32 con0, con1;
1042 
1043 	if (IS_ERR(bsp_priv->grf)) {
1044 		dev_err(dev, "Missing rockchip,grf property\n");
1045 		return;
1046 	}
1047 
1048 	con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1049 				     RK3568_GRF_GMAC0_CON0;
1050 	con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1051 				     RK3568_GRF_GMAC0_CON1;
1052 
1053 	regmap_write(bsp_priv->grf, con0,
1054 		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1055 		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1056 
1057 	regmap_write(bsp_priv->grf, con1,
1058 		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
1059 		     RK3568_GMAC_RXCLK_DLY_ENABLE |
1060 		     RK3568_GMAC_TXCLK_DLY_ENABLE);
1061 }
1062 
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1063 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1064 {
1065 	struct device *dev = &bsp_priv->pdev->dev;
1066 	u32 con1;
1067 
1068 	if (IS_ERR(bsp_priv->grf)) {
1069 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1070 		return;
1071 	}
1072 
1073 	con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1074 				     RK3568_GRF_GMAC0_CON1;
1075 	regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1076 }
1077 
rk3568_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1078 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1079 {
1080 	struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1081 	struct device *dev = &bsp_priv->pdev->dev;
1082 	unsigned long rate;
1083 	int ret;
1084 
1085 	switch (speed) {
1086 	case 10:
1087 		rate = 2500000;
1088 		break;
1089 	case 100:
1090 		rate = 25000000;
1091 		break;
1092 	case 1000:
1093 		rate = 125000000;
1094 		break;
1095 	default:
1096 		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1097 		return;
1098 	}
1099 
1100 	ret = clk_set_rate(clk_mac_speed, rate);
1101 	if (ret)
1102 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1103 			__func__, rate, ret);
1104 }
1105 
1106 static const struct rk_gmac_ops rk3568_ops = {
1107 	.set_to_rgmii = rk3568_set_to_rgmii,
1108 	.set_to_rmii = rk3568_set_to_rmii,
1109 	.set_rgmii_speed = rk3568_set_gmac_speed,
1110 	.set_rmii_speed = rk3568_set_gmac_speed,
1111 	.regs_valid = true,
1112 	.regs = {
1113 		0xfe2a0000, /* gmac0 */
1114 		0xfe010000, /* gmac1 */
1115 		0x0, /* sentinel */
1116 	},
1117 };
1118 
1119 /* VCCIO0_1_3_IOC */
1120 #define RK3576_VCCIO0_1_3_IOC_CON2		0X6408
1121 #define RK3576_VCCIO0_1_3_IOC_CON3		0X640c
1122 #define RK3576_VCCIO0_1_3_IOC_CON4		0X6410
1123 #define RK3576_VCCIO0_1_3_IOC_CON5		0X6414
1124 
1125 #define RK3576_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(15)
1126 #define RK3576_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(15)
1127 #define RK3576_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(7)
1128 #define RK3576_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(7)
1129 
1130 #define RK3576_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0x7F, 8)
1131 #define RK3576_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0x7F, 0)
1132 
1133 /* SDGMAC_GRF */
1134 #define RK3576_GRF_GMAC_CON0			0X0020
1135 #define RK3576_GRF_GMAC_CON1			0X0024
1136 
1137 #define RK3576_GMAC_RMII_MODE			GRF_BIT(3)
1138 #define RK3576_GMAC_RGMII_MODE			GRF_CLR_BIT(3)
1139 
1140 #define RK3576_GMAC_CLK_SELECT_IO		GRF_BIT(7)
1141 #define RK3576_GMAC_CLK_SELECT_CRU		GRF_CLR_BIT(7)
1142 
1143 #define RK3576_GMAC_CLK_RMII_DIV2		GRF_BIT(5)
1144 #define RK3576_GMAC_CLK_RMII_DIV20		GRF_CLR_BIT(5)
1145 
1146 #define RK3576_GMAC_CLK_RGMII_DIV1		\
1147 			(GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
1148 #define RK3576_GMAC_CLK_RGMII_DIV5		\
1149 			(GRF_BIT(6) | GRF_BIT(5))
1150 #define RK3576_GMAC_CLK_RGMII_DIV50		\
1151 			(GRF_BIT(6) | GRF_CLR_BIT(5))
1152 
1153 #define RK3576_GMAC_CLK_RMII_GATE		GRF_BIT(4)
1154 #define RK3576_GMAC_CLK_RMII_NOGATE		GRF_CLR_BIT(4)
1155 
rk3576_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1156 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
1157 				int tx_delay, int rx_delay)
1158 {
1159 	struct device *dev = &bsp_priv->pdev->dev;
1160 	unsigned int offset_con;
1161 
1162 	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1163 		dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n");
1164 		return;
1165 	}
1166 
1167 	offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1168 					 RK3576_GRF_GMAC_CON0;
1169 
1170 	regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
1171 
1172 	offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
1173 					 RK3576_VCCIO0_1_3_IOC_CON2;
1174 
1175 	/* m0 && m1 delay enabled */
1176 	regmap_write(bsp_priv->php_grf, offset_con,
1177 		     DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1178 	regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1179 		     DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1180 
1181 	/* m0 && m1 delay value */
1182 	regmap_write(bsp_priv->php_grf, offset_con,
1183 		     RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1184 		     RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1185 	regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1186 		     RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1187 		     RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1188 }
1189 
rk3576_set_to_rmii(struct rk_priv_data * bsp_priv)1190 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
1191 {
1192 	struct device *dev = &bsp_priv->pdev->dev;
1193 	unsigned int offset_con;
1194 
1195 	if (IS_ERR(bsp_priv->grf)) {
1196 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1197 		return;
1198 	}
1199 
1200 	offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1201 					 RK3576_GRF_GMAC_CON0;
1202 
1203 	regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
1204 }
1205 
rk3576_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1206 static void rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1207 {
1208 	struct device *dev = &bsp_priv->pdev->dev;
1209 	unsigned int val = 0, offset_con;
1210 
1211 	switch (speed) {
1212 	case 10:
1213 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1214 			val = RK3576_GMAC_CLK_RMII_DIV20;
1215 		else
1216 			val = RK3576_GMAC_CLK_RGMII_DIV50;
1217 		break;
1218 	case 100:
1219 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1220 			val = RK3576_GMAC_CLK_RMII_DIV2;
1221 		else
1222 			val = RK3576_GMAC_CLK_RGMII_DIV5;
1223 		break;
1224 	case 1000:
1225 		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1226 			val = RK3576_GMAC_CLK_RGMII_DIV1;
1227 		else
1228 			goto err;
1229 		break;
1230 	default:
1231 		goto err;
1232 	}
1233 
1234 	offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1235 					 RK3576_GRF_GMAC_CON0;
1236 
1237 	regmap_write(bsp_priv->grf, offset_con, val);
1238 
1239 	return;
1240 err:
1241 	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1242 }
1243 
rk3576_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1244 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1245 				       bool enable)
1246 {
1247 	unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
1248 				   RK3576_GMAC_CLK_SELECT_CRU;
1249 	unsigned int offset_con;
1250 
1251 	val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
1252 			RK3576_GMAC_CLK_RMII_GATE;
1253 
1254 	offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1255 					 RK3576_GRF_GMAC_CON0;
1256 
1257 	regmap_write(bsp_priv->grf, offset_con, val);
1258 }
1259 
1260 static const struct rk_gmac_ops rk3576_ops = {
1261 	.set_to_rgmii = rk3576_set_to_rgmii,
1262 	.set_to_rmii = rk3576_set_to_rmii,
1263 	.set_rgmii_speed = rk3576_set_gmac_speed,
1264 	.set_rmii_speed = rk3576_set_gmac_speed,
1265 	.set_clock_selection = rk3576_set_clock_selection,
1266 	.regs_valid = true,
1267 	.regs = {
1268 		0x2a220000, /* gmac0 */
1269 		0x2a230000, /* gmac1 */
1270 		0x0, /* sentinel */
1271 	},
1272 };
1273 
1274 /* sys_grf */
1275 #define RK3588_GRF_GMAC_CON7			0X031c
1276 #define RK3588_GRF_GMAC_CON8			0X0320
1277 #define RK3588_GRF_GMAC_CON9			0X0324
1278 
1279 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 3)
1280 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 3)
1281 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id)	GRF_BIT(2 * (id) + 2)
1282 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id)	GRF_CLR_BIT(2 * (id) + 2)
1283 
1284 #define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
1285 #define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
1286 
1287 /* php_grf */
1288 #define RK3588_GRF_GMAC_CON0			0X0008
1289 #define RK3588_GRF_CLK_CON1			0X0070
1290 
1291 #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id)	\
1292 	(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
1293 #define RK3588_GMAC_PHY_INTF_SEL_RMII(id)	\
1294 	(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
1295 
1296 #define RK3588_GMAC_CLK_RMII_MODE(id)		GRF_BIT(5 * (id))
1297 #define RK3588_GMAC_CLK_RGMII_MODE(id)		GRF_CLR_BIT(5 * (id))
1298 
1299 #define RK3588_GMAC_CLK_SELECT_CRU(id)		GRF_BIT(5 * (id) + 4)
1300 #define RK3588_GMAC_CLK_SELECT_IO(id)		GRF_CLR_BIT(5 * (id) + 4)
1301 
1302 #define RK3588_GMA_CLK_RMII_DIV2(id)		GRF_BIT(5 * (id) + 2)
1303 #define RK3588_GMA_CLK_RMII_DIV20(id)		GRF_CLR_BIT(5 * (id) + 2)
1304 
1305 #define RK3588_GMAC_CLK_RGMII_DIV1(id)		\
1306 			(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
1307 #define RK3588_GMAC_CLK_RGMII_DIV5(id)		\
1308 			(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1309 #define RK3588_GMAC_CLK_RGMII_DIV50(id)		\
1310 			(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
1311 
1312 #define RK3588_GMAC_CLK_RMII_GATE(id)		GRF_BIT(5 * (id) + 1)
1313 #define RK3588_GMAC_CLK_RMII_NOGATE(id)		GRF_CLR_BIT(5 * (id) + 1)
1314 
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1315 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1316 				int tx_delay, int rx_delay)
1317 {
1318 	struct device *dev = &bsp_priv->pdev->dev;
1319 	u32 offset_con, id = bsp_priv->id;
1320 
1321 	if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
1322 		dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
1323 		return;
1324 	}
1325 
1326 	offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1327 					 RK3588_GRF_GMAC_CON8;
1328 
1329 	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1330 		     RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
1331 
1332 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1333 		     RK3588_GMAC_CLK_RGMII_MODE(id));
1334 
1335 	regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1336 		     RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1337 		     RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1338 
1339 	regmap_write(bsp_priv->grf, offset_con,
1340 		     RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1341 		     RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1342 }
1343 
rk3588_set_to_rmii(struct rk_priv_data * bsp_priv)1344 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1345 {
1346 	struct device *dev = &bsp_priv->pdev->dev;
1347 
1348 	if (IS_ERR(bsp_priv->php_grf)) {
1349 		dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
1350 		return;
1351 	}
1352 
1353 	regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1354 		     RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
1355 
1356 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1357 		     RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1358 }
1359 
rk3588_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1360 static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1361 {
1362 	struct device *dev = &bsp_priv->pdev->dev;
1363 	unsigned int val = 0, id = bsp_priv->id;
1364 
1365 	switch (speed) {
1366 	case 10:
1367 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1368 			val = RK3588_GMA_CLK_RMII_DIV20(id);
1369 		else
1370 			val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1371 		break;
1372 	case 100:
1373 		if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1374 			val = RK3588_GMA_CLK_RMII_DIV2(id);
1375 		else
1376 			val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1377 		break;
1378 	case 1000:
1379 		if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII)
1380 			val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1381 		else
1382 			goto err;
1383 		break;
1384 	default:
1385 		goto err;
1386 	}
1387 
1388 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1389 
1390 	return;
1391 err:
1392 	dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1393 }
1394 
rk3588_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1395 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1396 				       bool enable)
1397 {
1398 	unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) :
1399 				   RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id);
1400 
1401 	val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
1402 			RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
1403 
1404 	regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1405 }
1406 
1407 static const struct rk_gmac_ops rk3588_ops = {
1408 	.set_to_rgmii = rk3588_set_to_rgmii,
1409 	.set_to_rmii = rk3588_set_to_rmii,
1410 	.set_rgmii_speed = rk3588_set_gmac_speed,
1411 	.set_rmii_speed = rk3588_set_gmac_speed,
1412 	.set_clock_selection = rk3588_set_clock_selection,
1413 	.regs_valid = true,
1414 	.regs = {
1415 		0xfe1b0000, /* gmac0 */
1416 		0xfe1c0000, /* gmac1 */
1417 		0x0, /* sentinel */
1418 	},
1419 };
1420 
1421 #define RV1108_GRF_GMAC_CON0		0X0900
1422 
1423 /* RV1108_GRF_GMAC_CON0 */
1424 #define RV1108_GMAC_PHY_INTF_SEL_RMII	(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1425 					GRF_BIT(6))
1426 #define RV1108_GMAC_FLOW_CTRL		GRF_BIT(3)
1427 #define RV1108_GMAC_FLOW_CTRL_CLR	GRF_CLR_BIT(3)
1428 #define RV1108_GMAC_SPEED_10M		GRF_CLR_BIT(2)
1429 #define RV1108_GMAC_SPEED_100M		GRF_BIT(2)
1430 #define RV1108_GMAC_RMII_CLK_25M	GRF_BIT(7)
1431 #define RV1108_GMAC_RMII_CLK_2_5M	GRF_CLR_BIT(7)
1432 
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)1433 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1434 {
1435 	struct device *dev = &bsp_priv->pdev->dev;
1436 
1437 	if (IS_ERR(bsp_priv->grf)) {
1438 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1439 		return;
1440 	}
1441 
1442 	regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1443 		     RV1108_GMAC_PHY_INTF_SEL_RMII);
1444 }
1445 
rv1108_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1446 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1447 {
1448 	struct device *dev = &bsp_priv->pdev->dev;
1449 
1450 	if (IS_ERR(bsp_priv->grf)) {
1451 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1452 		return;
1453 	}
1454 
1455 	if (speed == 10) {
1456 		regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1457 			     RV1108_GMAC_RMII_CLK_2_5M |
1458 			     RV1108_GMAC_SPEED_10M);
1459 	} else if (speed == 100) {
1460 		regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1461 			     RV1108_GMAC_RMII_CLK_25M |
1462 			     RV1108_GMAC_SPEED_100M);
1463 	} else {
1464 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1465 	}
1466 }
1467 
1468 static const struct rk_gmac_ops rv1108_ops = {
1469 	.set_to_rmii = rv1108_set_to_rmii,
1470 	.set_rmii_speed = rv1108_set_rmii_speed,
1471 };
1472 
1473 #define RV1126_GRF_GMAC_CON0		0X0070
1474 #define RV1126_GRF_GMAC_CON1		0X0074
1475 #define RV1126_GRF_GMAC_CON2		0X0078
1476 
1477 /* RV1126_GRF_GMAC_CON0 */
1478 #define RV1126_GMAC_PHY_INTF_SEL_RGMII	\
1479 		(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1480 #define RV1126_GMAC_PHY_INTF_SEL_RMII	\
1481 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1482 #define RV1126_GMAC_FLOW_CTRL			GRF_BIT(7)
1483 #define RV1126_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(7)
1484 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE		GRF_BIT(1)
1485 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1486 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE		GRF_BIT(0)
1487 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1488 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE		GRF_BIT(3)
1489 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1490 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE		GRF_BIT(2)
1491 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
1492 
1493 /* RV1126_GRF_GMAC_CON1 */
1494 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1495 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1496 /* RV1126_GRF_GMAC_CON2 */
1497 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1498 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1499 
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1500 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1501 				int tx_delay, int rx_delay)
1502 {
1503 	struct device *dev = &bsp_priv->pdev->dev;
1504 
1505 	if (IS_ERR(bsp_priv->grf)) {
1506 		dev_err(dev, "Missing rockchip,grf property\n");
1507 		return;
1508 	}
1509 
1510 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1511 		     RV1126_GMAC_PHY_INTF_SEL_RGMII |
1512 		     RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1513 		     RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1514 		     RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1515 		     RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1516 
1517 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1518 		     RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1519 		     RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1520 
1521 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1522 		     RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1523 		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1524 }
1525 
rv1126_set_to_rmii(struct rk_priv_data * bsp_priv)1526 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1527 {
1528 	struct device *dev = &bsp_priv->pdev->dev;
1529 
1530 	if (IS_ERR(bsp_priv->grf)) {
1531 		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1532 		return;
1533 	}
1534 
1535 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1536 		     RV1126_GMAC_PHY_INTF_SEL_RMII);
1537 }
1538 
rv1126_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)1539 static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1540 {
1541 	struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1542 	struct device *dev = &bsp_priv->pdev->dev;
1543 	unsigned long rate;
1544 	int ret;
1545 
1546 	switch (speed) {
1547 	case 10:
1548 		rate = 2500000;
1549 		break;
1550 	case 100:
1551 		rate = 25000000;
1552 		break;
1553 	case 1000:
1554 		rate = 125000000;
1555 		break;
1556 	default:
1557 		dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1558 		return;
1559 	}
1560 
1561 	ret = clk_set_rate(clk_mac_speed, rate);
1562 	if (ret)
1563 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1564 			__func__, rate, ret);
1565 }
1566 
rv1126_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1567 static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1568 {
1569 	struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
1570 	struct device *dev = &bsp_priv->pdev->dev;
1571 	unsigned long rate;
1572 	int ret;
1573 
1574 	switch (speed) {
1575 	case 10:
1576 		rate = 2500000;
1577 		break;
1578 	case 100:
1579 		rate = 25000000;
1580 		break;
1581 	default:
1582 		dev_err(dev, "unknown speed value for RGMII speed=%d", speed);
1583 		return;
1584 	}
1585 
1586 	ret = clk_set_rate(clk_mac_speed, rate);
1587 	if (ret)
1588 		dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1589 			__func__, rate, ret);
1590 }
1591 
1592 static const struct rk_gmac_ops rv1126_ops = {
1593 	.set_to_rgmii = rv1126_set_to_rgmii,
1594 	.set_to_rmii = rv1126_set_to_rmii,
1595 	.set_rgmii_speed = rv1126_set_rgmii_speed,
1596 	.set_rmii_speed = rv1126_set_rmii_speed,
1597 };
1598 
1599 #define RK_GRF_MACPHY_CON0		0xb00
1600 #define RK_GRF_MACPHY_CON1		0xb04
1601 #define RK_GRF_MACPHY_CON2		0xb08
1602 #define RK_GRF_MACPHY_CON3		0xb0c
1603 
1604 #define RK_MACPHY_ENABLE		GRF_BIT(0)
1605 #define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
1606 #define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
1607 #define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
1608 #define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
1609 #define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
1610 
rk_gmac_integrated_phy_powerup(struct rk_priv_data * priv)1611 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1612 {
1613 	if (priv->ops->integrated_phy_powerup)
1614 		priv->ops->integrated_phy_powerup(priv);
1615 
1616 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1617 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1618 
1619 	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1620 	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1621 
1622 	if (priv->phy_reset) {
1623 		/* PHY needs to be disabled before trying to reset it */
1624 		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1625 		if (priv->phy_reset)
1626 			reset_control_assert(priv->phy_reset);
1627 		usleep_range(10, 20);
1628 		if (priv->phy_reset)
1629 			reset_control_deassert(priv->phy_reset);
1630 		usleep_range(10, 20);
1631 		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1632 		msleep(30);
1633 	}
1634 }
1635 
rk_gmac_integrated_phy_powerdown(struct rk_priv_data * priv)1636 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1637 {
1638 	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1639 	if (priv->phy_reset)
1640 		reset_control_assert(priv->phy_reset);
1641 }
1642 
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1643 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1644 {
1645 	struct rk_priv_data *bsp_priv = plat->bsp_priv;
1646 	struct device *dev = &bsp_priv->pdev->dev;
1647 	int phy_iface = bsp_priv->phy_iface;
1648 	int i, j, ret;
1649 
1650 	bsp_priv->clk_enabled = false;
1651 
1652 	bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
1653 	if (phy_iface == PHY_INTERFACE_MODE_RMII)
1654 		bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
1655 
1656 	bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
1657 				      sizeof(*bsp_priv->clks), GFP_KERNEL);
1658 	if (!bsp_priv->clks)
1659 		return -ENOMEM;
1660 
1661 	for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
1662 		bsp_priv->clks[i].id = rk_clocks[i];
1663 
1664 	if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1665 		for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
1666 			bsp_priv->clks[i++].id = rk_rmii_clocks[j];
1667 	}
1668 
1669 	ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
1670 					 bsp_priv->clks);
1671 	if (ret)
1672 		return dev_err_probe(dev, ret, "Failed to get clocks\n");
1673 
1674 	/* "stmmaceth" will be enabled by the core */
1675 	bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1676 	ret = PTR_ERR_OR_ZERO(bsp_priv->clk_mac);
1677 	if (ret)
1678 		return dev_err_probe(dev, ret, "Cannot get stmmaceth clock\n");
1679 
1680 	if (bsp_priv->clock_input) {
1681 		dev_info(dev, "clock input from PHY\n");
1682 	} else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1683 		clk_set_rate(bsp_priv->clk_mac, 50000000);
1684 	}
1685 
1686 	if (plat->phy_node && bsp_priv->integrated_phy) {
1687 		bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1688 		ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
1689 		if (ret)
1690 			return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
1691 		clk_set_rate(bsp_priv->clk_phy, 50000000);
1692 	}
1693 
1694 	return 0;
1695 }
1696 
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1697 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1698 {
1699 	int ret;
1700 
1701 	if (enable) {
1702 		if (!bsp_priv->clk_enabled) {
1703 			ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
1704 						      bsp_priv->clks);
1705 			if (ret)
1706 				return ret;
1707 
1708 			ret = clk_prepare_enable(bsp_priv->clk_phy);
1709 			if (ret)
1710 				return ret;
1711 
1712 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1713 				bsp_priv->ops->set_clock_selection(bsp_priv,
1714 					       bsp_priv->clock_input, true);
1715 
1716 			mdelay(5);
1717 			bsp_priv->clk_enabled = true;
1718 		}
1719 	} else {
1720 		if (bsp_priv->clk_enabled) {
1721 			clk_bulk_disable_unprepare(bsp_priv->num_clks,
1722 						   bsp_priv->clks);
1723 			clk_disable_unprepare(bsp_priv->clk_phy);
1724 
1725 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1726 				bsp_priv->ops->set_clock_selection(bsp_priv,
1727 					      bsp_priv->clock_input, false);
1728 
1729 			bsp_priv->clk_enabled = false;
1730 		}
1731 	}
1732 
1733 	return 0;
1734 }
1735 
phy_power_on(struct rk_priv_data * bsp_priv,bool enable)1736 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1737 {
1738 	struct regulator *ldo = bsp_priv->regulator;
1739 	int ret;
1740 	struct device *dev = &bsp_priv->pdev->dev;
1741 
1742 	if (enable) {
1743 		ret = regulator_enable(ldo);
1744 		if (ret)
1745 			dev_err(dev, "fail to enable phy-supply\n");
1746 	} else {
1747 		ret = regulator_disable(ldo);
1748 		if (ret)
1749 			dev_err(dev, "fail to disable phy-supply\n");
1750 	}
1751 
1752 	return 0;
1753 }
1754 
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1755 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1756 					  struct plat_stmmacenet_data *plat,
1757 					  const struct rk_gmac_ops *ops)
1758 {
1759 	struct rk_priv_data *bsp_priv;
1760 	struct device *dev = &pdev->dev;
1761 	struct resource *res;
1762 	int ret;
1763 	const char *strings = NULL;
1764 	int value;
1765 
1766 	bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1767 	if (!bsp_priv)
1768 		return ERR_PTR(-ENOMEM);
1769 
1770 	of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1771 	bsp_priv->ops = ops;
1772 
1773 	/* Some SoCs have multiple MAC controllers, which need
1774 	 * to be distinguished.
1775 	 */
1776 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1777 	if (res && ops->regs_valid) {
1778 		int i = 0;
1779 
1780 		while (ops->regs[i]) {
1781 			if (ops->regs[i] == res->start) {
1782 				bsp_priv->id = i;
1783 				break;
1784 			}
1785 			i++;
1786 		}
1787 	}
1788 
1789 	bsp_priv->regulator = devm_regulator_get(dev, "phy");
1790 	if (IS_ERR(bsp_priv->regulator)) {
1791 		ret = PTR_ERR(bsp_priv->regulator);
1792 		dev_err_probe(dev, ret, "failed to get phy regulator\n");
1793 		return ERR_PTR(ret);
1794 	}
1795 
1796 	ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1797 	if (ret) {
1798 		dev_err(dev, "Can not read property: clock_in_out.\n");
1799 		bsp_priv->clock_input = true;
1800 	} else {
1801 		dev_info(dev, "clock input or output? (%s).\n",
1802 			 strings);
1803 		if (!strcmp(strings, "input"))
1804 			bsp_priv->clock_input = true;
1805 		else
1806 			bsp_priv->clock_input = false;
1807 	}
1808 
1809 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1810 	if (ret) {
1811 		bsp_priv->tx_delay = 0x30;
1812 		dev_err(dev, "Can not read property: tx_delay.");
1813 		dev_err(dev, "set tx_delay to 0x%x\n",
1814 			bsp_priv->tx_delay);
1815 	} else {
1816 		dev_info(dev, "TX delay(0x%x).\n", value);
1817 		bsp_priv->tx_delay = value;
1818 	}
1819 
1820 	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1821 	if (ret) {
1822 		bsp_priv->rx_delay = 0x10;
1823 		dev_err(dev, "Can not read property: rx_delay.");
1824 		dev_err(dev, "set rx_delay to 0x%x\n",
1825 			bsp_priv->rx_delay);
1826 	} else {
1827 		dev_info(dev, "RX delay(0x%x).\n", value);
1828 		bsp_priv->rx_delay = value;
1829 	}
1830 
1831 	bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1832 							"rockchip,grf");
1833 	bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1834 							    "rockchip,php-grf");
1835 
1836 	if (plat->phy_node) {
1837 		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1838 								 "phy-is-integrated");
1839 		if (bsp_priv->integrated_phy) {
1840 			bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1841 			if (IS_ERR(bsp_priv->phy_reset)) {
1842 				dev_err(&pdev->dev, "No PHY reset control found.\n");
1843 				bsp_priv->phy_reset = NULL;
1844 			}
1845 		}
1846 	}
1847 	dev_info(dev, "integrated PHY? (%s).\n",
1848 		 bsp_priv->integrated_phy ? "yes" : "no");
1849 
1850 	bsp_priv->pdev = pdev;
1851 
1852 	return bsp_priv;
1853 }
1854 
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1855 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1856 {
1857 	switch (bsp_priv->phy_iface) {
1858 	case PHY_INTERFACE_MODE_RGMII:
1859 	case PHY_INTERFACE_MODE_RGMII_ID:
1860 	case PHY_INTERFACE_MODE_RGMII_RXID:
1861 	case PHY_INTERFACE_MODE_RGMII_TXID:
1862 		if (!bsp_priv->ops->set_to_rgmii)
1863 			return -EINVAL;
1864 		break;
1865 	case PHY_INTERFACE_MODE_RMII:
1866 		if (!bsp_priv->ops->set_to_rmii)
1867 			return -EINVAL;
1868 		break;
1869 	default:
1870 		dev_err(&bsp_priv->pdev->dev,
1871 			"unsupported interface %d", bsp_priv->phy_iface);
1872 	}
1873 	return 0;
1874 }
1875 
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1876 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1877 {
1878 	int ret;
1879 	struct device *dev = &bsp_priv->pdev->dev;
1880 
1881 	ret = rk_gmac_check_ops(bsp_priv);
1882 	if (ret)
1883 		return ret;
1884 
1885 	ret = gmac_clk_enable(bsp_priv, true);
1886 	if (ret)
1887 		return ret;
1888 
1889 	/*rmii or rgmii*/
1890 	switch (bsp_priv->phy_iface) {
1891 	case PHY_INTERFACE_MODE_RGMII:
1892 		dev_info(dev, "init for RGMII\n");
1893 		bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1894 					    bsp_priv->rx_delay);
1895 		break;
1896 	case PHY_INTERFACE_MODE_RGMII_ID:
1897 		dev_info(dev, "init for RGMII_ID\n");
1898 		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1899 		break;
1900 	case PHY_INTERFACE_MODE_RGMII_RXID:
1901 		dev_info(dev, "init for RGMII_RXID\n");
1902 		bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1903 		break;
1904 	case PHY_INTERFACE_MODE_RGMII_TXID:
1905 		dev_info(dev, "init for RGMII_TXID\n");
1906 		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1907 		break;
1908 	case PHY_INTERFACE_MODE_RMII:
1909 		dev_info(dev, "init for RMII\n");
1910 		bsp_priv->ops->set_to_rmii(bsp_priv);
1911 		break;
1912 	default:
1913 		dev_err(dev, "NO interface defined!\n");
1914 	}
1915 
1916 	ret = phy_power_on(bsp_priv, true);
1917 	if (ret) {
1918 		gmac_clk_enable(bsp_priv, false);
1919 		return ret;
1920 	}
1921 
1922 	pm_runtime_get_sync(dev);
1923 
1924 	if (bsp_priv->integrated_phy)
1925 		rk_gmac_integrated_phy_powerup(bsp_priv);
1926 
1927 	return 0;
1928 }
1929 
rk_gmac_powerdown(struct rk_priv_data * gmac)1930 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1931 {
1932 	if (gmac->integrated_phy)
1933 		rk_gmac_integrated_phy_powerdown(gmac);
1934 
1935 	pm_runtime_put_sync(&gmac->pdev->dev);
1936 
1937 	phy_power_on(gmac, false);
1938 	gmac_clk_enable(gmac, false);
1939 }
1940 
rk_fix_speed(void * priv,unsigned int speed,unsigned int mode)1941 static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode)
1942 {
1943 	struct rk_priv_data *bsp_priv = priv;
1944 	struct device *dev = &bsp_priv->pdev->dev;
1945 
1946 	switch (bsp_priv->phy_iface) {
1947 	case PHY_INTERFACE_MODE_RGMII:
1948 	case PHY_INTERFACE_MODE_RGMII_ID:
1949 	case PHY_INTERFACE_MODE_RGMII_RXID:
1950 	case PHY_INTERFACE_MODE_RGMII_TXID:
1951 		if (bsp_priv->ops->set_rgmii_speed)
1952 			bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1953 		break;
1954 	case PHY_INTERFACE_MODE_RMII:
1955 		if (bsp_priv->ops->set_rmii_speed)
1956 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1957 		break;
1958 	default:
1959 		dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1960 	}
1961 }
1962 
rk_gmac_probe(struct platform_device * pdev)1963 static int rk_gmac_probe(struct platform_device *pdev)
1964 {
1965 	struct plat_stmmacenet_data *plat_dat;
1966 	struct stmmac_resources stmmac_res;
1967 	const struct rk_gmac_ops *data;
1968 	int ret;
1969 
1970 	data = of_device_get_match_data(&pdev->dev);
1971 	if (!data) {
1972 		dev_err(&pdev->dev, "no of match data provided\n");
1973 		return -EINVAL;
1974 	}
1975 
1976 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1977 	if (ret)
1978 		return ret;
1979 
1980 	plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1981 	if (IS_ERR(plat_dat))
1982 		return PTR_ERR(plat_dat);
1983 
1984 	/* If the stmmac is not already selected as gmac4,
1985 	 * then make sure we fallback to gmac.
1986 	 */
1987 	if (!plat_dat->has_gmac4)
1988 		plat_dat->has_gmac = true;
1989 	plat_dat->fix_mac_speed = rk_fix_speed;
1990 
1991 	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1992 	if (IS_ERR(plat_dat->bsp_priv))
1993 		return PTR_ERR(plat_dat->bsp_priv);
1994 
1995 	ret = rk_gmac_clk_init(plat_dat);
1996 	if (ret)
1997 		return ret;
1998 
1999 	ret = rk_gmac_powerup(plat_dat->bsp_priv);
2000 	if (ret)
2001 		return ret;
2002 
2003 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
2004 	if (ret)
2005 		goto err_gmac_powerdown;
2006 
2007 	return 0;
2008 
2009 err_gmac_powerdown:
2010 	rk_gmac_powerdown(plat_dat->bsp_priv);
2011 
2012 	return ret;
2013 }
2014 
rk_gmac_remove(struct platform_device * pdev)2015 static void rk_gmac_remove(struct platform_device *pdev)
2016 {
2017 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
2018 
2019 	stmmac_dvr_remove(&pdev->dev);
2020 
2021 	rk_gmac_powerdown(bsp_priv);
2022 }
2023 
2024 #ifdef CONFIG_PM_SLEEP
rk_gmac_suspend(struct device * dev)2025 static int rk_gmac_suspend(struct device *dev)
2026 {
2027 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2028 	int ret = stmmac_suspend(dev);
2029 
2030 	/* Keep the PHY up if we use Wake-on-Lan. */
2031 	if (!device_may_wakeup(dev)) {
2032 		rk_gmac_powerdown(bsp_priv);
2033 		bsp_priv->suspended = true;
2034 	}
2035 
2036 	return ret;
2037 }
2038 
rk_gmac_resume(struct device * dev)2039 static int rk_gmac_resume(struct device *dev)
2040 {
2041 	struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
2042 
2043 	/* The PHY was up for Wake-on-Lan. */
2044 	if (bsp_priv->suspended) {
2045 		rk_gmac_powerup(bsp_priv);
2046 		bsp_priv->suspended = false;
2047 	}
2048 
2049 	return stmmac_resume(dev);
2050 }
2051 #endif /* CONFIG_PM_SLEEP */
2052 
2053 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
2054 
2055 static const struct of_device_id rk_gmac_dwmac_match[] = {
2056 	{ .compatible = "rockchip,px30-gmac",	.data = &px30_ops   },
2057 	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2058 	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2059 	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2060 	{ .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
2061 	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2062 	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2063 	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2064 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2065 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2066 	{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
2067 	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
2068 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2069 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2070 	{ }
2071 };
2072 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
2073 
2074 static struct platform_driver rk_gmac_dwmac_driver = {
2075 	.probe  = rk_gmac_probe,
2076 	.remove = rk_gmac_remove,
2077 	.driver = {
2078 		.name           = "rk_gmac-dwmac",
2079 		.pm		= &rk_gmac_pm_ops,
2080 		.of_match_table = rk_gmac_dwmac_match,
2081 	},
2082 };
2083 module_platform_driver(rk_gmac_dwmac_driver);
2084 
2085 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
2086 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
2087 MODULE_LICENSE("GPL");
2088