1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW_TX_H_
6 #define __RTW_TX_H_
7
8 #define RTK_TX_MAX_AGG_NUM_MASK 0x1f
9
10 #define RTW_TX_PROBE_TIMEOUT msecs_to_jiffies(500)
11
12 struct rtw_tx_desc {
13 __le32 w0;
14 __le32 w1;
15 __le32 w2;
16 __le32 w3;
17 __le32 w4;
18 __le32 w5;
19 __le32 w6;
20 __le32 w7;
21 __le32 w8;
22 __le32 w9;
23 } __packed;
24
25 #define RTW_TX_DESC_W0_TXPKTSIZE GENMASK(15, 0)
26 #define RTW_TX_DESC_W0_OFFSET GENMASK(23, 16)
27 #define RTW_TX_DESC_W0_BMC BIT(24)
28 #define RTW_TX_DESC_W0_LS BIT(26)
29 #define RTW_TX_DESC_W0_DISQSELSEQ BIT(31)
30 #define RTW_TX_DESC_W1_MACID GENMASK(7, 0)
31 #define RTW_TX_DESC_W1_QSEL GENMASK(12, 8)
32 #define RTW_TX_DESC_W1_RATE_ID GENMASK(20, 16)
33 #define RTW_TX_DESC_W1_SEC_TYPE GENMASK(23, 22)
34 #define RTW_TX_DESC_W1_PKT_OFFSET GENMASK(28, 24)
35 #define RTW_TX_DESC_W1_MORE_DATA BIT(29)
36 #define RTW_TX_DESC_W2_AGG_EN BIT(12)
37 #define RTW_TX_DESC_W2_SPE_RPT BIT(19)
38 #define RTW_TX_DESC_W2_AMPDU_DEN GENMASK(22, 20)
39 #define RTW_TX_DESC_W2_BT_NULL BIT(23)
40 #define RTW_TX_DESC_W3_HW_SSN_SEL GENMASK(7, 6)
41 #define RTW_TX_DESC_W3_USE_RATE BIT(8)
42 #define RTW_TX_DESC_W3_DISDATAFB BIT(10)
43 #define RTW_TX_DESC_W3_USE_RTS BIT(12)
44 #define RTW_TX_DESC_W3_NAVUSEHDR BIT(15)
45 #define RTW_TX_DESC_W3_MAX_AGG_NUM GENMASK(21, 17)
46 #define RTW_TX_DESC_W4_DATARATE GENMASK(6, 0)
47 #define RTW_TX_DESC_W4_DATARATE_FB_LIMIT GENMASK(12, 8)
48 #define RTW_TX_DESC_W4_RTSRATE GENMASK(28, 24)
49 #define RTW_TX_DESC_W5_DATA_SHORT BIT(4)
50 #define RTW_TX_DESC_W5_DATA_BW GENMASK(6, 5)
51 #define RTW_TX_DESC_W5_DATA_LDPC BIT(7)
52 #define RTW_TX_DESC_W5_DATA_STBC GENMASK(9, 8)
53 #define RTW_TX_DESC_W5_DATA_RTS_SHORT BIT(12)
54 #define RTW_TX_DESC_W6_SW_DEFINE GENMASK(11, 0)
55 #define RTW_TX_DESC_W7_TXDESC_CHECKSUM GENMASK(15, 0)
56 #define RTW_TX_DESC_W7_DMA_TXAGG_NUM GENMASK(31, 24)
57 #define RTW_TX_DESC_W8_EN_HWSEQ BIT(15)
58 #define RTW_TX_DESC_W9_SW_SEQ GENMASK(23, 12)
59 #define RTW_TX_DESC_W9_TIM_EN BIT(7)
60 #define RTW_TX_DESC_W9_TIM_OFFSET GENMASK(6, 0)
61
62 enum rtw_tx_desc_queue_select {
63 TX_DESC_QSEL_TID0 = 0,
64 TX_DESC_QSEL_TID1 = 1,
65 TX_DESC_QSEL_TID2 = 2,
66 TX_DESC_QSEL_TID3 = 3,
67 TX_DESC_QSEL_TID4 = 4,
68 TX_DESC_QSEL_TID5 = 5,
69 TX_DESC_QSEL_TID6 = 6,
70 TX_DESC_QSEL_TID7 = 7,
71 TX_DESC_QSEL_TID8 = 8,
72 TX_DESC_QSEL_TID9 = 9,
73 TX_DESC_QSEL_TID10 = 10,
74 TX_DESC_QSEL_TID11 = 11,
75 TX_DESC_QSEL_TID12 = 12,
76 TX_DESC_QSEL_TID13 = 13,
77 TX_DESC_QSEL_TID14 = 14,
78 TX_DESC_QSEL_TID15 = 15,
79 TX_DESC_QSEL_BEACON = 16,
80 TX_DESC_QSEL_HIGH = 17,
81 TX_DESC_QSEL_MGMT = 18,
82 TX_DESC_QSEL_H2C = 19,
83 };
84
85 enum rtw_rsvd_packet_type;
86
87 void rtw_tx(struct rtw_dev *rtwdev,
88 struct ieee80211_tx_control *control,
89 struct sk_buff *skb);
90 void rtw_txq_init(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
91 void rtw_txq_cleanup(struct rtw_dev *rtwdev, struct ieee80211_txq *txq);
92 void rtw_tx_work(struct work_struct *w);
93 void __rtw_tx_work(struct rtw_dev *rtwdev);
94 void rtw_tx_pkt_info_update(struct rtw_dev *rtwdev,
95 struct rtw_tx_pkt_info *pkt_info,
96 struct ieee80211_sta *sta,
97 struct sk_buff *skb);
98 void rtw_tx_fill_tx_desc(struct rtw_dev *rtwdev,
99 struct rtw_tx_pkt_info *pkt_info, struct sk_buff *skb);
100 void rtw_tx_report_enqueue(struct rtw_dev *rtwdev, struct sk_buff *skb, u8 sn);
101 void rtw_tx_report_handle(struct rtw_dev *rtwdev, struct sk_buff *skb, int src);
102 void rtw_tx_rsvd_page_pkt_info_update(struct rtw_dev *rtwdev,
103 struct rtw_tx_pkt_info *pkt_info,
104 struct sk_buff *skb,
105 enum rtw_rsvd_packet_type type);
106 struct sk_buff *
107 rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev,
108 struct rtw_tx_pkt_info *pkt_info,
109 u8 *buf, u32 size);
110 struct sk_buff *
111 rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev,
112 struct rtw_tx_pkt_info *pkt_info,
113 u8 *buf, u32 size);
114
115 enum rtw_tx_queue_type rtw_tx_ac_to_hwq(enum ieee80211_ac_numbers ac);
116 enum rtw_tx_queue_type rtw_tx_queue_mapping(struct sk_buff *skb);
117
118 static inline
fill_txdesc_checksum_common(u8 * txdesc,size_t words)119 void fill_txdesc_checksum_common(u8 *txdesc, size_t words)
120 {
121 __le16 chksum = 0;
122 __le16 *data = (__le16 *)(txdesc);
123 struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc;
124
125 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM);
126
127 while (words--)
128 chksum ^= *data++;
129
130 le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum),
131 RTW_TX_DESC_W7_TXDESC_CHECKSUM);
132 }
133
rtw_tx_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)134 static inline void rtw_tx_fill_txdesc_checksum(struct rtw_dev *rtwdev,
135 struct rtw_tx_pkt_info *pkt_info,
136 u8 *txdesc)
137 {
138 const struct rtw_chip_info *chip = rtwdev->chip;
139
140 chip->ops->fill_txdesc_checksum(rtwdev, pkt_info, txdesc);
141 }
142
143 #endif
144