xref: /linux/drivers/net/wireless/realtek/rtw89/phy.h (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_PHY_H__
6 #define __RTW89_PHY_H__
7 
8 #include "core.h"
9 
10 #define RTW89_BBMCU_ADDR_OFFSET	0x30000
11 #define RTW89_RF_ADDR_ADSEL_MASK  BIT(16)
12 
13 #define get_phy_headline(addr)		FIELD_GET(GENMASK(31, 28), addr)
14 #define PHY_HEADLINE_VALID	0xf
15 #define get_phy_target(addr)		FIELD_GET(GENMASK(27, 0), addr)
16 #define get_phy_compare(rfe, cv)	(FIELD_PREP(GENMASK(23, 16), rfe) | \
17 					 FIELD_PREP(GENMASK(7, 0), cv))
18 
19 #define get_phy_cond(addr)		FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr)		FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr)		FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr)		FIELD_GET(GENMASK(7, 0), addr)
23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24 #define PHY_COND_BRANCH_IF	0x8
25 #define PHY_COND_BRANCH_ELIF	0x9
26 #define PHY_COND_BRANCH_ELSE	0xa
27 #define PHY_COND_BRANCH_END	0xb
28 #define PHY_COND_CHECK		0x4
29 #define PHY_COND_DONT_CARE	0xff
30 
31 #define RA_MASK_CCK_RATES	GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES	GENMASK_ULL(11, 4)
33 #define RA_MASK_SUBCCK_RATES	0x5ULL
34 #define RA_MASK_SUBOFDM_RATES	0x10ULL
35 #define RA_MASK_HT_1SS_RATES	GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES	GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES	GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES	GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES	GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES	GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES	GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES	GENMASK_ULL(45, 36)
43 #define RA_MASK_VHT_4SS_RATES	GENMASK_ULL(57, 48)
44 #define RA_MASK_VHT_RATES	GENMASK_ULL(57, 12)
45 #define RA_MASK_HE_1SS_RATES	GENMASK_ULL(23, 12)
46 #define RA_MASK_HE_2SS_RATES	GENMASK_ULL(35, 24)
47 #define RA_MASK_HE_3SS_RATES	GENMASK_ULL(47, 36)
48 #define RA_MASK_HE_4SS_RATES	GENMASK_ULL(59, 48)
49 #define RA_MASK_HE_RATES	GENMASK_ULL(59, 12)
50 #define RA_MASK_EHT_1SS_RATES	GENMASK_ULL(27, 12)
51 #define RA_MASK_EHT_2SS_RATES	GENMASK_ULL(43, 28)
52 #define RA_MASK_EHT_3SS_RATES	GENMASK_ULL(59, 44)
53 #define RA_MASK_EHT_4SS_RATES	GENMASK_ULL(62, 60)
54 #define RA_MASK_EHT_1SS_MCS0_11	GENMASK_ULL(23, 12)
55 #define RA_MASK_EHT_2SS_MCS0_11	GENMASK_ULL(39, 28)
56 #define RA_MASK_EHT_3SS_MCS0_11	GENMASK_ULL(55, 44)
57 #define RA_MASK_EHT_4SS_MCS0_11	GENMASK_ULL(62, 60)
58 #define RA_MASK_EHT_RATES	GENMASK_ULL(62, 12)
59 
60 #define CFO_TRK_ENABLE_TH (2 << 2)
61 #define CFO_TRK_STOP_TH_4 (30 << 2)
62 #define CFO_TRK_STOP_TH_3 (20 << 2)
63 #define CFO_TRK_STOP_TH_2 (10 << 2)
64 #define CFO_TRK_STOP_TH_1 (03 << 2)
65 #define CFO_TRK_STOP_TH (2 << 2)
66 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
67 #define CFO_PERIOD_CNT 15
68 #define CFO_BOUND 64
69 #define CFO_TP_UPPER 100
70 #define CFO_TP_LOWER 50
71 #define CFO_COMP_PERIOD 250
72 #define CFO_COMP_WEIGHT 8
73 #define MAX_CFO_TOLERANCE 30
74 #define CFO_TF_CNT_TH 300
75 
76 #define UL_TB_TF_CNT_L2H_TH 100
77 #define UL_TB_TF_CNT_H2L_TH 70
78 
79 #define ANTDIV_TRAINNING_CNT 2
80 #define ANTDIV_TRAINNING_INTVL 30
81 #define ANTDIV_DELAY 110
82 #define ANTDIV_TP_DIFF_TH_HIGH 100
83 #define ANTDIV_TP_DIFF_TH_LOW 5
84 #define ANTDIV_EVM_DIFF_TH 8
85 #define ANTDIV_RSSI_DIFF_TH 3
86 
87 #define CCX_MAX_PERIOD 2097
88 #define CCX_MAX_PERIOD_UNIT 32
89 #define MS_TO_4US_RATIO 250
90 #define ENV_MNTR_FAIL_DWORD 0xffffffff
91 #define ENV_MNTR_IFSCLM_HIS_MAX 127
92 #define PERMIL 1000
93 #define PERCENT 100
94 #define IFS_CLM_TH0_UPPER 64
95 #define IFS_CLM_TH_MUL 4
96 #define IFS_CLM_TH_START_IDX 0
97 
98 #define TIA0_GAIN_A 12
99 #define TIA0_GAIN_G 16
100 #define LNA0_GAIN (-24)
101 #define U4_MAX_BIT 3
102 #define U8_MAX_BIT 7
103 #define DIG_GAIN_SHIFT 2
104 #define DIG_GAIN 8
105 
106 #define LNA_IDX_MAX 6
107 #define LNA_IDX_MIN 0
108 #define TIA_IDX_MAX 1
109 #define TIA_IDX_MIN 0
110 #define RXB_IDX_MAX 31
111 #define RXB_IDX_MIN 0
112 
113 #define IGI_RSSI_MAX 110
114 #define PD_TH_MAX_RSSI 70
115 #define PD_TH_MIN_RSSI 8
116 #define CCKPD_TH_MIN_RSSI (-18)
117 #define PD_TH_BW160_CMP_VAL 9
118 #define PD_TH_BW80_CMP_VAL 6
119 #define PD_TH_BW40_CMP_VAL 3
120 #define PD_TH_BW20_CMP_VAL 0
121 #define PD_TH_CMP_VAL 3
122 #define PD_TH_SB_FLTR_CMP_VAL 7
123 
124 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
125 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
126 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
127 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
128 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
129 
130 #define EDCCA_MAX 249
131 #define EDCCA_TH_L2H_LB 66
132 #define EDCCA_TH_REF 3
133 #define EDCCA_HL_DIFF_NORMAL 8
134 #define RSSI_UNIT_CONVER 110
135 #define EDCCA_UNIT_CONVER 128
136 #define EDCCA_PWROFST_DEFAULT 18
137 
138 enum rtw89_phy_c2h_ra_func {
139 	RTW89_PHY_C2H_FUNC_STS_RPT,
140 	RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
141 	RTW89_PHY_C2H_FUNC_TXSTS,
142 	RTW89_PHY_C2H_FUNC_RA_MAX,
143 };
144 
145 enum rtw89_phy_c2h_rfk_log_func {
146 	RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0,
147 	RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1,
148 	RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2,
149 	RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3,
150 	RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4,
151 	RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5,
152 
153 	RTW89_PHY_C2H_RFK_LOG_FUNC_NUM,
154 };
155 
156 enum rtw89_phy_c2h_rfk_report_func {
157 	RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0,
158 	RTW89_PHY_C2H_RFK_LOG_TAS_PWR = 6,
159 };
160 
161 enum rtw89_phy_c2h_dm_func {
162 	RTW89_PHY_C2H_DM_FUNC_FW_TEST,
163 	RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
164 	RTW89_PHY_C2H_DM_FUNC_SIGB,
165 	RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
166 	RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
167 	RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc,
168 	RTW89_PHY_C2H_DM_FUNC_NUM,
169 };
170 
171 enum rtw89_phy_c2h_class {
172 	RTW89_PHY_C2H_CLASS_RUA,
173 	RTW89_PHY_C2H_CLASS_RA,
174 	RTW89_PHY_C2H_CLASS_DM,
175 	RTW89_PHY_C2H_RFK_LOG = 0x8,
176 	RTW89_PHY_C2H_RFK_REPORT = 0x9,
177 	RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
178 	RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
179 	RTW89_PHY_C2H_CLASS_MAX,
180 };
181 
182 enum rtw89_env_monitor_result_level {
183 	RTW89_PHY_ENV_MON_CCX_FAIL = 0,
184 	RTW89_PHY_ENV_MON_NHM = BIT(0),
185 	RTW89_PHY_ENV_MON_CLM = BIT(1),
186 	RTW89_PHY_ENV_MON_FAHM = BIT(2),
187 	RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
188 	RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
189 };
190 
191 #define CCX_US_BASE_RATIO 4
192 enum rtw89_ccx_unit {
193 	RTW89_CCX_4_US = 0,
194 	RTW89_CCX_8_US = 1,
195 	RTW89_CCX_16_US = 2,
196 	RTW89_CCX_32_US = 3
197 };
198 
199 enum rtw89_phy_status_ie_type {
200 	RTW89_PHYSTS_IE00_CMN_CCK			= 0,
201 	RTW89_PHYSTS_IE01_CMN_OFDM			= 1,
202 	RTW89_PHYSTS_IE02_CMN_EXT_AX			= 2,
203 	RTW89_PHYSTS_IE03_CMN_EXT_SEG_1			= 3,
204 	RTW89_PHYSTS_IE04_CMN_EXT_PATH_A		= 4,
205 	RTW89_PHYSTS_IE05_CMN_EXT_PATH_B		= 5,
206 	RTW89_PHYSTS_IE06_CMN_EXT_PATH_C		= 6,
207 	RTW89_PHYSTS_IE07_CMN_EXT_PATH_D		= 7,
208 	RTW89_PHYSTS_IE08_FTR_CH			= 8,
209 	RTW89_PHYSTS_IE09_FTR_0				= 9,
210 	RTW89_PHYSTS_IE10_FTR_PLCP_EXT			= 10,
211 	RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM		= 11,
212 	RTW89_PHYSTS_IE12_MU_EIGEN_INFO			= 12,
213 	RTW89_PHYSTS_IE13_DL_MU_DEF			= 13,
214 	RTW89_PHYSTS_IE14_TB_UL_CQI			= 14,
215 	RTW89_PHYSTS_IE15_TB_UL_DEF			= 15,
216 	RTW89_PHYSTS_IE16_RSVD16			= 16,
217 	RTW89_PHYSTS_IE17_TB_UL_CTRL			= 17,
218 	RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN		= 18,
219 	RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN		= 19,
220 	RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0	= 20,
221 	RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1	= 21,
222 	RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC		= 22,
223 	RTW89_PHYSTS_IE23_RSVD23			= 23,
224 	RTW89_PHYSTS_IE24_OFDM_TD_PATH_A		= 24,
225 	RTW89_PHYSTS_IE25_OFDM_TD_PATH_B		= 25,
226 	RTW89_PHYSTS_IE26_OFDM_TD_PATH_C		= 26,
227 	RTW89_PHYSTS_IE27_OFDM_TD_PATH_D		= 27,
228 	RTW89_PHYSTS_IE28_DBG_CCK_PATH_A		= 28,
229 	RTW89_PHYSTS_IE29_DBG_CCK_PATH_B		= 29,
230 	RTW89_PHYSTS_IE30_DBG_CCK_PATH_C		= 30,
231 	RTW89_PHYSTS_IE31_DBG_CCK_PATH_D		= 31,
232 
233 	/* keep last */
234 	RTW89_PHYSTS_IE_NUM,
235 	RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
236 };
237 
238 enum rtw89_phy_status_bitmap {
239 	RTW89_TD_SEARCH_FAIL  = 0,
240 	RTW89_BRK_BY_TX_PKT   = 1,
241 	RTW89_CCA_SPOOF       = 2,
242 	RTW89_OFDM_BRK        = 3,
243 	RTW89_CCK_BRK         = 4,
244 	RTW89_DL_MU_SPOOFING  = 5,
245 	RTW89_HE_MU           = 6,
246 	RTW89_VHT_MU          = 7,
247 	RTW89_UL_TB_SPOOFING  = 8,
248 	RTW89_RSVD_9          = 9,
249 	RTW89_TRIG_BASE_PPDU  = 10,
250 	RTW89_CCK_PKT         = 11,
251 	RTW89_LEGACY_OFDM_PKT = 12,
252 	RTW89_HT_PKT          = 13,
253 	RTW89_VHT_PKT         = 14,
254 	RTW89_HE_PKT          = 15,
255 	RTW89_EHT_PKT         = 16,
256 
257 	RTW89_PHYSTS_BITMAP_NUM
258 };
259 
260 enum rtw89_dig_gain_type {
261 	RTW89_DIG_GAIN_LNA_G = 0,
262 	RTW89_DIG_GAIN_TIA_G = 1,
263 	RTW89_DIG_GAIN_LNA_A = 2,
264 	RTW89_DIG_GAIN_TIA_A = 3,
265 	RTW89_DIG_GAIN_MAX = 4
266 };
267 
268 enum rtw89_dig_gain_lna_idx {
269 	RTW89_DIG_GAIN_LNA_IDX1 = 1,
270 	RTW89_DIG_GAIN_LNA_IDX2 = 2,
271 	RTW89_DIG_GAIN_LNA_IDX3 = 3,
272 	RTW89_DIG_GAIN_LNA_IDX4 = 4,
273 	RTW89_DIG_GAIN_LNA_IDX5 = 5,
274 	RTW89_DIG_GAIN_LNA_IDX6 = 6
275 };
276 
277 enum rtw89_dig_gain_tia_idx {
278 	RTW89_DIG_GAIN_TIA_IDX0 = 0,
279 	RTW89_DIG_GAIN_TIA_IDX1 = 1
280 };
281 
282 enum rtw89_tssi_bandedge_cfg {
283 	RTW89_TSSI_BANDEDGE_FLAT,
284 	RTW89_TSSI_BANDEDGE_LOW,
285 	RTW89_TSSI_BANDEDGE_MID,
286 	RTW89_TSSI_BANDEDGE_HIGH,
287 
288 	RTW89_TSSI_CFG_NUM,
289 };
290 
291 enum rtw89_tssi_sbw_idx {
292 	RTW89_TSSI_SBW20,
293 	RTW89_TSSI_SBW40_0,
294 	RTW89_TSSI_SBW40_1,
295 	RTW89_TSSI_SBW80_0,
296 	RTW89_TSSI_SBW80_1,
297 	RTW89_TSSI_SBW80_2,
298 	RTW89_TSSI_SBW80_3,
299 	RTW89_TSSI_SBW160_0,
300 	RTW89_TSSI_SBW160_1,
301 	RTW89_TSSI_SBW160_2,
302 	RTW89_TSSI_SBW160_3,
303 	RTW89_TSSI_SBW160_4,
304 	RTW89_TSSI_SBW160_5,
305 	RTW89_TSSI_SBW160_6,
306 	RTW89_TSSI_SBW160_7,
307 
308 	RTW89_TSSI_SBW_NUM,
309 };
310 
311 struct rtw89_txpwr_byrate_cfg {
312 	enum rtw89_band band;
313 	enum rtw89_nss nss;
314 	enum rtw89_rate_section rs;
315 	u8 shf;
316 	u8 len;
317 	u32 data;
318 };
319 
320 struct rtw89_txpwr_track_cfg {
321 	const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
322 	const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
323 	const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
324 	const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
325 	const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
326 	const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
327 	const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
328 	const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
329 	const s8 *delta_swingidx_2gb_n;
330 	const s8 *delta_swingidx_2gb_p;
331 	const s8 *delta_swingidx_2ga_n;
332 	const s8 *delta_swingidx_2ga_p;
333 	const s8 *delta_swingidx_2g_cck_b_n;
334 	const s8 *delta_swingidx_2g_cck_b_p;
335 	const s8 *delta_swingidx_2g_cck_a_n;
336 	const s8 *delta_swingidx_2g_cck_a_p;
337 };
338 
339 struct rtw89_phy_dig_gain_cfg {
340 	const struct rtw89_reg_def *table;
341 	u8 size;
342 };
343 
344 struct rtw89_phy_dig_gain_table {
345 	const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
346 	const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
347 	const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
348 	const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
349 };
350 
351 struct rtw89_phy_tssi_dbw_table {
352 	u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
353 };
354 
355 struct rtw89_phy_reg3_tbl {
356 	const struct rtw89_reg3_def *reg3;
357 	int size;
358 };
359 
360 #define DECLARE_PHY_REG3_TBL(_name)			\
361 const struct rtw89_phy_reg3_tbl _name ## _tbl = {	\
362 	.reg3 = _name,					\
363 	.size = ARRAY_SIZE(_name),			\
364 }
365 
366 struct rtw89_nbi_reg_def {
367 	struct rtw89_reg_def notch1_idx;
368 	struct rtw89_reg_def notch1_frac_idx;
369 	struct rtw89_reg_def notch1_en;
370 	struct rtw89_reg_def notch2_idx;
371 	struct rtw89_reg_def notch2_frac_idx;
372 	struct rtw89_reg_def notch2_en;
373 };
374 
375 struct rtw89_ccx_regs {
376 	u32 setting_addr;
377 	u32 edcca_opt_mask;
378 	u32 measurement_trig_mask;
379 	u32 trig_opt_mask;
380 	u32 en_mask;
381 	u32 ifs_cnt_addr;
382 	u32 ifs_clm_period_mask;
383 	u32 ifs_clm_cnt_unit_mask;
384 	u32 ifs_clm_cnt_clear_mask;
385 	u32 ifs_collect_en_mask;
386 	u32 ifs_t1_addr;
387 	u32 ifs_t1_th_h_mask;
388 	u32 ifs_t1_en_mask;
389 	u32 ifs_t1_th_l_mask;
390 	u32 ifs_t2_addr;
391 	u32 ifs_t2_th_h_mask;
392 	u32 ifs_t2_en_mask;
393 	u32 ifs_t2_th_l_mask;
394 	u32 ifs_t3_addr;
395 	u32 ifs_t3_th_h_mask;
396 	u32 ifs_t3_en_mask;
397 	u32 ifs_t3_th_l_mask;
398 	u32 ifs_t4_addr;
399 	u32 ifs_t4_th_h_mask;
400 	u32 ifs_t4_en_mask;
401 	u32 ifs_t4_th_l_mask;
402 	u32 ifs_clm_tx_cnt_addr;
403 	u32 ifs_clm_edcca_excl_cca_fa_mask;
404 	u32 ifs_clm_tx_cnt_msk;
405 	u32 ifs_clm_cca_addr;
406 	u32 ifs_clm_ofdmcca_excl_fa_mask;
407 	u32 ifs_clm_cckcca_excl_fa_mask;
408 	u32 ifs_clm_fa_addr;
409 	u32 ifs_clm_ofdm_fa_mask;
410 	u32 ifs_clm_cck_fa_mask;
411 	u32 ifs_his_addr;
412 	u32 ifs_t4_his_mask;
413 	u32 ifs_t3_his_mask;
414 	u32 ifs_t2_his_mask;
415 	u32 ifs_t1_his_mask;
416 	u32 ifs_avg_l_addr;
417 	u32 ifs_t2_avg_mask;
418 	u32 ifs_t1_avg_mask;
419 	u32 ifs_avg_h_addr;
420 	u32 ifs_t4_avg_mask;
421 	u32 ifs_t3_avg_mask;
422 	u32 ifs_cca_l_addr;
423 	u32 ifs_t2_cca_mask;
424 	u32 ifs_t1_cca_mask;
425 	u32 ifs_cca_h_addr;
426 	u32 ifs_t4_cca_mask;
427 	u32 ifs_t3_cca_mask;
428 	u32 ifs_total_addr;
429 	u32 ifs_cnt_done_mask;
430 	u32 ifs_total_mask;
431 };
432 
433 struct rtw89_physts_regs {
434 	u32 setting_addr;
435 	u32 dis_trigger_fail_mask;
436 	u32 dis_trigger_brk_mask;
437 };
438 
439 struct rtw89_cfo_regs {
440 	u32 comp;
441 	u32 weighting_mask;
442 	u32 comp_seg0;
443 	u32 valid_0_mask;
444 };
445 
446 enum rtw89_bandwidth_section_num_ax {
447 	RTW89_BW20_SEC_NUM_AX = 8,
448 	RTW89_BW40_SEC_NUM_AX = 4,
449 	RTW89_BW80_SEC_NUM_AX = 2,
450 };
451 
452 enum rtw89_bandwidth_section_num_be {
453 	RTW89_BW20_SEC_NUM_BE = 16,
454 	RTW89_BW40_SEC_NUM_BE = 8,
455 	RTW89_BW80_SEC_NUM_BE = 4,
456 	RTW89_BW160_SEC_NUM_BE = 2,
457 };
458 
459 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40
460 
461 struct rtw89_txpwr_limit_ax {
462 	s8 cck_20m[RTW89_BF_NUM];
463 	s8 cck_40m[RTW89_BF_NUM];
464 	s8 ofdm[RTW89_BF_NUM];
465 	s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM];
466 	s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM];
467 	s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM];
468 	s8 mcs_160m[RTW89_BF_NUM];
469 	s8 mcs_40m_0p5[RTW89_BF_NUM];
470 	s8 mcs_40m_2p5[RTW89_BF_NUM];
471 };
472 
473 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76
474 
475 struct rtw89_txpwr_limit_be {
476 	s8 cck_20m[RTW89_BF_NUM];
477 	s8 cck_40m[RTW89_BF_NUM];
478 	s8 ofdm[RTW89_BF_NUM];
479 	s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM];
480 	s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM];
481 	s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM];
482 	s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM];
483 	s8 mcs_320m[RTW89_BF_NUM];
484 	s8 mcs_40m_0p5[RTW89_BF_NUM];
485 	s8 mcs_40m_2p5[RTW89_BF_NUM];
486 	s8 mcs_40m_4p5[RTW89_BF_NUM];
487 	s8 mcs_40m_6p5[RTW89_BF_NUM];
488 };
489 
490 #define RTW89_RU_SEC_NUM_AX 8
491 
492 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24
493 
494 struct rtw89_txpwr_limit_ru_ax {
495 	s8 ru26[RTW89_RU_SEC_NUM_AX];
496 	s8 ru52[RTW89_RU_SEC_NUM_AX];
497 	s8 ru106[RTW89_RU_SEC_NUM_AX];
498 };
499 
500 #define RTW89_RU_SEC_NUM_BE 16
501 
502 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80
503 
504 struct rtw89_txpwr_limit_ru_be {
505 	s8 ru26[RTW89_RU_SEC_NUM_BE];
506 	s8 ru52[RTW89_RU_SEC_NUM_BE];
507 	s8 ru106[RTW89_RU_SEC_NUM_BE];
508 	s8 ru52_26[RTW89_RU_SEC_NUM_BE];
509 	s8 ru106_26[RTW89_RU_SEC_NUM_BE];
510 };
511 
512 struct rtw89_phy_rfk_log_fmt {
513 	const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
514 };
515 
516 struct rtw89_phy_gen_def {
517 	u32 cr_base;
518 	const struct rtw89_ccx_regs *ccx;
519 	const struct rtw89_physts_regs *physts;
520 	const struct rtw89_cfo_regs *cfo;
521 	u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
522 	void (*config_bb_gain)(struct rtw89_dev *rtwdev,
523 			       const struct rtw89_reg2_def *reg,
524 			       enum rtw89_rf_path rf_path,
525 			       void *extra_data);
526 	void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev);
527 	void (*bb_wrap_init)(struct rtw89_dev *rtwdev);
528 	void (*ch_info_init)(struct rtw89_dev *rtwdev);
529 
530 	void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
531 				 const struct rtw89_chan *chan,
532 				 enum rtw89_phy_idx phy_idx);
533 	void (*set_txpwr_offset)(struct rtw89_dev *rtwdev,
534 				 const struct rtw89_chan *chan,
535 				 enum rtw89_phy_idx phy_idx);
536 	void (*set_txpwr_limit)(struct rtw89_dev *rtwdev,
537 				const struct rtw89_chan *chan,
538 				enum rtw89_phy_idx phy_idx);
539 	void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev,
540 				   const struct rtw89_chan *chan,
541 				   enum rtw89_phy_idx phy_idx);
542 };
543 
544 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
545 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be;
546 
rtw89_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)547 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
548 				    u32 addr, u8 data)
549 {
550 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
551 
552 	rtw89_write8(rtwdev, addr + phy->cr_base, data);
553 }
554 
rtw89_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)555 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
556 				     u32 addr, u16 data)
557 {
558 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
559 
560 	rtw89_write16(rtwdev, addr + phy->cr_base, data);
561 }
562 
rtw89_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)563 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
564 				     u32 addr, u32 data)
565 {
566 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
567 
568 	rtw89_write32(rtwdev, addr + phy->cr_base, data);
569 }
570 
rtw89_phy_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits)571 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
572 					 u32 addr, u32 bits)
573 {
574 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
575 
576 	rtw89_write32_set(rtwdev, addr + phy->cr_base, bits);
577 }
578 
rtw89_phy_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits)579 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
580 					 u32 addr, u32 bits)
581 {
582 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
583 
584 	rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits);
585 }
586 
rtw89_phy_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)587 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
588 					  u32 addr, u32 mask, u32 data)
589 {
590 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
591 
592 	rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data);
593 }
594 
rtw89_phy_read8(struct rtw89_dev * rtwdev,u32 addr)595 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
596 {
597 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
598 
599 	return rtw89_read8(rtwdev, addr + phy->cr_base);
600 }
601 
rtw89_phy_read16(struct rtw89_dev * rtwdev,u32 addr)602 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
603 {
604 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
605 
606 	return rtw89_read16(rtwdev, addr + phy->cr_base);
607 }
608 
rtw89_phy_read32(struct rtw89_dev * rtwdev,u32 addr)609 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
610 {
611 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
612 
613 	return rtw89_read32(rtwdev, addr + phy->cr_base);
614 }
615 
rtw89_phy_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)616 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
617 					u32 addr, u32 mask)
618 {
619 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
620 
621 	return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
622 }
623 
rtw89_bbmcu_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data,enum rtw89_phy_idx phy_idx)624 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev,
625 				       u32 addr, u32 data, enum rtw89_phy_idx phy_idx)
626 {
627 	if (phy_idx && addr < 0x10000)
628 		addr += 0x20000;
629 
630 	rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data);
631 }
632 
633 static inline
rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)634 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
635 {
636 	switch (subband) {
637 	default:
638 	case RTW89_CH_2G:
639 		return RTW89_GAIN_OFFSET_2G_OFDM;
640 	case RTW89_CH_5G_BAND_1:
641 		return RTW89_GAIN_OFFSET_5G_LOW;
642 	case RTW89_CH_5G_BAND_3:
643 		return RTW89_GAIN_OFFSET_5G_MID;
644 	case RTW89_CH_5G_BAND_4:
645 		return RTW89_GAIN_OFFSET_5G_HIGH;
646 	case RTW89_CH_6G_BAND_IDX0:
647 		return RTW89_GAIN_OFFSET_6G_L0;
648 	case RTW89_CH_6G_BAND_IDX1:
649 		return RTW89_GAIN_OFFSET_6G_L1;
650 	case RTW89_CH_6G_BAND_IDX2:
651 		return RTW89_GAIN_OFFSET_6G_M0;
652 	case RTW89_CH_6G_BAND_IDX3:
653 		return RTW89_GAIN_OFFSET_6G_M1;
654 	case RTW89_CH_6G_BAND_IDX4:
655 		return RTW89_GAIN_OFFSET_6G_H0;
656 	case RTW89_CH_6G_BAND_IDX5:
657 		return RTW89_GAIN_OFFSET_6G_H1;
658 	case RTW89_CH_6G_BAND_IDX6:
659 		return RTW89_GAIN_OFFSET_6G_UH0;
660 	case RTW89_CH_6G_BAND_IDX7:
661 		return RTW89_GAIN_OFFSET_6G_UH1;
662 	}
663 }
664 
665 static inline
rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)666 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
667 {
668 	switch (subband) {
669 	default:
670 	case RTW89_CH_2G:
671 		return RTW89_BB_GAIN_BAND_2G;
672 	case RTW89_CH_5G_BAND_1:
673 		return RTW89_BB_GAIN_BAND_5G_L;
674 	case RTW89_CH_5G_BAND_3:
675 		return RTW89_BB_GAIN_BAND_5G_M;
676 	case RTW89_CH_5G_BAND_4:
677 		return RTW89_BB_GAIN_BAND_5G_H;
678 	case RTW89_CH_6G_BAND_IDX0:
679 	case RTW89_CH_6G_BAND_IDX1:
680 		return RTW89_BB_GAIN_BAND_6G_L;
681 	case RTW89_CH_6G_BAND_IDX2:
682 	case RTW89_CH_6G_BAND_IDX3:
683 		return RTW89_BB_GAIN_BAND_6G_M;
684 	case RTW89_CH_6G_BAND_IDX4:
685 	case RTW89_CH_6G_BAND_IDX5:
686 		return RTW89_BB_GAIN_BAND_6G_H;
687 	case RTW89_CH_6G_BAND_IDX6:
688 	case RTW89_CH_6G_BAND_IDX7:
689 		return RTW89_BB_GAIN_BAND_6G_UH;
690 	}
691 }
692 
693 static inline
rtw89_subband_to_gain_band_be(enum rtw89_subband subband)694 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband)
695 {
696 	switch (subband) {
697 	default:
698 	case RTW89_CH_2G:
699 		return RTW89_BB_GAIN_BAND_2G_BE;
700 	case RTW89_CH_5G_BAND_1:
701 		return RTW89_BB_GAIN_BAND_5G_L_BE;
702 	case RTW89_CH_5G_BAND_3:
703 		return RTW89_BB_GAIN_BAND_5G_M_BE;
704 	case RTW89_CH_5G_BAND_4:
705 		return RTW89_BB_GAIN_BAND_5G_H_BE;
706 	case RTW89_CH_6G_BAND_IDX0:
707 		return RTW89_BB_GAIN_BAND_6G_L0_BE;
708 	case RTW89_CH_6G_BAND_IDX1:
709 		return RTW89_BB_GAIN_BAND_6G_L1_BE;
710 	case RTW89_CH_6G_BAND_IDX2:
711 		return RTW89_BB_GAIN_BAND_6G_M0_BE;
712 	case RTW89_CH_6G_BAND_IDX3:
713 		return RTW89_BB_GAIN_BAND_6G_M1_BE;
714 	case RTW89_CH_6G_BAND_IDX4:
715 		return RTW89_BB_GAIN_BAND_6G_H0_BE;
716 	case RTW89_CH_6G_BAND_IDX5:
717 		return RTW89_BB_GAIN_BAND_6G_H1_BE;
718 	case RTW89_CH_6G_BAND_IDX6:
719 		return RTW89_BB_GAIN_BAND_6G_UH0_BE;
720 	case RTW89_CH_6G_BAND_IDX7:
721 		return RTW89_BB_GAIN_BAND_6G_UH1_BE;
722 	}
723 }
724 
725 struct rtw89_rfk_chan_desc {
726 	/* desc is valid iff ch is non-zero */
727 	u8 ch;
728 
729 	/* To avoid us from extending old chip code every time, each new
730 	 * field must be defined along with a bool flag in positivte way.
731 	 */
732 	bool has_band;
733 	u8 band;
734 	bool has_bw;
735 	u8 bw;
736 };
737 
738 enum rtw89_rfk_flag {
739 	RTW89_RFK_F_WRF = 0,
740 	RTW89_RFK_F_WM = 1,
741 	RTW89_RFK_F_WS = 2,
742 	RTW89_RFK_F_WC = 3,
743 	RTW89_RFK_F_DELAY = 4,
744 	RTW89_RFK_F_NUM,
745 };
746 
747 struct rtw89_rfk_tbl {
748 	const struct rtw89_reg5_def *defs;
749 	u32 size;
750 };
751 
752 #define RTW89_DECLARE_RFK_TBL(_name)		\
753 const struct rtw89_rfk_tbl _name ## _tbl = {	\
754 	.defs = _name,				\
755 	.size = ARRAY_SIZE(_name),		\
756 }
757 
758 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data)	\
759 	{.flag = RTW89_RFK_F_WRF,			\
760 	 .path = _path,					\
761 	 .addr = _addr,					\
762 	 .mask = _mask,					\
763 	 .data = _data,}
764 
765 #define RTW89_DECL_RFK_WM(_addr, _mask, _data)	\
766 	{.flag = RTW89_RFK_F_WM,		\
767 	 .addr = _addr,				\
768 	 .mask = _mask,				\
769 	 .data = _data,}
770 
771 #define RTW89_DECL_RFK_WS(_addr, _mask)	\
772 	{.flag = RTW89_RFK_F_WS,	\
773 	 .addr = _addr,			\
774 	 .mask = _mask,}
775 
776 #define RTW89_DECL_RFK_WC(_addr, _mask)	\
777 	{.flag = RTW89_RFK_F_WC,	\
778 	 .addr = _addr,			\
779 	 .mask = _mask,}
780 
781 #define RTW89_DECL_RFK_DELAY(_data)	\
782 	{.flag = RTW89_RFK_F_DELAY,	\
783 	 .data = _data,}
784 
785 void
786 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
787 
788 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f)	\
789 	do {							\
790 		typeof(dev) __dev = (dev);			\
791 		if (cond)					\
792 			rtw89_rfk_parser(__dev, (tbl_t));	\
793 		else						\
794 			rtw89_rfk_parser(__dev, (tbl_f));	\
795 	} while (0)
796 
797 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
798 			      const struct rtw89_phy_reg3_tbl *tbl);
799 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
800 		      const struct rtw89_chan *chan,
801 		      enum rtw89_bandwidth dbw);
802 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
803 		      enum rtw89_bandwidth dbw);
804 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
805 		      u32 addr, u32 mask);
806 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
807 			 u32 addr, u32 mask);
808 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
809 			 u32 addr, u32 mask);
810 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
811 			u32 addr, u32 mask, u32 data);
812 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
813 			   u32 addr, u32 mask, u32 data);
814 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
815 			   u32 addr, u32 mask, u32 data);
816 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
817 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
818 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
819 				const struct rtw89_reg2_def *reg,
820 				enum rtw89_rf_path rf_path,
821 				void *extra_data);
822 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
823 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev);
824 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
825 			   u32 data, enum rtw89_phy_idx phy_idx);
826 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
827 			       enum rtw89_phy_idx phy_idx);
828 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
829 			       enum rtw89_phy_idx phy_idx);
830 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
831 			 enum rtw89_phy_idx phy_idx);
832 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
833 			   struct rtw89_txpwr_byrate *head,
834 			   const struct rtw89_rate_desc *desc);
835 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
836 			       const struct rtw89_rate_desc *rate_desc);
837 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev);
838 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
839 				  const struct rtw89_chan *chan);
840 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
841 			 const struct rtw89_chan *chan);
842 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
843 				 const struct rtw89_txpwr_table *tbl);
844 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
845 			      u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
846 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
847 				 u8 ru, u8 ntx, u8 ch);
848 
rtw89_phy_preinit_rf_nctl(struct rtw89_dev * rtwdev)849 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev)
850 {
851 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
852 
853 	phy->preinit_rf_nctl(rtwdev);
854 }
855 
rtw89_phy_bb_wrap_init(struct rtw89_dev * rtwdev)856 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev)
857 {
858 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
859 
860 	if (phy->bb_wrap_init)
861 		phy->bb_wrap_init(rtwdev);
862 }
863 
rtw89_phy_ch_info_init(struct rtw89_dev * rtwdev)864 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev)
865 {
866 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
867 
868 	if (phy->ch_info_init)
869 		phy->ch_info_init(rtwdev);
870 }
871 
872 static inline
rtw89_phy_set_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)873 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
874 				const struct rtw89_chan *chan,
875 				enum rtw89_phy_idx phy_idx)
876 {
877 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
878 
879 	phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
880 }
881 
882 static inline
rtw89_phy_set_txpwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)883 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
884 				const struct rtw89_chan *chan,
885 				enum rtw89_phy_idx phy_idx)
886 {
887 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
888 
889 	phy->set_txpwr_offset(rtwdev, chan, phy_idx);
890 }
891 
892 static inline
rtw89_phy_set_txpwr_limit(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)893 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
894 			       const struct rtw89_chan *chan,
895 			       enum rtw89_phy_idx phy_idx)
896 {
897 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
898 
899 	phy->set_txpwr_limit(rtwdev, chan, phy_idx);
900 }
901 
902 static inline
rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)903 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
904 				  const struct rtw89_chan *chan,
905 				  enum rtw89_phy_idx phy_idx)
906 {
907 	const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
908 
909 	phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx);
910 }
911 
rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev * rtwdev,s8 txpwr_rf)912 static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf)
913 {
914 	const struct rtw89_chip_info *chip = rtwdev->chip;
915 
916 	return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
917 }
918 
rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev * rtwdev,s8 txpwr_bb)919 static inline s8 rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_bb)
920 {
921 	const struct rtw89_chip_info *chip = rtwdev->chip;
922 
923 	return txpwr_bb >> (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
924 }
925 
rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev * rtwdev,s8 txpwr_rf)926 static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
927 {
928 	const struct rtw89_chip_info *chip = rtwdev->chip;
929 
930 	return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
931 }
932 
rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev * rtwdev,s8 dbm)933 static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
934 {
935 	const struct rtw89_chip_info *chip = rtwdev->chip;
936 
937 	return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
938 }
939 
rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev * rtwdev,s8 txpwr_mac)940 static inline s16 rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_mac)
941 {
942 	const struct rtw89_chip_info *chip = rtwdev->chip;
943 
944 	return txpwr_mac << (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
945 }
946 
rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev * rtwdev,s8 txpwr_mac)947 static inline s16 rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_mac)
948 {
949 	const struct rtw89_chip_info *chip = rtwdev->chip;
950 
951 	return txpwr_mac << (chip->txpwr_factor_bb - chip->txpwr_factor_mac);
952 }
953 
954 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link);
955 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
956 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
957 			     u32 changed);
958 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
959 				  struct rtw89_sta_link *rtwsta_link,
960 				  u32 changed);
961 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
962 				struct ieee80211_vif *vif,
963 				const struct cfg80211_bitrate_mask *mask);
964 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
965 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
966 			  u32 len, u8 class, u8 func);
967 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
968 				    enum rtw89_phy_idx phy_idx,
969 				    unsigned int ms);
970 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
971 				enum rtw89_phy_idx phy_idx,
972 				const struct rtw89_chan *chan,
973 				enum rtw89_tssi_mode tssi_mode,
974 				unsigned int ms);
975 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
976 			       enum rtw89_phy_idx phy_idx,
977 			       const struct rtw89_chan *chan,
978 			       unsigned int ms);
979 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
980 			       enum rtw89_phy_idx phy_idx,
981 			       const struct rtw89_chan *chan,
982 			       unsigned int ms);
983 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
984 				  enum rtw89_phy_idx phy_idx,
985 				  const struct rtw89_chan *chan,
986 				  unsigned int ms);
987 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
988 				enum rtw89_phy_idx phy_idx,
989 				const struct rtw89_chan *chan,
990 				unsigned int ms);
991 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
992 				 enum rtw89_phy_idx phy_idx,
993 				 const struct rtw89_chan *chan,
994 				 bool is_chl_k, unsigned int ms);
995 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
996 					       enum rtw89_phy_idx phy,
997 					       const struct rtw89_chan *chan,
998 					       struct rtw89_h2c_rf_tssi *h2c);
999 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
1000 					      enum rtw89_phy_idx phy,
1001 					      const struct rtw89_chan *chan,
1002 					      struct rtw89_h2c_rf_tssi *h2c);
1003 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
1004 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work);
1005 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
1006 			 struct rtw89_rx_phy_ppdu *phy_ppdu);
1007 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
1008 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
1009 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1010 			    u32 val);
1011 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1012 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
1013 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev);
1014 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore);
1015 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
1016 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
1017 			    struct rtw89_rx_phy_ppdu *phy_ppdu);
1018 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
1019 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work);
1020 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
1021 			     struct rtw89_vif_link *rtwvif_link);
1022 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
1023 					  enum rtw89_mac_idx mac_idx,
1024 					  enum rtw89_tssi_bandedge_cfg bandedge_cfg);
1025 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1026 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
1027 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band);
1028 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
1029 			   u8 *ch, enum nl80211_band *band);
1030 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
1031 			    struct rtw89_bb_ctx *bb, bool scan);
1032 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev);
1033 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1034 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
1035 					   enum rtw89_phy_idx phy_idx);
1036 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
1037 					 enum rtw89_phy_idx phy_idx);
1038 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
1039 			 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
1040 			 const struct rtw89_chan *target_chan);
1041 
1042 #endif
1043