1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "reg.h"
10
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
15 #define HFC_PAGE_UNIT 64
16 #define RPWM_TRY_CNT 3
17
18 enum rtw89_mac_hwmod_sel {
19 RTW89_DMAC_SEL = 0,
20 RTW89_CMAC_SEL = 1,
21
22 RTW89_MAC_INVALID,
23 };
24
25 enum rtw89_mac_fwd_target {
26 RTW89_FWD_DONT_CARE = 0,
27 RTW89_FWD_TO_HOST = 1,
28 RTW89_FWD_TO_WLAN_CPU = 2
29 };
30
31 enum rtw89_mac_wd_dma_intvl {
32 RTW89_MAC_WD_DMA_INTVL_0S,
33 RTW89_MAC_WD_DMA_INTVL_256NS,
34 RTW89_MAC_WD_DMA_INTVL_512NS,
35 RTW89_MAC_WD_DMA_INTVL_768NS,
36 RTW89_MAC_WD_DMA_INTVL_1US,
37 RTW89_MAC_WD_DMA_INTVL_1_5US,
38 RTW89_MAC_WD_DMA_INTVL_2US,
39 RTW89_MAC_WD_DMA_INTVL_4US,
40 RTW89_MAC_WD_DMA_INTVL_8US,
41 RTW89_MAC_WD_DMA_INTVL_16US,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
43 };
44
45 enum rtw89_mac_multi_tag_num {
46 RTW89_MAC_TAG_NUM_1,
47 RTW89_MAC_TAG_NUM_2,
48 RTW89_MAC_TAG_NUM_3,
49 RTW89_MAC_TAG_NUM_4,
50 RTW89_MAC_TAG_NUM_5,
51 RTW89_MAC_TAG_NUM_6,
52 RTW89_MAC_TAG_NUM_7,
53 RTW89_MAC_TAG_NUM_8,
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
55 };
56
57 enum rtw89_mac_lbc_tmr {
58 RTW89_MAC_LBC_TMR_8US = 0,
59 RTW89_MAC_LBC_TMR_16US,
60 RTW89_MAC_LBC_TMR_32US,
61 RTW89_MAC_LBC_TMR_64US,
62 RTW89_MAC_LBC_TMR_128US,
63 RTW89_MAC_LBC_TMR_256US,
64 RTW89_MAC_LBC_TMR_512US,
65 RTW89_MAC_LBC_TMR_1MS,
66 RTW89_MAC_LBC_TMR_2MS,
67 RTW89_MAC_LBC_TMR_4MS,
68 RTW89_MAC_LBC_TMR_8MS,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
70 };
71
72 enum rtw89_mac_cpuio_op_cmd_type {
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
74 CPUIO_OP_CMD_GET_NEXT_PID = 1,
75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
77 CPUIO_OP_CMD_DEQ = 8,
78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
80 };
81
82 enum rtw89_mac_wde_dle_port_id {
83 WDE_DLE_PORT_ID_DISPATCH = 0,
84 WDE_DLE_PORT_ID_PKTIN = 1,
85 WDE_DLE_PORT_ID_CMAC0 = 3,
86 WDE_DLE_PORT_ID_CMAC1 = 4,
87 WDE_DLE_PORT_ID_CPU_IO = 6,
88 WDE_DLE_PORT_ID_WDRLS = 7,
89 WDE_DLE_PORT_ID_END = 8
90 };
91
92 enum rtw89_mac_wde_dle_queid_wdrls {
93 WDE_DLE_QUEID_TXOK = 0,
94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
96 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
97 WDE_DLE_QUEID_NO_REPORT = 4
98 };
99
100 enum rtw89_mac_ple_dle_port_id {
101 PLE_DLE_PORT_ID_DISPATCH = 0,
102 PLE_DLE_PORT_ID_MPDU = 1,
103 PLE_DLE_PORT_ID_SEC = 2,
104 PLE_DLE_PORT_ID_CMAC0 = 3,
105 PLE_DLE_PORT_ID_CMAC1 = 4,
106 PLE_DLE_PORT_ID_WDRLS = 5,
107 PLE_DLE_PORT_ID_CPU_IO = 6,
108 PLE_DLE_PORT_ID_PLRLS = 7,
109 PLE_DLE_PORT_ID_END = 8
110 };
111
112 enum rtw89_mac_ple_dle_queid_plrls {
113 PLE_DLE_QUEID_NO_REPORT = 0x0
114 };
115
116 enum rtw89_machdr_frame_type {
117 RTW89_MGNT = 0,
118 RTW89_CTRL = 1,
119 RTW89_DATA = 2,
120 };
121
122 enum rtw89_mac_dle_dfi_type {
123 DLE_DFI_TYPE_FREEPG = 0,
124 DLE_DFI_TYPE_QUOTA = 1,
125 DLE_DFI_TYPE_PAGELLT = 2,
126 DLE_DFI_TYPE_PKTINFO = 3,
127 DLE_DFI_TYPE_PREPKTLLT = 4,
128 DLE_DFI_TYPE_NXTPKTLLT = 5,
129 DLE_DFI_TYPE_QLNKTBL = 6,
130 DLE_DFI_TYPE_QEMPTY = 7,
131 };
132
133 enum rtw89_mac_dle_wde_quota_id {
134 WDE_QTAID_HOST_IF = 0,
135 WDE_QTAID_WLAN_CPU = 1,
136 WDE_QTAID_DATA_CPU = 2,
137 WDE_QTAID_PKTIN = 3,
138 WDE_QTAID_CPUIO = 4,
139 };
140
141 enum rtw89_mac_dle_ple_quota_id {
142 PLE_QTAID_B0_TXPL = 0,
143 PLE_QTAID_B1_TXPL = 1,
144 PLE_QTAID_C2H = 2,
145 PLE_QTAID_H2C = 3,
146 PLE_QTAID_WLAN_CPU = 4,
147 PLE_QTAID_MPDU = 5,
148 PLE_QTAID_CMAC0_RX = 6,
149 PLE_QTAID_CMAC1_RX = 7,
150 PLE_QTAID_CMAC1_BBRPT = 8,
151 PLE_QTAID_WDRLS = 9,
152 PLE_QTAID_CPUIO = 10,
153 };
154
155 enum rtw89_mac_dle_ctrl_type {
156 DLE_CTRL_TYPE_WDE = 0,
157 DLE_CTRL_TYPE_PLE = 1,
158 DLE_CTRL_TYPE_NUM = 2,
159 };
160
161 enum rtw89_mac_ax_l0_to_l1_event {
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
164 MAC_AX_L0_TO_L1_RLS_PKID = 2,
165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
169 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
170 };
171
172 enum rtw89_mac_phy_rpt_size {
173 MAC_AX_PHY_RPT_SIZE_0 = 0,
174 MAC_AX_PHY_RPT_SIZE_8 = 1,
175 MAC_AX_PHY_RPT_SIZE_16 = 2,
176 MAC_AX_PHY_RPT_SIZE_24 = 3,
177 };
178
179 enum rtw89_mac_hdr_cnv_size {
180 MAC_AX_HDR_CNV_SIZE_0 = 0,
181 MAC_AX_HDR_CNV_SIZE_32 = 1,
182 MAC_AX_HDR_CNV_SIZE_64 = 2,
183 MAC_AX_HDR_CNV_SIZE_96 = 3,
184 };
185
186 enum rtw89_mac_wow_fw_status {
187 WOWLAN_NOT_READY = 0x00,
188 WOWLAN_SLEEP_READY = 0x01,
189 WOWLAN_RESUME_READY = 0x02,
190 };
191
192 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
193
194 enum rtw89_mac_dbg_port_sel {
195 /* CMAC 0 related */
196 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
197 RTW89_DBG_PORT_SEL_SCH_C0,
198 RTW89_DBG_PORT_SEL_TMAC_C0,
199 RTW89_DBG_PORT_SEL_RMAC_C0,
200 RTW89_DBG_PORT_SEL_RMACST_C0,
201 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
202 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
203 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
204 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
205 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
206 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
207 /* CMAC 1 related */
208 RTW89_DBG_PORT_SEL_PTCL_C1,
209 RTW89_DBG_PORT_SEL_SCH_C1,
210 RTW89_DBG_PORT_SEL_TMAC_C1,
211 RTW89_DBG_PORT_SEL_RMAC_C1,
212 RTW89_DBG_PORT_SEL_RMACST_C1,
213 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
214 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
215 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
216 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
217 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
218 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
219 /* DLE related */
220 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
221 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
222 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
223 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
224 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
225 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
226 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
227 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
228 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
229 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
230 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
231 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
232 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
233 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
234 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
235 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
236 RTW89_DBG_PORT_SEL_PKTINFO,
237 /* DISPATCHER related */
238 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
239 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
240 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
241 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
242 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
243 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
244 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
245 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
246 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
247 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
248 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
249 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
250 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
251 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
252 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
253 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
254 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
255 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
256 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
257 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
258 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
259 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
260 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
261 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
262 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
263 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
264 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
265 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
266 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
267 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
268 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
269 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
270 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
271 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
272 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
273 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
274 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
275 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
276 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
277 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
278 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
279 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
280 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
281 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
282 /* PCIE related */
283 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
284 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
285 RTW89_DBG_PORT_SEL_PCIE_CVT,
286 RTW89_DBG_PORT_SEL_PCIE_CXPL,
287 RTW89_DBG_PORT_SEL_PCIE_IO,
288 RTW89_DBG_PORT_SEL_PCIE_MISC,
289 RTW89_DBG_PORT_SEL_PCIE_MISC2,
290
291 /* keep last */
292 RTW89_DBG_PORT_SEL_LAST,
293 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
294 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
295 };
296
297 /* SRAM mem dump */
298 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
299 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
300
301 #define AXIDMA_BASE_ADDR 0x18006000
302 #define STA_SCHED_BASE_ADDR 0x18808000
303 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
304 #define SECURITY_CAM_BASE_ADDR 0x18814000
305 #define WOW_CAM_BASE_ADDR 0x18815000
306 #define CMAC_TBL_BASE_ADDR 0x18840000
307 #define ADDR_CAM_BASE_ADDR 0x18850000
308 #define BSSID_CAM_BASE_ADDR 0x18853000
309 #define BA_CAM_BASE_ADDR 0x18854000
310 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
311 #define SHARED_BUF_BASE_ADDR 0x18700000
312 #define DMAC_TBL_BASE_ADDR 0x18800000
313 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
314 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
315 #define TXD_FIFO_0_BASE_ADDR 0x18856200
316 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
317 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
318 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
319 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
320 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
321 #define CPU_LOCAL_BASE_ADDR 0x18003000
322
323 #define WD_PAGE_BASE_ADDR_BE 0x0
324 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
325 #define AXIDMA_BASE_ADDR_BE 0x18006000
326 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
327 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
328 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
329 #define STA_SCHED_BASE_ADDR_BE 0x18818000
330 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
331 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
332 #define SEC_CAM_BASE_ADDR_BE 0x18824000
333 #define WOW_CAM_BASE_ADDR_BE 0x18828000
334 #define MLD_TBL_BASE_ADDR_BE 0x18829000
335 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
336 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
337 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
338 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
339 #define BA_CAM_BASE_ADDR_BE 0x18859000
340 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
341 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
342 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
343 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
344 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
345 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
346 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
347
348 #define CCTL_INFO_SIZE 32
349
350 enum rtw89_mac_mem_sel {
351 RTW89_MAC_MEM_AXIDMA,
352 RTW89_MAC_MEM_SHARED_BUF,
353 RTW89_MAC_MEM_DMAC_TBL,
354 RTW89_MAC_MEM_SHCUT_MACHDR,
355 RTW89_MAC_MEM_STA_SCHED,
356 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
357 RTW89_MAC_MEM_SECURITY_CAM,
358 RTW89_MAC_MEM_WOW_CAM,
359 RTW89_MAC_MEM_CMAC_TBL,
360 RTW89_MAC_MEM_ADDR_CAM,
361 RTW89_MAC_MEM_BA_CAM,
362 RTW89_MAC_MEM_BCN_IE_CAM0,
363 RTW89_MAC_MEM_BCN_IE_CAM1,
364 RTW89_MAC_MEM_TXD_FIFO_0,
365 RTW89_MAC_MEM_TXD_FIFO_1,
366 RTW89_MAC_MEM_TXDATA_FIFO_0,
367 RTW89_MAC_MEM_TXDATA_FIFO_1,
368 RTW89_MAC_MEM_CPU_LOCAL,
369 RTW89_MAC_MEM_BSSID_CAM,
370 RTW89_MAC_MEM_TXD_FIFO_0_V1,
371 RTW89_MAC_MEM_TXD_FIFO_1_V1,
372 RTW89_MAC_MEM_WD_PAGE,
373
374 /* keep last */
375 RTW89_MAC_MEM_NUM,
376 };
377
378 enum rtw89_rpwm_req_pwr_state {
379 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
380 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
381 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
382 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
383 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
384 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
385 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
386 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
387 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
388 };
389
390 struct rtw89_pwr_cfg {
391 u16 addr;
392 u8 cv_msk;
393 u8 intf_msk;
394 u8 base:4;
395 u8 cmd:4;
396 u8 msk;
397 u8 val;
398 };
399
400 enum rtw89_mac_c2h_ofld_func {
401 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
402 RTW89_MAC_C2H_FUNC_READ_RSP,
403 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
404 RTW89_MAC_C2H_FUNC_BCN_RESEND,
405 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
406 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
407 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
408 RTW89_MAC_C2H_FUNC_TX_DUTY_RPT = 0xa,
409 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
410 RTW89_MAC_C2H_FUNC_OFLD_MAX,
411 };
412
413 enum rtw89_mac_c2h_info_func {
414 RTW89_MAC_C2H_FUNC_REC_ACK,
415 RTW89_MAC_C2H_FUNC_DONE_ACK,
416 RTW89_MAC_C2H_FUNC_C2H_LOG,
417 RTW89_MAC_C2H_FUNC_BCN_CNT,
418 RTW89_MAC_C2H_FUNC_INFO_MAX,
419 };
420
421 enum rtw89_mac_c2h_mcc_func {
422 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
423 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
424 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
425 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
426
427 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
428 };
429
430 enum rtw89_mac_c2h_mrc_func {
431 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
432 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
433
434 NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
435 };
436
437 enum rtw89_mac_c2h_wow_func {
438 RTW89_MAC_C2H_FUNC_AOAC_REPORT,
439
440 NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
441 };
442
443 enum rtw89_mac_c2h_ap_func {
444 RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY = 0,
445
446 NUM_OF_RTW89_MAC_C2H_FUNC_AP,
447 };
448
449 enum rtw89_mac_c2h_class {
450 RTW89_MAC_C2H_CLASS_INFO = 0x0,
451 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
452 RTW89_MAC_C2H_CLASS_TWT = 0x2,
453 RTW89_MAC_C2H_CLASS_WOW = 0x3,
454 RTW89_MAC_C2H_CLASS_MCC = 0x4,
455 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
456 RTW89_MAC_C2H_CLASS_MRC = 0xe,
457 RTW89_MAC_C2H_CLASS_AP = 0x18,
458 RTW89_MAC_C2H_CLASS_MAX,
459 };
460
461 enum rtw89_mac_mcc_status {
462 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
463 RTW89_MAC_MCC_START_GROUP_OK = 1,
464 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
465 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
466 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
467 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
468 RTW89_MAC_MCC_TXNULL0_OK = 6,
469 RTW89_MAC_MCC_TXNULL1_OK = 7,
470
471 RTW89_MAC_MCC_SWITCH_EARLY = 10,
472 RTW89_MAC_MCC_TBTT = 11,
473 RTW89_MAC_MCC_DURATION_START = 12,
474 RTW89_MAC_MCC_DURATION_END = 13,
475
476 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
477 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
478 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
479 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
480 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
481 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
482 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
483 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
484 };
485
486 enum rtw89_mac_mrc_status {
487 RTW89_MAC_MRC_START_SCH_OK = 0,
488 RTW89_MAC_MRC_STOP_SCH_OK = 1,
489 RTW89_MAC_MRC_DEL_SCH_OK = 2,
490 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
491 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
492 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
493 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
494 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
495 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
496 RTW89_MAC_MRC_MALLOC_FAIL = 22,
497 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
498 RTW89_MAC_MRC_TXNULL0_FAIL = 24,
499 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
500 };
501
502 struct rtw89_mac_ax_coex {
503 #define RTW89_MAC_AX_COEX_RTK_MODE 0
504 #define RTW89_MAC_AX_COEX_CSR_MODE 1
505 u8 pta_mode;
506 #define RTW89_MAC_AX_COEX_INNER 0
507 #define RTW89_MAC_AX_COEX_OUTPUT 1
508 #define RTW89_MAC_AX_COEX_INPUT 2
509 u8 direction;
510 };
511
512 struct rtw89_mac_ax_plt {
513 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
514 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
515 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
516 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
517 u8 band;
518 u8 tx;
519 u8 rx;
520 };
521
522 enum rtw89_mac_bf_rrsc_rate {
523 RTW89_MAC_BF_RRSC_6M = 0,
524 RTW89_MAC_BF_RRSC_9M = 1,
525 RTW89_MAC_BF_RRSC_12M,
526 RTW89_MAC_BF_RRSC_18M,
527 RTW89_MAC_BF_RRSC_24M,
528 RTW89_MAC_BF_RRSC_36M,
529 RTW89_MAC_BF_RRSC_48M,
530 RTW89_MAC_BF_RRSC_54M,
531 RTW89_MAC_BF_RRSC_HT_MSC0,
532 RTW89_MAC_BF_RRSC_HT_MSC1,
533 RTW89_MAC_BF_RRSC_HT_MSC2,
534 RTW89_MAC_BF_RRSC_HT_MSC3,
535 RTW89_MAC_BF_RRSC_HT_MSC4,
536 RTW89_MAC_BF_RRSC_HT_MSC5,
537 RTW89_MAC_BF_RRSC_HT_MSC6,
538 RTW89_MAC_BF_RRSC_HT_MSC7,
539 RTW89_MAC_BF_RRSC_VHT_MSC0,
540 RTW89_MAC_BF_RRSC_VHT_MSC1,
541 RTW89_MAC_BF_RRSC_VHT_MSC2,
542 RTW89_MAC_BF_RRSC_VHT_MSC3,
543 RTW89_MAC_BF_RRSC_VHT_MSC4,
544 RTW89_MAC_BF_RRSC_VHT_MSC5,
545 RTW89_MAC_BF_RRSC_VHT_MSC6,
546 RTW89_MAC_BF_RRSC_VHT_MSC7,
547 RTW89_MAC_BF_RRSC_HE_MSC0,
548 RTW89_MAC_BF_RRSC_HE_MSC1,
549 RTW89_MAC_BF_RRSC_HE_MSC2,
550 RTW89_MAC_BF_RRSC_HE_MSC3,
551 RTW89_MAC_BF_RRSC_HE_MSC4,
552 RTW89_MAC_BF_RRSC_HE_MSC5,
553 RTW89_MAC_BF_RRSC_HE_MSC6,
554 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
555 RTW89_MAC_BF_RRSC_MAX = 32
556 };
557
558 #define RTW89_R32_EA 0xEAEAEAEA
559 #define RTW89_R32_DEAD 0xDEADBEEF
560 #define MAC_REG_POOL_COUNT 10
561 #define ACCESS_CMAC(_addr) \
562 ({typeof(_addr) __addr = (_addr); \
563 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
564 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
565 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
566
567 #define PTCL_IDLE_POLL_CNT 10000
568 #define SW_CVR_DUR_US 8
569 #define SW_CVR_CNT 8
570
571 #define DLE_BOUND_UNIT (8 * 1024)
572 #define DLE_WAIT_CNT 2000
573 #define TRXCFG_WAIT_CNT 2000
574
575 #define RTW89_WDE_PG_64 64
576 #define RTW89_WDE_PG_128 128
577 #define RTW89_WDE_PG_256 256
578
579 #define S_AX_WDE_PAGE_SEL_64 0
580 #define S_AX_WDE_PAGE_SEL_128 1
581 #define S_AX_WDE_PAGE_SEL_256 2
582
583 #define RTW89_PLE_PG_64 64
584 #define RTW89_PLE_PG_128 128
585 #define RTW89_PLE_PG_256 256
586
587 #define S_AX_PLE_PAGE_SEL_64 0
588 #define S_AX_PLE_PAGE_SEL_128 1
589 #define S_AX_PLE_PAGE_SEL_256 2
590
591 #define B_CMAC0_MGQ_NORMAL BIT(2)
592 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
593 #define B_CMAC0_CPUMGQ BIT(4)
594 #define B_CMAC1_MGQ_NORMAL BIT(10)
595 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
596 #define B_CMAC1_CPUMGQ BIT(12)
597
598 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
599 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
600
601 #define QEMP_ACQ_GRP_MACID_NUM 8
602 #define QEMP_ACQ_GRP_QSEL_SH 4
603 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
604
605 #define SDIO_LOCAL_BASE_ADDR 0x80000000
606
607 #define PWR_CMD_WRITE 0
608 #define PWR_CMD_POLL 1
609 #define PWR_CMD_DELAY 2
610 #define PWR_CMD_END 3
611
612 #define PWR_INTF_MSK_SDIO BIT(0)
613 #define PWR_INTF_MSK_USB BIT(1)
614 #define PWR_INTF_MSK_PCIE BIT(2)
615 #define PWR_INTF_MSK_ALL 0x7
616
617 #define PWR_BASE_MAC 0
618 #define PWR_BASE_USB 1
619 #define PWR_BASE_PCIE 2
620 #define PWR_BASE_SDIO 3
621
622 #define PWR_CV_MSK_A BIT(0)
623 #define PWR_CV_MSK_B BIT(1)
624 #define PWR_CV_MSK_C BIT(2)
625 #define PWR_CV_MSK_D BIT(3)
626 #define PWR_CV_MSK_E BIT(4)
627 #define PWR_CV_MSK_F BIT(5)
628 #define PWR_CV_MSK_G BIT(6)
629 #define PWR_CV_MSK_TEST BIT(7)
630 #define PWR_CV_MSK_ALL 0xFF
631
632 #define PWR_DELAY_US 0
633 #define PWR_DELAY_MS 1
634
635 /* STA scheduler */
636 #define SS_MACID_SH 8
637 #define SS_TX_LEN_MSK 0x1FFFFF
638 #define SS_CTRL1_R_TX_LEN 5
639 #define SS_CTRL1_R_NEXT_LINK 20
640 #define SS_LINK_SIZE 256
641
642 /* MAC debug port */
643 #define TMAC_DBG_SEL_C0 0xA5
644 #define RMAC_DBG_SEL_C0 0xA6
645 #define TRXPTCL_DBG_SEL_C0 0xA7
646 #define TMAC_DBG_SEL_C1 0xB5
647 #define RMAC_DBG_SEL_C1 0xB6
648 #define TRXPTCL_DBG_SEL_C1 0xB7
649 #define FW_PROG_CNTR_DBG_SEL 0xF2
650 #define PCIE_TXDMA_DBG_SEL 0x30
651 #define PCIE_RXDMA_DBG_SEL 0x31
652 #define PCIE_CVT_DBG_SEL 0x32
653 #define PCIE_CXPL_DBG_SEL 0x33
654 #define PCIE_IO_DBG_SEL 0x37
655 #define PCIE_MISC_DBG_SEL 0x38
656 #define PCIE_MISC2_DBG_SEL 0x00
657 #define MAC_DBG_SEL 1
658 #define RMAC_CMAC_DBG_SEL 1
659
660 /* TRXPTCL dbg port sel */
661 #define TRXPTRL_DBG_SEL_TMAC 0
662 #define TRXPTRL_DBG_SEL_RMAC 1
663
664 struct rtw89_cpuio_ctrl {
665 u16 pkt_num;
666 u16 start_pktid;
667 u16 end_pktid;
668 u8 cmd_type;
669 u8 macid;
670 u8 src_pid;
671 u8 src_qid;
672 u8 dst_pid;
673 u8 dst_qid;
674 u16 pktid;
675 };
676
677 struct rtw89_mac_dbg_port_info {
678 u32 sel_addr;
679 u8 sel_byte;
680 u32 sel_msk;
681 u32 srt;
682 u32 end;
683 u32 rd_addr;
684 u8 rd_byte;
685 u32 rd_msk;
686 };
687
688 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
689 #define QLNKTBL_ADDR_INFO_SEL_0 0
690 #define QLNKTBL_ADDR_INFO_SEL_1 1
691 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
692 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
693
694 struct rtw89_mac_dle_dfi_ctrl {
695 enum rtw89_mac_dle_ctrl_type type;
696 u32 target;
697 u32 addr;
698 u32 out_data;
699 };
700
701 struct rtw89_mac_dle_dfi_quota {
702 enum rtw89_mac_dle_ctrl_type dle_type;
703 u32 qtaid;
704 u16 rsv_pgnum;
705 u16 use_pgnum;
706 };
707
708 struct rtw89_mac_dle_dfi_qempty {
709 enum rtw89_mac_dle_ctrl_type dle_type;
710 u32 grpsel;
711 u32 qempty;
712 };
713
714 enum rtw89_mac_dle_rsvd_qt_type {
715 DLE_RSVD_QT_MPDU_INFO,
716 DLE_RSVD_QT_B0_CSI,
717 DLE_RSVD_QT_B1_CSI,
718 DLE_RSVD_QT_B0_LMR,
719 DLE_RSVD_QT_B1_LMR,
720 DLE_RSVD_QT_B0_FTM,
721 DLE_RSVD_QT_B1_FTM,
722 };
723
724 struct rtw89_mac_dle_rsvd_qt_cfg {
725 u16 pktid;
726 u16 pg_num;
727 u32 size;
728 };
729
730 enum rtw89_mac_error_scenario {
731 RTW89_RXI300_ERROR = 1,
732 RTW89_WCPU_CPU_EXCEPTION = 2,
733 RTW89_WCPU_ASSERTION = 3,
734 };
735
736 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
737
738 /* Define DBG and recovery enum */
739 enum mac_ax_err_info {
740 /* Get error info */
741
742 /* L0 */
743 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
744 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
745 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
746 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
747
748 /* L1 */
749 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
750 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
751 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
752 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
753 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
754 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
755
756 /* L2 */
757 /* address hole (master) */
758 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
759 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
760 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
761 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
762 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
763 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
764 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
765 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
766
767 /* AHB bridge timeout (master) */
768 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
769 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
770 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
771 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
772 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
773 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
774 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
775 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
776
777 /* APB_SA bridge timeout (master + slave) */
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
844 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
845 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
846 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
847 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
848 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
849 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
850 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
851 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
852 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
853 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
854 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
855 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
856 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
857 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
858 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
859 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
860 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
861 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
862 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
863 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
864 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
865
866 /* APB_BBRF bridge timeout (master) */
867 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
868 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
869 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
870 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
871 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
872 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
873 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
874 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
875 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
876 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
877 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
878 MAC_AX_ERR_ASSERTION = 0x4000,
879 MAC_AX_ERR_RXI300 = 0x5000,
880 MAC_AX_GET_ERR_MAX,
881 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
882
883 /* set error info */
884 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
885 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
886 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
887 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
888 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
889 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
890 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
891 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
892 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
893 MAC_AX_SET_ERR_MAX,
894 };
895
896 struct rtw89_mac_size_set {
897 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
898 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
899 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
900 const struct rtw89_dle_size wde_size0;
901 const struct rtw89_dle_size wde_size0_v1;
902 const struct rtw89_dle_size wde_size4;
903 const struct rtw89_dle_size wde_size4_v1;
904 const struct rtw89_dle_size wde_size6;
905 const struct rtw89_dle_size wde_size7;
906 const struct rtw89_dle_size wde_size9;
907 const struct rtw89_dle_size wde_size18;
908 const struct rtw89_dle_size wde_size19;
909 const struct rtw89_dle_size wde_size23;
910 const struct rtw89_dle_size ple_size0;
911 const struct rtw89_dle_size ple_size0_v1;
912 const struct rtw89_dle_size ple_size3_v1;
913 const struct rtw89_dle_size ple_size4;
914 const struct rtw89_dle_size ple_size6;
915 const struct rtw89_dle_size ple_size8;
916 const struct rtw89_dle_size ple_size9;
917 const struct rtw89_dle_size ple_size18;
918 const struct rtw89_dle_size ple_size19;
919 const struct rtw89_wde_quota wde_qt0;
920 const struct rtw89_wde_quota wde_qt0_v1;
921 const struct rtw89_wde_quota wde_qt4;
922 const struct rtw89_wde_quota wde_qt6;
923 const struct rtw89_wde_quota wde_qt7;
924 const struct rtw89_wde_quota wde_qt17;
925 const struct rtw89_wde_quota wde_qt18;
926 const struct rtw89_wde_quota wde_qt23;
927 const struct rtw89_ple_quota ple_qt0;
928 const struct rtw89_ple_quota ple_qt1;
929 const struct rtw89_ple_quota ple_qt4;
930 const struct rtw89_ple_quota ple_qt5;
931 const struct rtw89_ple_quota ple_qt9;
932 const struct rtw89_ple_quota ple_qt13;
933 const struct rtw89_ple_quota ple_qt18;
934 const struct rtw89_ple_quota ple_qt44;
935 const struct rtw89_ple_quota ple_qt45;
936 const struct rtw89_ple_quota ple_qt46;
937 const struct rtw89_ple_quota ple_qt47;
938 const struct rtw89_ple_quota ple_qt57;
939 const struct rtw89_ple_quota ple_qt58;
940 const struct rtw89_ple_quota ple_qt59;
941 const struct rtw89_ple_quota ple_qt_52a_wow;
942 const struct rtw89_ple_quota ple_qt_52b_wow;
943 const struct rtw89_ple_quota ple_qt_52bt_wow;
944 const struct rtw89_ple_quota ple_qt_51b_wow;
945 const struct rtw89_rsvd_quota ple_rsvd_qt0;
946 const struct rtw89_rsvd_quota ple_rsvd_qt1;
947 const struct rtw89_dle_rsvd_size rsvd0_size0;
948 const struct rtw89_dle_rsvd_size rsvd1_size0;
949 };
950
951 extern const struct rtw89_mac_size_set rtw89_mac_size;
952
953 struct rtw89_mac_gen_def {
954 u32 band1_offset;
955 u32 filter_model_addr;
956 u32 indir_access_addr;
957 const u32 *mem_base_addrs;
958 u32 rx_fltr;
959 const struct rtw89_port_reg *port_base;
960 u32 agg_len_ht;
961 u32 ps_status;
962
963 struct rtw89_reg_def muedca_ctrl;
964 struct rtw89_reg_def bfee_ctrl;
965 struct rtw89_reg_def narrow_bw_ru_dis;
966 struct rtw89_reg_def wow_ctrl;
967 struct rtw89_reg_def agg_limit;
968 struct rtw89_reg_def txcnt_limit;
969
970 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
971 enum rtw89_mac_hwmod_sel sel);
972 int (*sys_init)(struct rtw89_dev *rtwdev);
973 int (*trx_init)(struct rtw89_dev *rtwdev);
974 void (*hci_func_en)(struct rtw89_dev *rtwdev);
975 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
976 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
977 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
978 void (*bf_assoc)(struct rtw89_dev *rtwdev,
979 struct rtw89_vif_link *rtwvif_link,
980 struct rtw89_sta_link *rtwsta_link);
981
982 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
983 enum rtw89_machdr_frame_type type,
984 enum rtw89_mac_fwd_target fwd_target,
985 u8 mac_idx);
986 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
987 void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
988
989 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
990 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
991 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
992 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
993 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
994 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
995 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
996 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
997 const struct rtw89_wde_quota *min_cfg,
998 const struct rtw89_wde_quota *max_cfg,
999 u16 ext_wde_min_qt_wcpu);
1000 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
1001 const struct rtw89_ple_quota *min_cfg,
1002 const struct rtw89_ple_quota *max_cfg);
1003 int (*set_cpuio)(struct rtw89_dev *rtwdev,
1004 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1005 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
1006
1007 void (*disable_cpu)(struct rtw89_dev *rtwdev);
1008 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
1009 bool dlfw, bool include_bb);
1010 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
1011 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
1012 void (*fwdl_secure_idmem_share_mode)(struct rtw89_dev *rtwdev, u8 mode);
1013 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
1014 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
1015 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
1016 int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev);
1017
1018 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1019 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
1020
1021 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
1022 enum rtw89_phy_idx phy_idx,
1023 u32 reg_base, u32 *cr);
1024
1025 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1026 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1027
1028 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
1029 void (*dump_err_status)(struct rtw89_dev *rtwdev,
1030 enum mac_ax_err_info err);
1031
1032 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
1033
1034 int (*add_chan_list)(struct rtw89_dev *rtwdev,
1035 struct rtw89_vif_link *rtwvif_link, bool connected);
1036 int (*add_chan_list_pno)(struct rtw89_dev *rtwdev,
1037 struct rtw89_vif_link *rtwvif_link);
1038 int (*scan_offload)(struct rtw89_dev *rtwdev,
1039 struct rtw89_scan_option *option,
1040 struct rtw89_vif_link *rtwvif_link,
1041 bool wowlan);
1042
1043 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
1044 };
1045
1046 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1047 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1048
1049 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)1050 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1051 {
1052 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1053
1054 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1055 }
1056
1057 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)1058 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1059 {
1060 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1061 }
1062
1063 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base)1064 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base)
1065 {
1066 u32 reg;
1067
1068 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1069 rtwvif_link->mac_idx);
1070 return rtw89_read32(rtwdev, reg);
1071 }
1072
1073 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask)1074 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1075 u32 base, u32 mask)
1076 {
1077 u32 reg;
1078
1079 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1080 rtwvif_link->mac_idx);
1081 return rtw89_read32_mask(rtwdev, reg, mask);
1082 }
1083
1084 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 data)1085 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, u32 base,
1086 u32 data)
1087 {
1088 u32 reg;
1089
1090 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1091 rtwvif_link->mac_idx);
1092 rtw89_write32(rtwdev, reg, data);
1093 }
1094
1095 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u32 data)1096 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1097 u32 base, u32 mask, u32 data)
1098 {
1099 u32 reg;
1100
1101 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1102 rtwvif_link->mac_idx);
1103 rtw89_write32_mask(rtwdev, reg, mask, data);
1104 }
1105
1106 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 mask,u16 data)1107 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1108 u32 base, u32 mask, u16 data)
1109 {
1110 u32 reg;
1111
1112 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1113 rtwvif_link->mac_idx);
1114 rtw89_write16_mask(rtwdev, reg, mask, data);
1115 }
1116
1117 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1118 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1119 u32 base, u32 bit)
1120 {
1121 u32 reg;
1122
1123 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1124 rtwvif_link->mac_idx);
1125 rtw89_write32_clr(rtwdev, reg, bit);
1126 }
1127
1128 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u16 bit)1129 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1130 u32 base, u16 bit)
1131 {
1132 u32 reg;
1133
1134 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1135 rtwvif_link->mac_idx);
1136 rtw89_write16_clr(rtwdev, reg, bit);
1137 }
1138
1139 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u32 base,u32 bit)1140 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1141 u32 base, u32 bit)
1142 {
1143 u32 reg;
1144
1145 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif_link->port,
1146 rtwvif_link->mac_idx);
1147 rtw89_write32_set(rtwdev, reg, bit);
1148 }
1149
1150 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev);
1151 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1152 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1153 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1154 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1155 enum rtw89_qta_mode ext_mode);
1156 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1157 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1158 enum rtw89_qta_mode mode);
1159 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1160 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1161 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1162 enum rtw89_mac_hwmod_sel sel)
1163 {
1164 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1165
1166 return mac->check_mac_en(rtwdev, band, sel);
1167 }
1168
1169 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1170 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1171 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1172 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1173 struct rtw89_mac_dle_dfi_quota *quota);
1174 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1175 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1176 struct rtw89_mac_dle_dfi_qempty *qempty);
1177 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1178 enum mac_ax_err_info err);
1179 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1180 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1181 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1182 struct rtw89_vif_link *rtwvif_link,
1183 struct rtw89_vif_link *rtwvif_src,
1184 u16 offset_tu);
1185 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
1186 u64 *tsf);
1187 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1188 struct rtw89_vif_link *rtwvif_link, bool en);
1189 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1190 struct rtw89_vif_link *rtwvif_link);
1191 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev,
1192 struct rtw89_vif_link *rtwvif_link);
1193 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1194 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1195 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
1196 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1197 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1198
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1199 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1200 {
1201 const struct rtw89_chip_info *chip = rtwdev->chip;
1202
1203 return chip->ops->enable_bb_rf(rtwdev);
1204 }
1205
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1206 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1207 {
1208 const struct rtw89_chip_info *chip = rtwdev->chip;
1209
1210 return chip->ops->disable_bb_rf(rtwdev);
1211 }
1212
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1213 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1214 {
1215 int ret;
1216
1217 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1218 return 0;
1219
1220 ret = rtw89_chip_disable_bb_rf(rtwdev);
1221 if (ret)
1222 return ret;
1223 ret = rtw89_chip_enable_bb_rf(rtwdev);
1224 if (ret)
1225 return ret;
1226
1227 return 0;
1228 }
1229
1230 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1231 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1232 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1233 u8 class, u8 func);
1234 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1235 u32 len, u8 class, u8 func);
1236 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1237 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1238 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1239 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1240 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1241 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1242 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1243 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1244 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1245 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1246 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1247
1248 static inline
rtw89_mac_cfg_phy_rpt(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1249 void rtw89_mac_cfg_phy_rpt(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1250 {
1251 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1252
1253 if (mac->cfg_phy_rpt)
1254 mac->cfg_phy_rpt(rtwdev, mac_idx, enable);
1255 }
1256
1257 static inline
rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev * rtwdev,bool enable)1258 void rtw89_mac_cfg_phy_rpt_bands(struct rtw89_dev *rtwdev, bool enable)
1259 {
1260 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_0, enable);
1261
1262 if (!rtwdev->dbcc_en)
1263 return;
1264
1265 rtw89_mac_cfg_phy_rpt(rtwdev, RTW89_MAC_1, enable);
1266 }
1267
1268 static inline
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1269 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1270 {
1271 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1272
1273 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1274 }
1275
1276 static inline
rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev * rtwdev,bool enable)1277 int rtw89_mac_cfg_ppdu_status_bands(struct rtw89_dev *rtwdev, bool enable)
1278 {
1279 int ret;
1280
1281 ret = rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, enable);
1282 if (ret)
1283 return ret;
1284
1285 if (!rtwdev->dbcc_en)
1286 return 0;
1287
1288 return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1289 }
1290
1291 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1292 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1293 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1294 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1295 const struct rtw89_mac_ax_coex *coex);
1296 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1297 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1298 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1299 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1300 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1301 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1302
1303 static inline
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1304 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1305 {
1306 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1307
1308 return mac->cfg_plt(rtwdev, plt);
1309 }
1310
1311 static inline
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)1312 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1313 {
1314 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1315
1316 return mac->get_plt_cnt(rtwdev, band);
1317 }
1318
1319 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1320 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1321 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1322 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1323 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1324 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1325 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1326 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1327
1328 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)1329 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev,
1330 struct rtw89_vif_link *rtwvif_link,
1331 struct rtw89_sta_link *rtwsta_link)
1332 {
1333 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1334
1335 if (mac->bf_assoc)
1336 mac->bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
1337 }
1338
1339 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
1340 struct rtw89_vif_link *rtwvif_link,
1341 struct rtw89_sta_link *rtwsta_link);
1342 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1343 struct ieee80211_bss_conf *conf);
1344 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1345 struct rtw89_sta_link *rtwsta_link,
1346 bool disconnect);
1347 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1348 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1349 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1350 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1351 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1352 struct rtw89_vif_link *rtwvif_link, bool en);
1353 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1354
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1355 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1356 {
1357 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1358 return;
1359
1360 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1361 return;
1362
1363 _rtw89_mac_bf_monitor_track(rtwdev);
1364 }
1365
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1366 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1367 enum rtw89_phy_idx phy_idx,
1368 u32 reg_base, u32 *val)
1369 {
1370 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1371 u32 cr;
1372
1373 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1374 return -EINVAL;
1375
1376 *val = rtw89_read32(rtwdev, cr);
1377 return 0;
1378 }
1379
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1380 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1381 enum rtw89_phy_idx phy_idx,
1382 u32 reg_base, u32 val)
1383 {
1384 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1385 u32 cr;
1386
1387 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1388 return -EINVAL;
1389
1390 rtw89_write32(rtwdev, cr, val);
1391 return 0;
1392 }
1393
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1394 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1395 enum rtw89_phy_idx phy_idx,
1396 u32 reg_base, u32 mask, u32 val)
1397 {
1398 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1399 u32 cr;
1400
1401 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1402 return -EINVAL;
1403
1404 rtw89_write32_mask(rtwdev, cr, mask, val);
1405 return 0;
1406 }
1407
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1408 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1409 bool enable)
1410 {
1411 const struct rtw89_chip_info *chip = rtwdev->chip;
1412
1413 if (enable)
1414 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1415 B_AX_HCI_TXDMA_EN);
1416 else
1417 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1418 B_AX_HCI_TXDMA_EN);
1419 }
1420
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1421 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1422 bool enable)
1423 {
1424 const struct rtw89_chip_info *chip = rtwdev->chip;
1425
1426 if (enable)
1427 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1428 B_AX_HCI_RXDMA_EN);
1429 else
1430 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1431 B_AX_HCI_RXDMA_EN);
1432 }
1433
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1434 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1435 bool enable)
1436 {
1437 const struct rtw89_chip_info *chip = rtwdev->chip;
1438
1439 if (enable)
1440 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1441 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1442 else
1443 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1444 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1445 }
1446
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1447 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1448 {
1449 u32 val;
1450
1451 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1452 B_AX_WLMAC_PWR_STE_MASK);
1453
1454 return !!val;
1455 }
1456
1457 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1458 bool resume, u32 tx_time);
1459 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link,
1460 u32 *tx_time);
1461 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1462 struct rtw89_sta_link *rtwsta_link,
1463 bool resume, u8 tx_retry);
1464 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1465 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry);
1466
1467 enum rtw89_mac_xtal_si_offset {
1468 XTAL0 = 0x0,
1469 XTAL3 = 0x3,
1470 XTAL_SI_XTAL_SC_XI = 0x04,
1471 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1472 XTAL_SI_XTAL_SC_XO = 0x05,
1473 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1474 XTAL_SI_XREF_MODE = 0x0B,
1475 XTAL_SI_PWR_CUT = 0x10,
1476 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1477 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1478 XTAL_SI_XTAL_DRV = 0x15,
1479 #define XTAL_SI_DRV_LATCH BIT(4)
1480 XTAL_SI_XTAL_PLL = 0x16,
1481 XTAL_SI_XTAL_XMD_2 = 0x24,
1482 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1483 XTAL_SI_XTAL_XMD_4 = 0x26,
1484 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1485 XTAL_SI_XREF_RF1 = 0x2D,
1486 XTAL_SI_XREF_RF2 = 0x2E,
1487 XTAL_SI_CV = 0x41,
1488 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1489 XTAL_SI_LOW_ADDR = 0x62,
1490 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1491 XTAL_SI_CTRL = 0x63,
1492 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1493 #define XTAL_SI_RDY BIT(5)
1494 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1495 XTAL_SI_READ_VAL = 0x7A,
1496 XTAL_SI_WL_RFC_S0 = 0x80,
1497 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1498 #define XTAL_SI_RF00 BIT(0)
1499 XTAL_SI_WL_RFC_S1 = 0x81,
1500 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1501 #define XTAL_SI_RF10 BIT(0)
1502 XTAL_SI_ANAPAR_WL = 0x90,
1503 #define XTAL_SI_SRAM2RFC BIT(7)
1504 #define XTAL_SI_GND_SHDN_WL BIT(6)
1505 #define XTAL_SI_SHDN_WL BIT(5)
1506 #define XTAL_SI_RFC2RF BIT(4)
1507 #define XTAL_SI_OFF_EI BIT(3)
1508 #define XTAL_SI_OFF_WEI BIT(2)
1509 #define XTAL_SI_PON_EI BIT(1)
1510 #define XTAL_SI_PON_WEI BIT(0)
1511 XTAL_SI_SRAM_CTRL = 0xA1,
1512 #define XTAL_SI_SRAM_DIS BIT(1)
1513 #define FULL_BIT_MASK GENMASK(7, 0)
1514 XTAL_SI_APBT = 0xD1,
1515 XTAL_SI_PLL = 0xE0,
1516 XTAL_SI_PLL_1 = 0xE1,
1517 };
1518
1519 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1520 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1521 {
1522 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1523
1524 return mac->write_xtal_si(rtwdev, offset, val, mask);
1525 }
1526
1527 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1528 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1529 {
1530 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1531
1532 return mac->read_xtal_si(rtwdev, offset, val);
1533 }
1534
1535 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1536 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1537 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1538 enum rtw89_mac_idx band);
1539 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1540 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1541 bool band1_en);
1542 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1543 enum rtw89_mac_dle_rsvd_qt_type type,
1544 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1545 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1546
1547 static inline
rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev * rtwdev,u8 mode)1548 void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
1549 {
1550 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1551
1552 if (!mac->fwdl_secure_idmem_share_mode)
1553 return;
1554
1555 return mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1556 }
1557 #endif
1558